^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #define CS4245_CHIP_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define CS4245_POWER_CTRL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define CS4245_DAC_CTRL_1 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define CS4245_ADC_CTRL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define CS4245_MCLK_FREQ 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define CS4245_SIGNAL_SEL 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define CS4245_PGA_B_CTRL 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CS4245_PGA_A_CTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CS4245_ANALOG_IN 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CS4245_DAC_A_CTRL 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CS4245_DAC_B_CTRL 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CS4245_DAC_CTRL_2 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CS4245_INT_STATUS 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CS4245_INT_MASK 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CS4245_INT_MODE_MSB 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CS4245_INT_MODE_LSB 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Chip ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CS4245_CHIP_PART_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CS4245_CHIP_REV_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Power Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CS4245_FREEZE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CS4245_PDN_MIC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CS4245_PDN_ADC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CS4245_PDN_DAC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CS4245_PDN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* DAC Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CS4245_DAC_FM_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CS4245_DAC_FM_SINGLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CS4245_DAC_FM_DOUBLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CS4245_DAC_FM_QUAD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CS4245_DAC_DIF_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CS4245_DAC_DIF_LJUST 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CS4245_DAC_DIF_I2S 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CS4245_DAC_DIF_RJUST_16 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CS4245_DAC_DIF_RJUST_24 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CS4245_RESERVED_1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CS4245_MUTE_DAC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CS4245_DEEMPH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CS4245_DAC_MASTER 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* ADC Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CS4245_ADC_FM_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CS4245_ADC_FM_SINGLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CS4245_ADC_FM_DOUBLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CS4245_ADC_FM_QUAD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CS4245_ADC_DIF_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CS4245_ADC_DIF_LJUST 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CS4245_ADC_DIF_I2S 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CS4245_MUTE_ADC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CS4245_HPF_FREEZE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CS4245_ADC_MASTER 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* MCLK Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CS4245_MCLK1_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CS4245_MCLK1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CS4245_MCLK2_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CS4245_MCLK2_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CS4245_MCLK_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CS4245_MCLK_1_5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CS4245_MCLK_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CS4245_MCLK_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CS4245_MCLK_4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Signal Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CS4245_A_OUT_SEL_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CS4245_A_OUT_SEL_HIZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CS4245_A_OUT_SEL_DAC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CS4245_A_OUT_SEL_PGA 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CS4245_LOOP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CS4245_ASYNCH 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Channel B/A PGA Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CS4245_PGA_GAIN_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* ADC Input Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CS4245_PGA_SOFT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CS4245_PGA_ZERO 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CS4245_SEL_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CS4245_SEL_MIC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CS4245_SEL_INPUT_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CS4245_SEL_INPUT_2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CS4245_SEL_INPUT_3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CS4245_SEL_INPUT_4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CS4245_SEL_INPUT_5 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CS4245_SEL_INPUT_6 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* DAC Channel A/B Volume Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CS4245_VOL_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* DAC Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CS4245_DAC_SOFT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CS4245_DAC_ZERO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CS4245_INVERT_DAC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CS4245_INT_ACTIVE_HIGH 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Interrupt Status/Mask/Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CS4245_ADC_CLK_ERR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CS4245_DAC_CLK_ERR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CS4245_ADC_OVFL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CS4245_ADC_UNDRFL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CS4245_SPI_ADDRESS_S (0x9e << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CS4245_SPI_WRITE_S (0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CS4245_SPI_ADDRESS 0x9e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CS4245_SPI_WRITE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CS4245_SPI_READ 1
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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