Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef CM9780_H_INCLUDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define CM9780_H_INCLUDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define CM9780_JACK		0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define CM9780_MIXER		0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define CM9780_GPIO_SETUP	0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define CM9780_GPIO_STATUS	0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* jack control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CM9780_RSOE		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CM9780_CBOE		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CM9780_SSOE		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CM9780_FROE		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CM9780_HP2FMICOE	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CM9780_CB2MICOE		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CM9780_FMIC2LI		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CM9780_FMIC2MIC		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CM9780_HP2LI		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CM9780_HP2MIC		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CM9780_MIC2LI		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CM9780_MIC2MIC		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CM9780_LI2LI		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CM9780_LI2MIC		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CM9780_LO2LI		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CM9780_LO2MIC		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* mixer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CM9780_BSTSEL		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CM9780_STRO_MIC		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CM9780_SPDI_FREX	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CM9780_SPDI_SSEX	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CM9780_SPDI_CBEX	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CM9780_SPDI_RSEX	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CM9780_MIX2FR		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CM9780_MIX2SS		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CM9780_MIX2CB		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CM9780_MIX2RS		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CM9780_MIX2FR_EX	0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CM9780_MIX2SS_EX	0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CM9780_MIX2CB_EX	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CM9780_MIX2RS_EX	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CM9780_P47_IO		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CM9780_PCBSW		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* GPIO setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CM9780_GPI0EN		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CM9780_GPI1EN		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CM9780_SENSE_P		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CM9780_LOCK_P		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CM9780_GPIO0P		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CM9780_GPIO1P		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CM9780_GPIO0IO		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CM9780_GPIO1IO		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* GPIO status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CM9780_GPO0		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CM9780_GPO1		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CM9780_GPIO0S		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CM9780_GPIO1S		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CM9780_GPII0S		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CM9780_GPII1S		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif