Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef AK4396_H_INCLUDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define AK4396_H_INCLUDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define AK4396_WRITE		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define AK4396_CONTROL_1	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define AK4396_CONTROL_2	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define AK4396_CONTROL_3	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define AK4396_LCH_ATT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define AK4396_RCH_ATT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AK4396_RSTN		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AK4396_DIF_MASK		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AK4396_DIF_16_LSB	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AK4396_DIF_20_LSB	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AK4396_DIF_24_MSB	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AK4396_DIF_24_I2S	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AK4396_DIF_24_LSB	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AK4396_ACKS		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AK4396_SMUTE		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AK4396_DEM_MASK		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AK4396_DEM_441		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AK4396_DEM_OFF		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AK4396_DEM_48		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AK4396_DEM_32		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AK4396_DFS_MASK		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AK4396_DFS_NORMAL	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AK4396_DFS_DOUBLE	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AK4396_DFS_QUAD		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AK4396_SLOW		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AK4396_DZFM		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AK4396_DZFE		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AK4396_DZFB		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AK4396_DCKB		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AK4396_DCKS		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AK4396_DSDM		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AK4396_D_P_MASK		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AK4396_PCM		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AK4396_DSD		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif