^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for NeoMagic 256AV and 256ZX chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on nm256_audio.c OSS driver in linux kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * The original author of OSS nm256 driver wishes to remain anonymous,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * so I just put my acknoledgment to him/her here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The original author's web page is found at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * http://www.uglx.org/sony.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CARD_NAME "NeoMagic 256AV/ZX"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_NAME "NM256"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_DESCRIPTION("NeoMagic NM256AV/ZX");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_SUPPORTED_DEVICE("{{NeoMagic,NM256AV},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "{NeoMagic,NM256ZX}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * some compile conditions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int index = SNDRV_DEFAULT_IDX1; /* Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int playback_bufsize = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int capture_bufsize = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static bool force_ac97; /* disabled as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int buffer_top; /* not specified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static bool use_cache; /* disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static bool vaio_hack; /* disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static bool reset_workaround;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static bool reset_workaround_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) module_param(index, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) module_param(id, charp, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) module_param(playback_bufsize, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_PARM_DESC(playback_bufsize, "DAC frame size in kB for " CARD_NAME " soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) module_param(capture_bufsize, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MODULE_PARM_DESC(capture_bufsize, "ADC frame size in kB for " CARD_NAME " soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) module_param(force_ac97, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MODULE_PARM_DESC(force_ac97, "Force to use AC97 codec for " CARD_NAME " soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) module_param(buffer_top, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MODULE_PARM_DESC(buffer_top, "Set the top address of audio buffer for " CARD_NAME " soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) module_param(use_cache, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MODULE_PARM_DESC(use_cache, "Enable the cache for coefficient table access.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) module_param(vaio_hack, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MODULE_PARM_DESC(vaio_hack, "Enable workaround for Sony VAIO notebooks.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) module_param(reset_workaround, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MODULE_PARM_DESC(reset_workaround, "Enable AC97 RESET workaround for some laptops.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) module_param(reset_workaround_2, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MODULE_PARM_DESC(reset_workaround_2, "Enable extended AC97 RESET workaround for some other laptops.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* just for backward compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static bool enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) module_param(enable, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * hw definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* The BIOS signature. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define NM_SIGNATURE 0x4e4d0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Signature mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define NM_SIG_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Size of the second memory area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define NM_PORT2_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* The base offset of the mixer in the second memory area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define NM_MIXER_OFFSET 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* The maximum size of a coefficient entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define NM_MAX_PLAYBACK_COEF_SIZE 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define NM_MAX_RECORD_COEF_SIZE 0x1260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* The interrupt register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define NM_INT_REG 0xa04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* And its bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define NM_PLAYBACK_INT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define NM_RECORD_INT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define NM_MISC_INT_1 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define NM_MISC_INT_2 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define NM_ACK_INT(chip, X) snd_nm256_writew(chip, NM_INT_REG, (X) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* The AV's "mixer ready" status bit and location. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define NM_MIXER_STATUS_OFFSET 0xa04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define NM_MIXER_READY_MASK 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define NM_MIXER_PRESENCE 0xa06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NM_PRESENCE_MASK 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define NM_PRESENCE_VALUE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * For the ZX. It uses the same interrupt register, but it holds 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * bits instead of 16.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define NM2_PLAYBACK_INT 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define NM2_RECORD_INT 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define NM2_MISC_INT_1 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define NM2_MISC_INT_2 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define NM2_ACK_INT(chip, X) snd_nm256_writel(chip, NM_INT_REG, (X))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* The ZX's "mixer ready" status bit and location. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define NM2_MIXER_STATUS_OFFSET 0xa06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define NM2_MIXER_READY_MASK 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* The playback registers start from here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define NM_PLAYBACK_REG_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* The record registers start from here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define NM_RECORD_REG_OFFSET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* The rate register is located 2 bytes from the start of the register area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define NM_RATE_REG_OFFSET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Mono/stereo flag, number of bits on playback, and rate mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define NM_RATE_STEREO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define NM_RATE_BITS_16 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define NM_RATE_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Playback enable register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define NM_PLAYBACK_ENABLE_REG (NM_PLAYBACK_REG_OFFSET + 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define NM_PLAYBACK_ENABLE_FLAG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define NM_PLAYBACK_ONESHOT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define NM_PLAYBACK_FREERUN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Mutes the audio output. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define NM_AUDIO_MUTE_REG (NM_PLAYBACK_REG_OFFSET + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define NM_AUDIO_MUTE_LEFT 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define NM_AUDIO_MUTE_RIGHT 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Recording enable register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define NM_RECORD_ENABLE_REG (NM_RECORD_REG_OFFSET + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define NM_RECORD_ENABLE_FLAG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define NM_RECORD_FREERUN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* coefficient buffer pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define NM_COEFF_START_OFFSET 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define NM_COEFF_END_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* DMA buffer offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define NM_RBUFFER_START (NM_RECORD_REG_OFFSET + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define NM_RBUFFER_END (NM_RECORD_REG_OFFSET + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define NM_RBUFFER_WMARK (NM_RECORD_REG_OFFSET + 0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define NM_RBUFFER_CURRP (NM_RECORD_REG_OFFSET + 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define NM_PBUFFER_START (NM_PLAYBACK_REG_OFFSET + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define NM_PBUFFER_END (NM_PLAYBACK_REG_OFFSET + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define NM_PBUFFER_WMARK (NM_PLAYBACK_REG_OFFSET + 0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define NM_PBUFFER_CURRP (NM_PLAYBACK_REG_OFFSET + 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct nm256_stream {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct nm256 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 buf; /* offset from chip->buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int bufsize; /* buffer size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void __iomem *bufptr; /* mapped pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long bufptr_addr; /* physical address of the mapped pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int dma_size; /* buffer size of the substream in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int period_size; /* period size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int periods; /* # of periods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int shift; /* bit shifts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int cur_period; /* current period # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct nm256 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) void __iomem *cport; /* control port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct resource *res_cport; /* its resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long cport_addr; /* physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void __iomem *buffer; /* buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct resource *res_buffer; /* its resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long buffer_addr; /* buffer phyiscal address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 buffer_start; /* start offset from pci resource 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 buffer_end; /* end offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 buffer_size; /* total buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 all_coeff_buf; /* coefficient buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 coeff_buf[2]; /* coefficient buffer for each stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int coeffs_current: 1; /* coeff. table is loaded? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned int use_cache: 1; /* use one big coef. table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int reset_workaround: 1; /* Workaround for some laptops to avoid freeze */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int reset_workaround_2: 1; /* Extended workaround for some other laptops to avoid freeze */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int in_resume: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int mixer_base; /* register offset of ac97 mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int mixer_status_offset; /* offset of mixer status reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int mixer_status_mask; /* bit mask to test the mixer status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int irq_acks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) irq_handler_t interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int badintrcount; /* counter to check bogus interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct mutex irq_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct nm256_stream streams[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct snd_ac97 *ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned short *ac97_regs; /* register caches, only for valid regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * include coefficient table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #include "nm256_coef.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * PCI ids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct pci_device_id snd_nm256_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MODULE_DEVICE_TABLE(pci, snd_nm256_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * lowlvel stuffs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static inline u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) snd_nm256_readb(struct nm256 *chip, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return readb(chip->cport + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static inline u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) snd_nm256_readw(struct nm256 *chip, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return readw(chip->cport + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static inline u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) snd_nm256_readl(struct nm256 *chip, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return readl(chip->cport + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) snd_nm256_writeb(struct nm256 *chip, int offset, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writeb(val, chip->cport + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) snd_nm256_writew(struct nm256 *chip, int offset, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) writew(val, chip->cport + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) snd_nm256_writel(struct nm256 *chip, int offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) writel(val, chip->cport + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) snd_nm256_write_buffer(struct nm256 *chip, const void *src, int offset, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) offset -= chip->buffer_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (offset < 0 || offset >= chip->buffer_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "write_buffer invalid offset = %d size = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) offset, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) memcpy_toio(chip->buffer + offset, src, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * coefficient handlers -- what a magic!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) snd_nm256_get_start_offset(int which)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u16 offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) while (which-- > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) offset += coefficient_sizes[which];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) snd_nm256_load_one_coefficient(struct nm256 *chip, int stream, u32 port, int which)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 coeff_buf = chip->coeff_buf[stream];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u16 offset = snd_nm256_get_start_offset(which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u16 size = coefficient_sizes[which];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) snd_nm256_write_buffer(chip, coefficients + offset, coeff_buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) snd_nm256_writel(chip, port, coeff_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* ??? Record seems to behave differently than playback. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) size--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) snd_nm256_writel(chip, port + 4, coeff_buf + size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) snd_nm256_load_coefficient(struct nm256 *chip, int stream, int number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* The enable register for the specified engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 poffset = (stream == SNDRV_PCM_STREAM_CAPTURE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) NM_RECORD_ENABLE_REG : NM_PLAYBACK_ENABLE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 addr = NM_COEFF_START_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) addr += (stream == SNDRV_PCM_STREAM_CAPTURE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) NM_RECORD_REG_OFFSET : NM_PLAYBACK_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (snd_nm256_readb(chip, poffset) & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "NM256: Engine was enabled while loading coefficients!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* The recording engine uses coefficient values 8-15. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) number &= 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) number += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (! chip->use_cache) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) snd_nm256_load_one_coefficient(chip, stream, addr, number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (! chip->coeffs_current) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) snd_nm256_write_buffer(chip, coefficients, chip->all_coeff_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) NM_TOTAL_COEFF_COUNT * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) chip->coeffs_current = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u32 base = chip->all_coeff_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u32 offset = snd_nm256_get_start_offset(number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 end_offset = offset + coefficient_sizes[number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) snd_nm256_writel(chip, addr, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) end_offset--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) snd_nm256_writel(chip, addr + 4, base + end_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* The actual rates supported by the card. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const unsigned int samplerates[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct snd_pcm_hw_constraint_list constraints_rates = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .count = ARRAY_SIZE(samplerates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .list = samplerates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * return the index of the target rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) snd_nm256_fixed_rate(unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (rate == samplerates[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * set sample rate and format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) snd_nm256_set_format(struct nm256 *chip, struct nm256_stream *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int rate_index = snd_nm256_fixed_rate(runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned char ratebits = (rate_index << 4) & NM_RATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) s->shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (snd_pcm_format_width(runtime->format) == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ratebits |= NM_RATE_BITS_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) s->shift++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (runtime->channels > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ratebits |= NM_RATE_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) s->shift++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) runtime->rate = samplerates[rate_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) switch (substream->stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case SNDRV_PCM_STREAM_PLAYBACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) snd_nm256_load_coefficient(chip, 0, rate_index); /* 0 = playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) snd_nm256_writeb(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) NM_PLAYBACK_REG_OFFSET + NM_RATE_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ratebits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case SNDRV_PCM_STREAM_CAPTURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) snd_nm256_load_coefficient(chip, 1, rate_index); /* 1 = record */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) snd_nm256_writeb(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) NM_RECORD_REG_OFFSET + NM_RATE_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ratebits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* acquire interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int snd_nm256_acquire_irq(struct nm256 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mutex_lock(&chip->irq_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (chip->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (request_irq(chip->pci->irq, chip->interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) KBUILD_MODNAME, chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) "unable to grab IRQ %d\n", chip->pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mutex_unlock(&chip->irq_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) chip->irq = chip->pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) chip->card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) chip->irq_acks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mutex_unlock(&chip->irq_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* release interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static void snd_nm256_release_irq(struct nm256 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) mutex_lock(&chip->irq_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (chip->irq_acks > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) chip->irq_acks--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (chip->irq_acks == 0 && chip->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) chip->card->sync_irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) mutex_unlock(&chip->irq_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * start / stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* update the watermark (current period) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static void snd_nm256_pcm_mark(struct nm256 *chip, struct nm256_stream *s, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) s->cur_period++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) s->cur_period %= s->periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) snd_nm256_writel(chip, reg, s->buf + s->cur_period * s->period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define snd_nm256_playback_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_PBUFFER_WMARK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define snd_nm256_capture_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_RBUFFER_WMARK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) snd_nm256_playback_start(struct nm256 *chip, struct nm256_stream *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* program buffer pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) snd_nm256_writel(chip, NM_PBUFFER_START, s->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) snd_nm256_writel(chip, NM_PBUFFER_END, s->buf + s->dma_size - (1 << s->shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) snd_nm256_writel(chip, NM_PBUFFER_CURRP, s->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) snd_nm256_playback_mark(chip, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Enable playback engine and interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) snd_nm256_writeb(chip, NM_PLAYBACK_ENABLE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) NM_PLAYBACK_ENABLE_FLAG | NM_PLAYBACK_FREERUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Enable both channels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) snd_nm256_writew(chip, NM_AUDIO_MUTE_REG, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) snd_nm256_capture_start(struct nm256 *chip, struct nm256_stream *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* program buffer pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) snd_nm256_writel(chip, NM_RBUFFER_START, s->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) snd_nm256_writel(chip, NM_RBUFFER_END, s->buf + s->dma_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) snd_nm256_writel(chip, NM_RBUFFER_CURRP, s->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) snd_nm256_capture_mark(chip, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Enable playback engine and interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) snd_nm256_writeb(chip, NM_RECORD_ENABLE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) NM_RECORD_ENABLE_FLAG | NM_RECORD_FREERUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Stop the play engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) snd_nm256_playback_stop(struct nm256 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Shut off sound from both channels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) snd_nm256_writew(chip, NM_AUDIO_MUTE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) NM_AUDIO_MUTE_LEFT | NM_AUDIO_MUTE_RIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Disable play engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) snd_nm256_writeb(chip, NM_PLAYBACK_ENABLE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) snd_nm256_capture_stop(struct nm256 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Disable recording engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) snd_nm256_writeb(chip, NM_RECORD_ENABLE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) snd_nm256_playback_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct nm256 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct nm256_stream *s = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (snd_BUG_ON(!s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) s->suspended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (! s->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) snd_nm256_playback_start(chip, s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) s->running = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) s->suspended = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (s->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) snd_nm256_playback_stop(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) s->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) snd_nm256_capture_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct nm256 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct nm256_stream *s = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (snd_BUG_ON(!s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (! s->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) snd_nm256_capture_start(chip, s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) s->running = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (s->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) snd_nm256_capture_stop(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) s->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * prepare playback/capture channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int snd_nm256_pcm_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct nm256 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct nm256_stream *s = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (snd_BUG_ON(!s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) s->dma_size = frames_to_bytes(runtime, substream->runtime->buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) s->period_size = frames_to_bytes(runtime, substream->runtime->period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) s->periods = substream->runtime->periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) s->cur_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) s->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) snd_nm256_set_format(chip, s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * get the current pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) snd_nm256_playback_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct nm256 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct nm256_stream *s = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) unsigned long curp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (snd_BUG_ON(!s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) curp = snd_nm256_readl(chip, NM_PBUFFER_CURRP) - (unsigned long)s->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) curp %= s->dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return bytes_to_frames(substream->runtime, curp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) snd_nm256_capture_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct nm256 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct nm256_stream *s = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) unsigned long curp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (snd_BUG_ON(!s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) curp = snd_nm256_readl(chip, NM_RBUFFER_CURRP) - (unsigned long)s->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) curp %= s->dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return bytes_to_frames(substream->runtime, curp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Remapped I/O space can be accessible as pointer on i386 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* This might be changed in the future */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #ifndef __i386__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * silence / copy for playback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) snd_nm256_playback_silence(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int channel, unsigned long pos, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct nm256_stream *s = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) memset_io(s->bufptr + pos, 0, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) snd_nm256_playback_copy(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) void __user *src, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct nm256_stream *s = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (copy_from_user_toio(s->bufptr + pos, src, count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) snd_nm256_playback_copy_kernel(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) void *src, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct nm256_stream *s = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) memcpy_toio(s->bufptr + pos, src, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * copy to user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) snd_nm256_capture_copy(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) void __user *dst, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct nm256_stream *s = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (copy_to_user_fromio(dst, s->bufptr + pos, count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) snd_nm256_capture_copy_kernel(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int channel, unsigned long pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) void *dst, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct nm256_stream *s = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) memcpy_fromio(dst, s->bufptr + pos, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #endif /* !__i386__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * update playback/capture watermarks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* spinlock held! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) snd_nm256_playback_update(struct nm256 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct nm256_stream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) s = &chip->streams[SNDRV_PCM_STREAM_PLAYBACK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (s->running && s->substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) snd_pcm_period_elapsed(s->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) snd_nm256_playback_mark(chip, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* spinlock held! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) snd_nm256_capture_update(struct nm256 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct nm256_stream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) s = &chip->streams[SNDRV_PCM_STREAM_CAPTURE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (s->running && s->substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) snd_pcm_period_elapsed(s->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) snd_nm256_capture_mark(chip, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * hardware info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const struct snd_pcm_hardware snd_nm256_playback =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .info = SNDRV_PCM_INFO_MMAP_IOMEM |SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /*SNDRV_PCM_INFO_PAUSE |*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) SNDRV_PCM_INFO_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .rates = SNDRV_PCM_RATE_KNOT/*24k*/ | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .buffer_bytes_max = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .period_bytes_min = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .period_bytes_max = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static const struct snd_pcm_hardware snd_nm256_capture =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .info = SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /*SNDRV_PCM_INFO_PAUSE |*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) SNDRV_PCM_INFO_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .rates = SNDRV_PCM_RATE_KNOT/*24k*/ | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .buffer_bytes_max = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .period_bytes_min = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .period_bytes_max = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* set dma transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int snd_nm256_pcm_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* area and addr are already set and unchanged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static void snd_nm256_setup_stream(struct nm256 *chip, struct nm256_stream *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) const struct snd_pcm_hardware *hw_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) s->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) runtime->hw = *hw_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) runtime->hw.buffer_bytes_max = s->bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) runtime->hw.period_bytes_max = s->bufsize / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) runtime->dma_area = (void __force *) s->bufptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) runtime->dma_addr = s->bufptr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) runtime->dma_bytes = s->bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) runtime->private_data = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) s->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) &constraints_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) snd_nm256_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct nm256 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (snd_nm256_acquire_irq(chip) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) snd_nm256_setup_stream(chip, &chip->streams[SNDRV_PCM_STREAM_PLAYBACK],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) substream, &snd_nm256_playback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) snd_nm256_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct nm256 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (snd_nm256_acquire_irq(chip) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) snd_nm256_setup_stream(chip, &chip->streams[SNDRV_PCM_STREAM_CAPTURE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) substream, &snd_nm256_capture);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * close - we don't have to do special..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) snd_nm256_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct nm256 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) snd_nm256_release_irq(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) snd_nm256_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct nm256 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) snd_nm256_release_irq(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * create a pcm instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static const struct snd_pcm_ops snd_nm256_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .open = snd_nm256_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .close = snd_nm256_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .hw_params = snd_nm256_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .prepare = snd_nm256_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .trigger = snd_nm256_playback_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .pointer = snd_nm256_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #ifndef __i386__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .copy_user = snd_nm256_playback_copy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .copy_kernel = snd_nm256_playback_copy_kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .fill_silence = snd_nm256_playback_silence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .mmap = snd_pcm_lib_mmap_iomem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static const struct snd_pcm_ops snd_nm256_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .open = snd_nm256_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .close = snd_nm256_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .hw_params = snd_nm256_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .prepare = snd_nm256_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .trigger = snd_nm256_capture_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .pointer = snd_nm256_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #ifndef __i386__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .copy_user = snd_nm256_capture_copy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .copy_kernel = snd_nm256_capture_copy_kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .mmap = snd_pcm_lib_mmap_iomem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) snd_nm256_pcm(struct nm256 *chip, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct nm256_stream *s = &chip->streams[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) s->bufptr = chip->buffer + (s->buf - chip->buffer_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) s->bufptr_addr = chip->buffer_addr + (s->buf - chip->buffer_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) err = snd_pcm_new(chip->card, chip->card->driver, device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_nm256_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_nm256_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) chip->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * Initialize the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) snd_nm256_init_chip(struct nm256 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* Reset everything. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) snd_nm256_writeb(chip, 0x0, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) snd_nm256_writew(chip, 0x214, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* stop sounds.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) //snd_nm256_playback_stop(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) //snd_nm256_capture_stop(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) snd_nm256_intr_check(struct nm256 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (chip->badintrcount++ > 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * I'm not sure if the best thing is to stop the card from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * playing or just release the interrupt (after all, we're in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * a bad situation, so doing fancy stuff may not be such a good
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * idea).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * I worry about the card engine continuing to play noise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * over and over, however--that could become a very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * obnoxious problem. And we know that when this usually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * happens things are fairly safe, it just means the user's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * inserted a PCMCIA card and someone's spamming us with IRQ 9s.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (chip->streams[SNDRV_PCM_STREAM_PLAYBACK].running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) snd_nm256_playback_stop(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (chip->streams[SNDRV_PCM_STREAM_CAPTURE].running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) snd_nm256_capture_stop(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) chip->badintrcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * Handle a potential interrupt for the device referred to by DEV_ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * I don't like the cut-n-paste job here either between the two routines,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * but there are sufficient differences between the two interrupt handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * that parameterizing it isn't all that great either. (Could use a macro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * I suppose...yucky bleah.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) snd_nm256_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct nm256 *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) u8 cbyte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) status = snd_nm256_readw(chip, NM_INT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* Not ours. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return snd_nm256_intr_check(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) chip->badintrcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* Rather boring; check for individual interrupts and process them. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (status & NM_PLAYBACK_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) status &= ~NM_PLAYBACK_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) NM_ACK_INT(chip, NM_PLAYBACK_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) snd_nm256_playback_update(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (status & NM_RECORD_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) status &= ~NM_RECORD_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) NM_ACK_INT(chip, NM_RECORD_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) snd_nm256_capture_update(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (status & NM_MISC_INT_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) status &= ~NM_MISC_INT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) NM_ACK_INT(chip, NM_MISC_INT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dev_dbg(chip->card->dev, "NM256: Got misc interrupt #1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) snd_nm256_writew(chip, NM_INT_REG, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) cbyte = snd_nm256_readb(chip, 0x400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) snd_nm256_writeb(chip, 0x400, cbyte | 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (status & NM_MISC_INT_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) status &= ~NM_MISC_INT_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) NM_ACK_INT(chip, NM_MISC_INT_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dev_dbg(chip->card->dev, "NM256: Got misc interrupt #2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) cbyte = snd_nm256_readb(chip, 0x400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) snd_nm256_writeb(chip, 0x400, cbyte & ~2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* Unknown interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) "NM256: Fire in the hole! Unknown status 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* Pray. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) NM_ACK_INT(chip, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * Handle a potential interrupt for the device referred to by DEV_ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * This handler is for the 256ZX, and is very similar to the non-ZX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) snd_nm256_interrupt_zx(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct nm256 *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) u8 cbyte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) status = snd_nm256_readl(chip, NM_INT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* Not ours. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return snd_nm256_intr_check(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) chip->badintrcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* Rather boring; check for individual interrupts and process them. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (status & NM2_PLAYBACK_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) status &= ~NM2_PLAYBACK_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) NM2_ACK_INT(chip, NM2_PLAYBACK_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) snd_nm256_playback_update(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (status & NM2_RECORD_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) status &= ~NM2_RECORD_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) NM2_ACK_INT(chip, NM2_RECORD_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) snd_nm256_capture_update(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (status & NM2_MISC_INT_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) status &= ~NM2_MISC_INT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) NM2_ACK_INT(chip, NM2_MISC_INT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) dev_dbg(chip->card->dev, "NM256: Got misc interrupt #1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) cbyte = snd_nm256_readb(chip, 0x400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) snd_nm256_writeb(chip, 0x400, cbyte | 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (status & NM2_MISC_INT_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) status &= ~NM2_MISC_INT_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) NM2_ACK_INT(chip, NM2_MISC_INT_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dev_dbg(chip->card->dev, "NM256: Got misc interrupt #2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) cbyte = snd_nm256_readb(chip, 0x400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) snd_nm256_writeb(chip, 0x400, cbyte & ~2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* Unknown interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) "NM256: Fire in the hole! Unknown status 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* Pray. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) NM2_ACK_INT(chip, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * AC97 interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * Waits for the mixer to become ready to be written; returns a zero value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * if it timed out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) snd_nm256_ac97_ready(struct nm256 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int timeout = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) u32 testaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) u16 testb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) testaddr = chip->mixer_status_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) testb = chip->mixer_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * Loop around waiting for the mixer to become ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) while (timeout-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if ((snd_nm256_readw(chip, testaddr) & testb) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * Initial register values to be written to the AC97 mixer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * While most of these are identical to the reset values, we do this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * so that we have most of the register contents cached--this avoids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * reading from the mixer directly (which seems to be problematic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * probably due to ignorance).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct initialValues {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) unsigned short reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) unsigned short value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static const struct initialValues nm256_ac97_init_val[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) { AC97_MASTER, 0x8000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) { AC97_HEADPHONE, 0x8000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) { AC97_MASTER_MONO, 0x8000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) { AC97_PC_BEEP, 0x8000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) { AC97_PHONE, 0x8008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) { AC97_MIC, 0x8000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) { AC97_LINE, 0x8808 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) { AC97_CD, 0x8808 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) { AC97_VIDEO, 0x8808 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) { AC97_AUX, 0x8808 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) { AC97_PCM, 0x8808 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) { AC97_REC_SEL, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) { AC97_REC_GAIN, 0x0B0B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) { AC97_GENERAL_PURPOSE, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) { AC97_3D_CONTROL, 0x8000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) { AC97_VENDOR_ID1, 0x8384 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) { AC97_VENDOR_ID2, 0x7609 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static int nm256_ac97_idx(unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) for (i = 0; i < ARRAY_SIZE(nm256_ac97_init_val); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (nm256_ac97_init_val[i].reg == reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * some nm256 easily crash when reading from mixer registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * thus we're treating it as a write-only mixer and cache the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * written values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static unsigned short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) snd_nm256_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct nm256 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) int idx = nm256_ac97_idx(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return chip->ac97_regs[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) snd_nm256_ac97_write(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) unsigned short reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct nm256 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) int tries = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) int idx = nm256_ac97_idx(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) u32 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) base = chip->mixer_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) snd_nm256_ac97_ready(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* Wait for the write to take, too. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) while (tries-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) snd_nm256_writew(chip, base + reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) msleep(1); /* a little delay here seems better.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (snd_nm256_ac97_ready(chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) /* successful write: set cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) chip->ac97_regs[idx] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dev_dbg(chip->card->dev, "nm256: ac97 codec not ready..\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /* static resolution table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) static const struct snd_ac97_res_table nm256_res_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) { AC97_MASTER, 0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) { AC97_HEADPHONE, 0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) { AC97_MASTER_MONO, 0x001f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) { AC97_PC_BEEP, 0x001f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) { AC97_PHONE, 0x001f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) { AC97_MIC, 0x001f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) { AC97_LINE, 0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) { AC97_CD, 0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) { AC97_VIDEO, 0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) { AC97_AUX, 0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) { AC97_PCM, 0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) { AC97_REC_GAIN, 0x0f0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) { } /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* initialize the ac97 into a known state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) snd_nm256_ac97_reset(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct nm256 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) /* Reset the mixer. 'Tis magic! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) snd_nm256_writeb(chip, 0x6c0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (! chip->reset_workaround) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* Dell latitude LS will lock up by this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) snd_nm256_writeb(chip, 0x6cc, 0x87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (! chip->reset_workaround_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* Dell latitude CSx will lock up by this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) snd_nm256_writeb(chip, 0x6cc, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) snd_nm256_writeb(chip, 0x6cc, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (! chip->in_resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) for (i = 0; i < ARRAY_SIZE(nm256_ac97_init_val); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* preload the cache, so as to avoid even a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * read of the mixer regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) snd_nm256_ac97_write(ac97, nm256_ac97_init_val[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) nm256_ac97_init_val[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /* create an ac97 mixer interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) snd_nm256_mixer(struct nm256 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct snd_ac97_bus *pbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct snd_ac97_template ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static const struct snd_ac97_bus_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .reset = snd_nm256_ac97_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .write = snd_nm256_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .read = snd_nm256_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) chip->ac97_regs = kcalloc(ARRAY_SIZE(nm256_ac97_init_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) sizeof(short), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (! chip->ac97_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ac97.scaps = AC97_SCAP_AUDIO; /* we support audio! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ac97.private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ac97.res_table = nm256_res_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) pbus->no_vra = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) err = snd_ac97_mixer(pbus, &ac97, &chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (! (chip->ac97->id & (0xf0000000))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* looks like an invalid id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) sprintf(chip->card->mixername, "%s AC97", chip->card->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * See if the signature left by the NM256 BIOS is intact; if so, we use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * the associated address as the end of our audio buffer in the video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) snd_nm256_peek_for_sig(struct nm256 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* The signature is located 1K below the end of video RAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) void __iomem *temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* Default buffer end is 5120 bytes below the top of RAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) unsigned long pointer_found = chip->buffer_end - 0x1400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) u32 sig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) temp = ioremap(chip->buffer_addr + chip->buffer_end - 0x400, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (temp == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) "Unable to scan for card signature in video RAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) sig = readl(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if ((sig & NM_SIG_MASK) == NM_SIGNATURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) u32 pointer = readl(temp + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * If it's obviously invalid, don't use it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (pointer == 0xffffffff ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) pointer < chip->buffer_size ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) pointer > chip->buffer_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) "invalid signature found: 0x%x\n", pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) iounmap(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) pointer_found = pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) dev_info(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) "found card signature in video RAM: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) iounmap(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) chip->buffer_end = pointer_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * APM event handler, so the card is properly reinitialized after a power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static int nm256_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct nm256 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) snd_ac97_suspend(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) chip->coeffs_current = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) static int nm256_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) struct nm256 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* Perform a full reset on the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) chip->in_resume = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) snd_nm256_init_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /* restore ac97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) snd_ac97_resume(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) struct nm256_stream *s = &chip->streams[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (s->substream && s->suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) snd_nm256_set_format(chip, s, s->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) chip->in_resume = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static SIMPLE_DEV_PM_OPS(nm256_pm, nm256_suspend, nm256_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define NM256_PM_OPS &nm256_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define NM256_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static int snd_nm256_free(struct nm256 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (chip->streams[SNDRV_PCM_STREAM_PLAYBACK].running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) snd_nm256_playback_stop(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (chip->streams[SNDRV_PCM_STREAM_CAPTURE].running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) snd_nm256_capture_stop(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (chip->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) iounmap(chip->cport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) iounmap(chip->buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) release_and_free_resource(chip->res_cport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) release_and_free_resource(chip->res_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) pci_disable_device(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) kfree(chip->ac97_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static int snd_nm256_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) struct nm256 *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return snd_nm256_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) snd_nm256_create(struct snd_card *card, struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) struct nm256 **chip_ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) struct nm256 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) int err, pval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .dev_free = snd_nm256_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) *chip_ret = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if ((err = pci_enable_device(pci)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) chip = kzalloc(sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (chip == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) chip->use_cache = use_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) spin_lock_init(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) mutex_init(&chip->irq_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* store buffer sizes in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize = playback_bufsize * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize = capture_bufsize * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * The NM256 has two memory ports. The first port is nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * more than a chunk of video RAM, which is used as the I/O ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * buffer. The second port has the actual juicy stuff (like the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * mixer and the playback engine control registers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) chip->buffer_addr = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) chip->cport_addr = pci_resource_start(pci, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* Init the memory port info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* remap control port (#2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) chip->res_cport = request_mem_region(chip->cport_addr, NM_PORT2_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) card->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (chip->res_cport == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) dev_err(card->dev, "memory region 0x%lx (size 0x%x) busy\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) chip->cport_addr, NM_PORT2_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) chip->cport = ioremap(chip->cport_addr, NM_PORT2_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (chip->cport == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) dev_err(card->dev, "unable to map control port %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) chip->cport_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (!strcmp(card->driver, "NM256AV")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /* Ok, try to see if this is a non-AC97 version of the hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) pval = snd_nm256_readw(chip, NM_MIXER_PRESENCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if ((pval & NM_PRESENCE_MASK) != NM_PRESENCE_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (! force_ac97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) dev_err(card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) "no ac97 is found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) dev_err(card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) "force the driver to load by passing in the module parameter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) dev_err(card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) " force_ac97=1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) dev_err(card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) "or try sb16, opl3sa2, or cs423x drivers instead.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) chip->buffer_end = 2560 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) chip->interrupt = snd_nm256_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) chip->mixer_status_offset = NM_MIXER_STATUS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) chip->mixer_status_mask = NM_MIXER_READY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /* Not sure if there is any relevant detect for the ZX or not. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (snd_nm256_readb(chip, 0xa0b) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) chip->buffer_end = 6144 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) chip->buffer_end = 4096 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) chip->interrupt = snd_nm256_interrupt_zx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) chip->mixer_status_offset = NM2_MIXER_STATUS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) chip->mixer_status_mask = NM2_MIXER_READY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) chip->buffer_size = chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (chip->use_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) chip->buffer_size += NM_TOTAL_COEFF_COUNT * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) chip->buffer_size += NM_MAX_PLAYBACK_COEF_SIZE + NM_MAX_RECORD_COEF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (buffer_top >= chip->buffer_size && buffer_top < chip->buffer_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) chip->buffer_end = buffer_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) /* get buffer end pointer from signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) if ((err = snd_nm256_peek_for_sig(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) chip->buffer_start = chip->buffer_end - chip->buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) chip->buffer_addr += chip->buffer_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) dev_info(card->dev, "Mapping port 1 from 0x%x - 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) chip->buffer_start, chip->buffer_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) chip->res_buffer = request_mem_region(chip->buffer_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) chip->buffer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) card->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (chip->res_buffer == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) dev_err(card->dev, "buffer 0x%lx (size 0x%x) busy\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) chip->buffer_addr, chip->buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) chip->buffer = ioremap(chip->buffer_addr, chip->buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (chip->buffer == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) dev_err(card->dev, "unable to map ring buffer at %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) chip->buffer_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /* set offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) addr = chip->buffer_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) chip->streams[SNDRV_PCM_STREAM_PLAYBACK].buf = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) addr += chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) chip->streams[SNDRV_PCM_STREAM_CAPTURE].buf = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) addr += chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (chip->use_cache) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) chip->all_coeff_buf = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) chip->coeff_buf[SNDRV_PCM_STREAM_PLAYBACK] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) addr += NM_MAX_PLAYBACK_COEF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) chip->coeff_buf[SNDRV_PCM_STREAM_CAPTURE] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* Fixed setting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) chip->mixer_base = NM_MIXER_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) chip->coeffs_current = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) snd_nm256_init_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) // pci_set_master(pci); /* needed? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) *chip_ret = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) __error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) snd_nm256_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) enum { NM_IGNORED, NM_RESET_WORKAROUND, NM_RESET_WORKAROUND_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static const struct snd_pci_quirk nm256_quirks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* HP omnibook 4150 has cs4232 codec internally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) SND_PCI_QUIRK(0x103c, 0x0007, "HP omnibook 4150", NM_IGNORED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) /* Reset workarounds to avoid lock-ups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) SND_PCI_QUIRK(0x104d, 0x8041, "Sony PCG-F305", NM_RESET_WORKAROUND),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) SND_PCI_QUIRK(0x1028, 0x0080, "Dell Latitude LS", NM_RESET_WORKAROUND),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) SND_PCI_QUIRK(0x1028, 0x0091, "Dell Latitude CSx", NM_RESET_WORKAROUND_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) { } /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static int snd_nm256_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct nm256 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) const struct snd_pci_quirk *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) q = snd_pci_quirk_lookup(pci, nm256_quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (q) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) dev_dbg(&pci->dev, "Enabled quirk for %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) snd_pci_quirk_name(q));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) switch (q->value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) case NM_IGNORED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) dev_info(&pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) "The device is on the denylist. Loading stopped\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) case NM_RESET_WORKAROUND_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) reset_workaround_2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) case NM_RESET_WORKAROUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) reset_workaround = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) switch (pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) case PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) strcpy(card->driver, "NM256AV");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) case PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) strcpy(card->driver, "NM256ZX");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) case PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) strcpy(card->driver, "NM256XL+");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) dev_err(&pci->dev, "invalid device id 0x%x\n", pci->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if (vaio_hack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) buffer_top = 0x25a800; /* this avoids conflicts with XFree86 server */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (playback_bufsize < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) playback_bufsize = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (playback_bufsize > 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) playback_bufsize = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (capture_bufsize < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) capture_bufsize = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (capture_bufsize > 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) capture_bufsize = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if ((err = snd_nm256_create(card, pci, &chip)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) card->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (reset_workaround) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) dev_dbg(&pci->dev, "reset_workaround activated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) chip->reset_workaround = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (reset_workaround_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) dev_dbg(&pci->dev, "reset_workaround_2 activated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) chip->reset_workaround_2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if ((err = snd_nm256_pcm(chip, 0)) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) (err = snd_nm256_mixer(chip)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) sprintf(card->shortname, "NeoMagic %s", card->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) sprintf(card->longname, "%s at 0x%lx & 0x%lx, irq %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) card->shortname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) chip->buffer_addr, chip->cport_addr, chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if ((err = snd_card_register(card)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) static void snd_nm256_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static struct pci_driver nm256_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .id_table = snd_nm256_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .probe = snd_nm256_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .remove = snd_nm256_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .pm = NM256_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) module_pci_driver(nm256_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags