^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Digigram miXart soundcards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * definitions and makros for basic card access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2003 by Digigram <alsa@digigram.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __SOUND_MIXART_HWDEP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __SOUND_MIXART_HWDEP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/hwdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef readl_be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define readl_be(x) be32_to_cpu((__force __be32)__raw_readl(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef writel_be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define writel_be(data,addr) __raw_writel((__force u32)cpu_to_be32(data),addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifndef readl_le
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define readl_le(x) le32_to_cpu((__force __le32)__raw_readl(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifndef writel_le
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define writel_le(data,addr) __raw_writel((__force u32)cpu_to_le32(data),addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MIXART_MEM(mgr,x) ((mgr)->mem[0].virt + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MIXART_REG(mgr,x) ((mgr)->mem[1].virt + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Daughter board Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DAUGHTER_TYPE_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DAUGHTER_VER_MASK 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DAUGHTER_TYPEVER_MASK (DAUGHTER_TYPE_MASK|DAUGHTER_VER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MIXART_DAUGHTER_TYPE_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MIXART_DAUGHTER_TYPE_COBRANET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MIXART_DAUGHTER_TYPE_AES 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MIXART_BA0_SIZE (16 * 1024 * 1024) /* 16M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MIXART_BA1_SIZE (4 * 1024) /* 4k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * -----------BAR 0 --------------------------------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MIXART_PSEUDOREG 0x2000 /* base address for pseudoregister */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MIXART_PSEUDOREG_BOARDNUMBER MIXART_PSEUDOREG+0 /* board number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* perfmeter (available when elf loaded)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MIXART_PSEUDOREG_PERF_STREAM_LOAD_OFFSET MIXART_PSEUDOREG+0x70 /* streaming load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MIXART_PSEUDOREG_PERF_SYSTEM_LOAD_OFFSET MIXART_PSEUDOREG+0x78 /* system load (reference)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MIXART_PSEUDOREG_PERF_MAILBX_LOAD_OFFSET MIXART_PSEUDOREG+0x7C /* mailbox load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MIXART_PSEUDOREG_PERF_INTERR_LOAD_OFFSET MIXART_PSEUDOREG+0x74 /* interrupt handling load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* motherboard xilinx loader info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MIXART_PSEUDOREG_MXLX_BASE_ADDR_OFFSET MIXART_PSEUDOREG+0x9C /* 0x00600000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MIXART_PSEUDOREG_MXLX_SIZE_OFFSET MIXART_PSEUDOREG+0xA0 /* xilinx size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MIXART_PSEUDOREG_MXLX_STATUS_OFFSET MIXART_PSEUDOREG+0xA4 /* status = EMBEBBED_STAT_XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* elf loader info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MIXART_PSEUDOREG_ELF_STATUS_OFFSET MIXART_PSEUDOREG+0xB0 /* status = EMBEBBED_STAT_XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * after the elf code is loaded, and the flowtable info was passed to it,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * the driver polls on this address, until it shows 1 (presence) or 2 (absence)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * once it is non-zero, the daughter board type may be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MIXART_PSEUDOREG_DBRD_PRESENCE_OFFSET MIXART_PSEUDOREG+0x990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Global info structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MIXART_PSEUDOREG_DBRD_TYPE_OFFSET MIXART_PSEUDOREG+0x994 /* Type and version of daughterboard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* daughterboard xilinx loader info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MIXART_PSEUDOREG_DXLX_BASE_ADDR_OFFSET MIXART_PSEUDOREG+0x998 /* get the address here where to write the file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MIXART_PSEUDOREG_DXLX_SIZE_OFFSET MIXART_PSEUDOREG+0x99C /* xilinx size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MIXART_PSEUDOREG_DXLX_STATUS_OFFSET MIXART_PSEUDOREG+0x9A0 /* status = EMBEBBED_STAT_XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MIXART_FLOWTABLE_PTR 0x3000 /* pointer to flow table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* mailbox addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* message DRV -> EMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MSG_INBOUND_POST_HEAD 0x010008 /* DRV posts MF + increment4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MSG_INBOUND_POST_TAIL 0x01000C /* EMB gets MF + increment4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* message EMB -> DRV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MSG_OUTBOUND_POST_TAIL 0x01001C /* DRV gets MF + increment4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MSG_OUTBOUND_POST_HEAD 0x010018 /* EMB posts MF + increment4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Get Free Frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MSG_INBOUND_FREE_TAIL 0x010004 /* DRV gets MFA + increment4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MSG_OUTBOUND_FREE_TAIL 0x010014 /* EMB gets MFA + increment4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Put Free Frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MSG_OUTBOUND_FREE_HEAD 0x010010 /* DRV puts MFA + increment4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MSG_INBOUND_FREE_HEAD 0x010000 /* EMB puts MFA + increment4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* firmware addresses of the message fifos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MSG_BOUND_STACK_SIZE 0x004000 /* size of each following stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* posted messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MSG_OUTBOUND_POST_STACK 0x108000 /* stack of messages to the DRV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MSG_INBOUND_POST_STACK 0x104000 /* stack of messages to the EMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* available empty messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MSG_OUTBOUND_FREE_STACK 0x10C000 /* stack of free enveloped for EMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MSG_INBOUND_FREE_STACK 0x100000 /* stack of free enveloped for DRV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* defines for mailbox message frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MSG_FRAME_OFFSET 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MSG_FRAME_SIZE 0x6400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MSG_FRAME_NUMBER 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MSG_FROM_AGENT_ITMF_OFFSET (MSG_FRAME_OFFSET + (MSG_FRAME_SIZE * MSG_FRAME_NUMBER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MSG_TO_AGENT_ITMF_OFFSET (MSG_FROM_AGENT_ITMF_OFFSET + MSG_FRAME_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MSG_HOST_RSC_PROTECTION (MSG_TO_AGENT_ITMF_OFFSET + MSG_FRAME_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MSG_AGENT_RSC_PROTECTION (MSG_HOST_RSC_PROTECTION + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * -----------BAR 1 --------------------------------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* interrupt addresses and constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MIXART_PCI_OMIMR_OFFSET 0x34 /* outbound message interrupt mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MIXART_PCI_OMISR_OFFSET 0x30 /* outbound message interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MIXART_PCI_ODBR_OFFSET 0x60 /* outbound doorbell register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MIXART_BA1_BRUTAL_RESET_OFFSET 0x68 /* write 1 in LSBit to reset board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MIXART_HOST_ALL_INTERRUPT_MASKED 0x02B /* 0000 0010 1011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MIXART_ALLOW_OUTBOUND_DOORBELL 0x023 /* 0000 0010 0011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MIXART_OIDI 0x008 /* 0000 0000 1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int snd_mixart_setup_firmware(struct mixart_mgr *mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #endif /* __SOUND_MIXART_HWDEP_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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