^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Digigram miXart soundcards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * DSP firmware management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2003 by Digigram <alsa@digigram.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "mixart.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "mixart_mixer.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "mixart_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "mixart_hwdep.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * wait for a value on a peudo register, exit with a timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @mgr: pointer to miXart manager structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @offset: unsigned pseudo_register base + offset of value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @is_egal: wait for the equal value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @value: value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @timeout: timeout in centisenconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int mixart_wait_nice_for_register_value(struct mixart_mgr *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 offset, int is_egal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 value, unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned long end_time = jiffies + (timeout * HZ / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) do { /* we may take too long time in this loop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * so give controls back to kernel if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) read = readl_be( MIXART_MEM( mgr, offset ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if(is_egal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if(read == value) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) else { /* wait for different value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if(read != value) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } while ( time_after_eq(end_time, jiffies) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) structures needed to upload elf code packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct snd_mixart_elf32_ehdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 e_ident[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __be16 e_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __be16 e_machine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __be32 e_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __be32 e_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __be32 e_phoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __be32 e_shoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __be32 e_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) __be16 e_ehsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __be16 e_phentsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __be16 e_phnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) __be16 e_shentsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __be16 e_shnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __be16 e_shstrndx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct snd_mixart_elf32_phdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __be32 p_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __be32 p_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __be32 p_vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __be32 p_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __be32 p_filesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __be32 p_memsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __be32 p_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __be32 p_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int mixart_load_elf(struct mixart_mgr *mgr, const struct firmware *dsp )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) char elf32_magic_number[4] = {0x7f,'E','L','F'};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct snd_mixart_elf32_ehdr *elf_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) elf_header = (struct snd_mixart_elf32_ehdr *)dsp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) for( i=0; i<4; i++ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if ( elf32_magic_number[i] != elf_header->e_ident[i] )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if( elf_header->e_phoff != 0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct snd_mixart_elf32_phdr elf_programheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) for( i=0; i < be16_to_cpu(elf_header->e_phnum); i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 pos = be32_to_cpu(elf_header->e_phoff) + (u32)(i * be16_to_cpu(elf_header->e_phentsize));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) memcpy( &elf_programheader, dsp->data + pos, sizeof(elf_programheader) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if(elf_programheader.p_type != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if( elf_programheader.p_filesz != 0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) memcpy_toio( MIXART_MEM( mgr, be32_to_cpu(elf_programheader.p_vaddr)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dsp->data + be32_to_cpu( elf_programheader.p_offset ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) be32_to_cpu( elf_programheader.p_filesz ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * get basic information and init miXart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* audio IDs for request to the board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MIXART_FIRST_ANA_AUDIO_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MIXART_FIRST_DIG_AUDIO_ID 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int mixart_enum_connectors(struct mixart_mgr *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct mixart_msg request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct mixart_enum_connector_resp *connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct mixart_audio_info_req *audio_info_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mixart_audio_info_resp *audio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) connector = kmalloc(sizeof(*connector), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) audio_info_req = kmalloc(sizeof(*audio_info_req), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) audio_info = kmalloc(sizeof(*audio_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (! connector || ! audio_info_req || ! audio_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) audio_info_req->line_max_level = MIXART_FLOAT_P_22_0_TO_HEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) audio_info_req->micro_max_level = MIXART_FLOAT_M_20_0_TO_HEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) audio_info_req->cd_max_level = MIXART_FLOAT____0_0_TO_HEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) request.message_id = MSG_SYSTEM_ENUM_PLAY_CONNECTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) request.uid = (struct mixart_uid){0,0}; /* board num = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) request.data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) request.size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) err = snd_mixart_send_msg(mgr, &request, sizeof(*connector), connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if((err < 0) || (connector->error_code) || (connector->uid_count > MIXART_MAX_PHYS_CONNECTORS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_err(&mgr->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "error MSG_SYSTEM_ENUM_PLAY_CONNECTOR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) for(k=0; k < connector->uid_count; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct mixart_pipe *pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if(k < MIXART_FIRST_DIG_AUDIO_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pipe = &mgr->chip[k/2]->pipe_out_ana;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pipe = &mgr->chip[(k-MIXART_FIRST_DIG_AUDIO_ID)/2]->pipe_out_dig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if(k & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pipe->uid_right_connector = connector->uid[k]; /* odd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pipe->uid_left_connector = connector->uid[k]; /* even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* dev_dbg(&mgr->pci->dev, "playback connector[%d].object_id = %x\n", k, connector->uid[k].object_id); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* TODO: really need send_msg MSG_CONNECTOR_GET_AUDIO_INFO for each connector ? perhaps for analog level caps ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) request.message_id = MSG_CONNECTOR_GET_AUDIO_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) request.uid = connector->uid[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) request.data = audio_info_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) request.size = sizeof(*audio_info_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) err = snd_mixart_send_msg(mgr, &request, sizeof(*audio_info), audio_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if( err < 0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dev_err(&mgr->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "error MSG_CONNECTOR_GET_AUDIO_INFO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*dev_dbg(&mgr->pci->dev, "play analog_info.analog_level_present = %x\n", audio_info->info.analog_info.analog_level_present);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) request.message_id = MSG_SYSTEM_ENUM_RECORD_CONNECTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) request.uid = (struct mixart_uid){0,0}; /* board num = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) request.data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) request.size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) err = snd_mixart_send_msg(mgr, &request, sizeof(*connector), connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if((err < 0) || (connector->error_code) || (connector->uid_count > MIXART_MAX_PHYS_CONNECTORS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_err(&mgr->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "error MSG_SYSTEM_ENUM_RECORD_CONNECTOR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for(k=0; k < connector->uid_count; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct mixart_pipe *pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if(k < MIXART_FIRST_DIG_AUDIO_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pipe = &mgr->chip[k/2]->pipe_in_ana;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pipe = &mgr->chip[(k-MIXART_FIRST_DIG_AUDIO_ID)/2]->pipe_in_dig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if(k & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pipe->uid_right_connector = connector->uid[k]; /* odd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pipe->uid_left_connector = connector->uid[k]; /* even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* dev_dbg(&mgr->pci->dev, "capture connector[%d].object_id = %x\n", k, connector->uid[k].object_id); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* TODO: really need send_msg MSG_CONNECTOR_GET_AUDIO_INFO for each connector ? perhaps for analog level caps ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) request.message_id = MSG_CONNECTOR_GET_AUDIO_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) request.uid = connector->uid[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) request.data = audio_info_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) request.size = sizeof(*audio_info_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) err = snd_mixart_send_msg(mgr, &request, sizeof(*audio_info), audio_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if( err < 0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_err(&mgr->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "error MSG_CONNECTOR_GET_AUDIO_INFO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*dev_dbg(&mgr->pci->dev, "rec analog_info.analog_level_present = %x\n", audio_info->info.analog_info.analog_level_present);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) kfree(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) kfree(audio_info_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) kfree(audio_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int mixart_enum_physio(struct mixart_mgr *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct mixart_msg request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct mixart_uid get_console_mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct mixart_return_uid console_mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct mixart_uid_enumeration phys_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* get the uid for the console manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) get_console_mgr.object_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) get_console_mgr.desc = MSG_CONSOLE_MANAGER | 0; /* cardindex = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) request.message_id = MSG_CONSOLE_GET_CLOCK_UID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) request.uid = get_console_mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) request.data = &get_console_mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) request.size = sizeof(get_console_mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) err = snd_mixart_send_msg(mgr, &request, sizeof(console_mgr), &console_mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if( (err < 0) || (console_mgr.error_code != 0) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_dbg(&mgr->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "error MSG_CONSOLE_GET_CLOCK_UID : err=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) console_mgr.error_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* used later for clock issues ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mgr->uid_console_manager = console_mgr.uid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) request.message_id = MSG_SYSTEM_ENUM_PHYSICAL_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) request.uid = (struct mixart_uid){0,0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) request.data = &console_mgr.uid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) request.size = sizeof(console_mgr.uid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) err = snd_mixart_send_msg(mgr, &request, sizeof(phys_io), &phys_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if( (err < 0) || ( phys_io.error_code != 0 ) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(&mgr->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "error MSG_SYSTEM_ENUM_PHYSICAL_IO err(%x) error_code(%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) err, phys_io.error_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* min 2 phys io per card (analog in + analog out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (phys_io.nb_uid < MIXART_MAX_CARDS * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) for(k=0; k<mgr->num_cards; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) mgr->chip[k]->uid_in_analog_physio = phys_io.uid[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mgr->chip[k]->uid_out_analog_physio = phys_io.uid[phys_io.nb_uid/2 + k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int mixart_first_init(struct mixart_mgr *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct mixart_msg request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if((err = mixart_enum_connectors(mgr)) < 0) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if((err = mixart_enum_physio(mgr)) < 0) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* send a synchro command to card (necessary to do this before first MSG_STREAM_START_STREAM_GRP_PACKET) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* though why not here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) request.message_id = MSG_SYSTEM_SEND_SYNCHRO_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) request.uid = (struct mixart_uid){0,0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) request.data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) request.size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* this command has no data. response is a 32 bit status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) err = snd_mixart_send_msg(mgr, &request, sizeof(k), &k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if( (err < 0) || (k != 0) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_err(&mgr->pci->dev, "error MSG_SYSTEM_SEND_SYNCHRO_CMD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return err == 0 ? -EINVAL : err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* firmware base addresses (when hard coded) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MIXART_MOTHERBOARD_XLX_BASE_ADDRESS 0x00600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int mixart_dsp_load(struct mixart_mgr* mgr, int index, const struct firmware *dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int err, card_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 status_xilinx, status_elf, status_daught;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* read motherboard xilinx status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) status_xilinx = readl_be( MIXART_MEM( mgr,MIXART_PSEUDOREG_MXLX_STATUS_OFFSET ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* read elf status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) status_elf = readl_be( MIXART_MEM( mgr,MIXART_PSEUDOREG_ELF_STATUS_OFFSET ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* read daughterboard xilinx status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) status_daught = readl_be( MIXART_MEM( mgr,MIXART_PSEUDOREG_DXLX_STATUS_OFFSET ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* motherboard xilinx status 5 will say that the board is performing a reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (status_xilinx == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_err(&mgr->pci->dev, "miXart is resetting !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return -EAGAIN; /* try again later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case MIXART_MOTHERBOARD_XLX_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* xilinx already loaded ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (status_xilinx == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_dbg(&mgr->pci->dev, "xilinx is already loaded !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* the status should be 0 == "idle" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (status_xilinx != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_err(&mgr->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "xilinx load error ! status = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) status_xilinx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -EIO; /* modprob -r may help ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* check xilinx validity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (((u32*)(dsp->data))[0] == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (dsp->size % 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* set xilinx status to copying */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) writel_be( 1, MIXART_MEM( mgr, MIXART_PSEUDOREG_MXLX_STATUS_OFFSET ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* setup xilinx base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) writel_be( MIXART_MOTHERBOARD_XLX_BASE_ADDRESS, MIXART_MEM( mgr,MIXART_PSEUDOREG_MXLX_BASE_ADDR_OFFSET ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* setup code size for xilinx file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) writel_be( dsp->size, MIXART_MEM( mgr, MIXART_PSEUDOREG_MXLX_SIZE_OFFSET ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* copy xilinx code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) memcpy_toio( MIXART_MEM( mgr, MIXART_MOTHERBOARD_XLX_BASE_ADDRESS), dsp->data, dsp->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* set xilinx status to copy finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) writel_be( 2, MIXART_MEM( mgr, MIXART_PSEUDOREG_MXLX_STATUS_OFFSET ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* return, because no further processing needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case MIXART_MOTHERBOARD_ELF_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (status_elf == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_dbg(&mgr->pci->dev, "elf file already loaded !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* the status should be 0 == "idle" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (status_elf != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(&mgr->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "elf load error ! status = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) status_elf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return -EIO; /* modprob -r may help ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* wait for xilinx status == 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) err = mixart_wait_nice_for_register_value( mgr, MIXART_PSEUDOREG_MXLX_STATUS_OFFSET, 1, 4, 500); /* 5sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_err(&mgr->pci->dev, "xilinx was not loaded or "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "could not be started\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* init some data on the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) writel_be( 0, MIXART_MEM( mgr, MIXART_PSEUDOREG_BOARDNUMBER ) ); /* set miXart boardnumber to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) writel_be( 0, MIXART_MEM( mgr, MIXART_FLOWTABLE_PTR ) ); /* reset pointer to flow table on miXart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* set elf status to copying */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) writel_be( 1, MIXART_MEM( mgr, MIXART_PSEUDOREG_ELF_STATUS_OFFSET ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* process the copying of the elf packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) err = mixart_load_elf( mgr, dsp );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (err < 0) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* set elf status to copy finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) writel_be( 2, MIXART_MEM( mgr, MIXART_PSEUDOREG_ELF_STATUS_OFFSET ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* wait for elf status == 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) err = mixart_wait_nice_for_register_value( mgr, MIXART_PSEUDOREG_ELF_STATUS_OFFSET, 1, 4, 300); /* 3sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_err(&mgr->pci->dev, "elf could not be started\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* miXart waits at this point on the pointer to the flow table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) writel_be( (u32)mgr->flowinfo.addr, MIXART_MEM( mgr, MIXART_FLOWTABLE_PTR ) ); /* give pointer of flow table to miXart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0; /* return, another xilinx file has to be loaded before */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case MIXART_AESEBUBOARD_XLX_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* elf and xilinx should be loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (status_elf != 4 || status_xilinx != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dev_err(&mgr->pci->dev, "xilinx or elf not "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "successfully loaded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return -EIO; /* modprob -r may help ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* wait for daughter detection != 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) err = mixart_wait_nice_for_register_value( mgr, MIXART_PSEUDOREG_DBRD_PRESENCE_OFFSET, 0, 0, 30); /* 300msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_err(&mgr->pci->dev, "error starting elf file\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* the board type can now be retrieved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) mgr->board_type = (DAUGHTER_TYPE_MASK & readl_be( MIXART_MEM( mgr, MIXART_PSEUDOREG_DBRD_TYPE_OFFSET)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (mgr->board_type == MIXART_DAUGHTER_TYPE_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break; /* no daughter board; the file does not have to be loaded, continue after the switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* only if aesebu daughter board presence (elf code must run) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (mgr->board_type != MIXART_DAUGHTER_TYPE_AES )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* daughter should be idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (status_daught != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_err(&mgr->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "daughter load error ! status = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) status_daught);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return -EIO; /* modprob -r may help ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* check daughterboard xilinx validity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (((u32*)(dsp->data))[0] == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (dsp->size % 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* inform mixart about the size of the file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) writel_be( dsp->size, MIXART_MEM( mgr, MIXART_PSEUDOREG_DXLX_SIZE_OFFSET ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* set daughterboard status to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) writel_be( 1, MIXART_MEM( mgr, MIXART_PSEUDOREG_DXLX_STATUS_OFFSET ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* wait for status == 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) err = mixart_wait_nice_for_register_value( mgr, MIXART_PSEUDOREG_DXLX_STATUS_OFFSET, 1, 2, 30); /* 300msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(&mgr->pci->dev, "daughter board load error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* get the address where to write the file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) val = readl_be( MIXART_MEM( mgr, MIXART_PSEUDOREG_DXLX_BASE_ADDR_OFFSET ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* copy daughterboard xilinx code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) memcpy_toio( MIXART_MEM( mgr, val), dsp->data, dsp->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* set daughterboard status to 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) writel_be( 4, MIXART_MEM( mgr, MIXART_PSEUDOREG_DXLX_STATUS_OFFSET ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* continue with init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) } /* end of switch file index*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* wait for daughter status == 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) err = mixart_wait_nice_for_register_value( mgr, MIXART_PSEUDOREG_DXLX_STATUS_OFFSET, 1, 3, 300); /* 3sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev_err(&mgr->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) "daughter board could not be initialised\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* init mailbox (communication with embedded) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) snd_mixart_init_mailbox(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* first communication with embedded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) err = mixart_first_init(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_err(&mgr->pci->dev, "miXart could not be set up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* create devices and mixer in accordance with HW options*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) for (card_index = 0; card_index < mgr->num_cards; card_index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct snd_mixart *chip = mgr->chip[card_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if ((err = snd_mixart_create_pcm(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (card_index == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if ((err = snd_mixart_create_mixer(chip->mgr)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if ((err = snd_card_register(chip->card)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dev_dbg(&mgr->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) "miXart firmware downloaded and successfully set up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int snd_mixart_setup_firmware(struct mixart_mgr *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const char * const fw_files[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) "miXart8.xlx", "miXart8.elf", "miXart8AES.xlx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) char path[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) const struct firmware *fw_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) sprintf(path, "mixart/%s", fw_files[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (request_firmware(&fw_entry, path, &mgr->pci->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev_err(&mgr->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "miXart: can't load firmware %s\n", path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* fake hwdep dsp record */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) err = mixart_dsp_load(mgr, i, fw_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) release_firmware(fw_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mgr->dsp_loaded |= 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) MODULE_FIRMWARE("mixart/miXart8.xlx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) MODULE_FIRMWARE("mixart/miXart8.elf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) MODULE_FIRMWARE("mixart/miXart8AES.xlx");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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