^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Digigram miXart soundcards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * main header file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2003 by Digigram <alsa@digigram.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __SOUND_MIXART_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __SOUND_MIXART_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MIXART_DRIVER_VERSION 0x000100 /* 0.1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct mixart_uid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 object_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct mem_area {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct mixart_route {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned char connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned char phase_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* firmware status codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MIXART_MOTHERBOARD_XLX_INDEX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MIXART_MOTHERBOARD_ELF_INDEX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MIXART_AESEBUBOARD_XLX_INDEX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MIXART_HARDW_FILES_MAX_INDEX 3 /* xilinx, elf, AESEBU xilinx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MIXART_MAX_CARDS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MSG_FIFO_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MIXART_MAX_PHYS_CONNECTORS (MIXART_MAX_CARDS * 2 * 2) /* 4 * stereo * (analog+digital) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct mixart_mgr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int num_cards;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct snd_mixart *chip[MIXART_MAX_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* memory-maps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct mem_area mem[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* one and only blocking message or notification may be pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 pending_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) wait_queue_head_t msg_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* messages fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 msg_fifo[MSG_FIFO_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int msg_fifo_readptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int msg_fifo_writeptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) atomic_t msg_processed; /* number of messages to be processed in irq thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct mutex lock; /* interrupt lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct mutex msg_lock; /* mailbox lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct mutex setup_mutex; /* mutex used in hw_params, open and close */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* hardware interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int dsp_loaded; /* bit flags of loaded dsp indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int board_type; /* read from embedded once elf file is loaded, 250 = miXart8, 251 = with AES, 252 = with Cobranet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct snd_dma_buffer flowinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct snd_dma_buffer bufferinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct mixart_uid uid_console_manager;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int ref_count_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct mutex mixer_mutex; /* mutex for mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MIXART_STREAM_STATUS_FREE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MIXART_STREAM_STATUS_OPEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MIXART_STREAM_STATUS_RUNNING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MIXART_STREAM_STATUS_DRAINING 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MIXART_STREAM_STATUS_PAUSE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MIXART_PLAYBACK_STREAMS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MIXART_CAPTURE_STREAMS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MIXART_PCM_ANALOG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MIXART_PCM_DIGITAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MIXART_PCM_TOTAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MIXART_MAX_STREAM_PER_CARD (MIXART_PCM_TOTAL * (MIXART_PLAYBACK_STREAMS + MIXART_CAPTURE_STREAMS) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MIXART_NOTIFY_CARD_MASK 0xF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MIXART_NOTIFY_CARD_OFFSET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MIXART_NOTIFY_PCM_MASK 0x0F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MIXART_NOTIFY_PCM_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MIXART_NOTIFY_CAPT_MASK 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MIXART_NOTIFY_SUBS_MASK 0x007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct mixart_stream {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct mixart_pipe *pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int pcm_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int status; /* nothing, running, draining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u64 abs_period_elapsed; /* last absolute stream position where period_elapsed was called (multiple of runtime->period_size) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 buf_periods; /* periods counter in the buffer (< runtime->periods) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 buf_period_frag; /* defines with buf_period_pos the exact position in the buffer (< runtime->period_size) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) enum mixart_pipe_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PIPE_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PIPE_STOPPED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PIPE_RUNNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PIPE_CLOCK_SET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct mixart_pipe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct mixart_uid group_uid; /* id of the pipe, as returned by embedded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int stream_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct mixart_uid uid_left_connector; /* UID's for the audio connectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct mixart_uid uid_right_connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) enum mixart_pipe_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int references; /* number of subs openned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int monitoring; /* pipe used for monitoring issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct snd_mixart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct mixart_mgr *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int chip_idx; /* zero based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct snd_hwdep *hwdep; /* DSP loader, only for the first card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct snd_pcm *pcm; /* PCM analog i/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct snd_pcm *pcm_dig; /* PCM digital i/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* allocate stereo pipe for instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct mixart_pipe pipe_in_ana;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct mixart_pipe pipe_out_ana;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* if AES/EBU daughter board is available, additional pipes possible on pcm_dig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct mixart_pipe pipe_in_dig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct mixart_pipe pipe_out_dig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct mixart_stream playback_stream[MIXART_PCM_TOTAL][MIXART_PLAYBACK_STREAMS]; /* 0 = pcm, 1 = pcm_dig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct mixart_stream capture_stream[MIXART_PCM_TOTAL]; /* 0 = pcm, 1 = pcm_dig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* UID's for the physical io's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct mixart_uid uid_out_analog_physio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct mixart_uid uid_in_analog_physio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int analog_playback_active[2]; /* Mixer : Master Playback active (!mute) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int analog_playback_volume[2]; /* Mixer : Master Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int analog_capture_volume[2]; /* Mixer : Master Capture Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int digital_playback_active[2*MIXART_PLAYBACK_STREAMS][2]; /* Mixer : Digital Playback Active [(analog+AES output)*streams][stereo]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int digital_playback_volume[2*MIXART_PLAYBACK_STREAMS][2]; /* Mixer : Digital Playback Volume [(analog+AES output)*streams][stereo]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int digital_capture_volume[2][2]; /* Mixer : Digital Capture Volume [analog+AES output][stereo] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int monitoring_active[2]; /* Mixer : Monitoring Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int monitoring_volume[2]; /* Mixer : Monitoring Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct mixart_bufferinfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 buffer_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 reserved[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 available_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 buffer_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct mixart_flowinfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 bufferinfo_array_phy_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 reserved[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 bufferinfo_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int snd_mixart_create_pcm(struct snd_mixart * chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct mixart_pipe *snd_mixart_add_ref_pipe(struct snd_mixart *chip, int pcm_number, int capture, int monitoring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int snd_mixart_kill_ref_pipe(struct mixart_mgr *mgr, struct mixart_pipe *pipe, int monitoring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif /* __SOUND_MIXART_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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