^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Most of the hardware init stuffs are based on maestro3 driver for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * OSS/Free by Zach Brown. Many thanks to Zach!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * ChangeLog:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Aug. 27, 2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - Fixed deadlock on capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DRIVER_NAME "Maestro3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <sound/mpu401.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MODULE_DESCRIPTION("ESS Maestro3 PCI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "{ESS,ES1988},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "{ESS,Allegro PCI},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "{ESS,Allegro-1 PCI},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "{ESS,Canyon3D-2/LE PCI}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_PARM_DESC(enable, "Enable this soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) module_param_array(external_amp, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) module_param_array(amp_gpio, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MAX_PLAYBACKS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MAX_CAPTURES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * maestro3 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Allegro PCI configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCI_LEGACY_AUDIO_CTRL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SOUND_BLASTER_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FM_SYNTHESIS_ENABLE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GAME_PORT_ENABLE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MPU401_IO_ENABLE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MPU401_IRQ_ENABLE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ALIAS_10BIT_IO 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SB_DMA_MASK 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SB_DMA_0 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SB_DMA_1 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SB_DMA_R 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SB_DMA_3 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SB_IRQ_MASK 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SB_IRQ_5 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SB_IRQ_7 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SB_IRQ_9 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SB_IRQ_10 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MIDI_IRQ_MASK 0x00003800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SERIAL_IRQ_ENABLE 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DISABLE_LEGACY 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCI_ALLEGRO_CONFIG 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SB_ADDR_240 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MPU_ADDR_MASK 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MPU_ADDR_330 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MPU_ADDR_300 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MPU_ADDR_320 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MPU_ADDR_340 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define USE_PCI_TIMING 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define POSTED_WRITE_ENABLE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DMA_POLICY_MASK 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DMA_DDMA 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DMA_TDMA 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DMA_PCPCI 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DMA_WBDMA16 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DMA_WBDMA4 0x00000500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DMA_WBDMA2 0x00000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DMA_WBDMA1 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DMA_SAFE_GUARD 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HI_PERF_GP_ENABLE 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PIC_SNOOP_MODE_0 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PIC_SNOOP_MODE_1 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SOUNDBLASTER_IRQ_MASK 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RING_IN_ENABLE 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SPDIF_TEST_MODE 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_MULT_MODE_SELECT_2 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define EEPROM_WRITE_ENABLE 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CODEC_DIR_IN 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HV_BUTTON_FROM_GD 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define REDUCED_DEBOUNCE 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HV_CTRL_ENABLE 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SPDIF_ENABLE 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_DIV_SELECT 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_DIV_BY_48 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_DIV_BY_49 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_DIV_BY_50 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_DIV_RESERVED 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PM_CTRL_ENABLE 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_MULT_MODE_SELECT 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_MULT_MODE_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_MULT_MODE_0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_MULT_MODE_1 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_MULT_MODE_2 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_MULT_MODE_3 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define INT_CLK_SELECT 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define INT_CLK_MULT_RESET 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* M3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define INT_CLK_SRC_NOT_PCI 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define INT_CLK_MULT_ENABLE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PCI_ACPI_CONTROL 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PCI_ACPI_D0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PCI_ACPI_D1 0xB4F70000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PCI_ACPI_D2 0xB4F7B4F7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PCI_USER_CONFIG 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define EXT_PCI_MASTER_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SPDIF_OUT_SELECT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TEST_PIN_DIR_CTRL 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AC97_CODEC_TEST 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TRI_STATE_BUFFER 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IN_CLK_12MHZ_SELECT 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MULTI_FUNC_DISABLE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EXT_MASTER_PAIR_SEL 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PCI_MASTER_SUPPORT 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define STOP_CLOCK_ENABLE 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define EAPD_DRIVE_ENABLE 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define REQ_TRI_STATE_ENABLE 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define REQ_LOW_ENABLE 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MIDI_1_ENABLE 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MIDI_2_ENABLE 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SB_AUDIO_SYNC 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HV_CTRL_TEST 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SOUNDBLASTER_TEST 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PCI_USER_CONFIG_C 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PCI_DDMA_CTRL 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DDMA_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Allegro registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define HOST_INT_CTRL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SB_INT_ENABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MPU401_INT_ENABLE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ASSP_INT_ENABLE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RING_INT_ENABLE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define HV_INT_ENABLE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLKRUN_GEN_ENABLE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define HV_CTRL_TO_PME 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SOFTWARE_RESET_ENABLE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * should be using the above defines, probably.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define REGB_ENABLE_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define REGB_STOP_CLOCK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define HOST_INT_STATUS 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SB_INT_PENDING 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MPU401_INT_PENDING 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ASSP_INT_PENDING 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define RING_INT_PENDING 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define HV_INT_PENDING 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define HARDWARE_VOL_CTRL 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SHADOW_MIX_REG_VOICE 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HW_VOL_COUNTER_VOICE 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SHADOW_MIX_REG_MASTER 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define HW_VOL_COUNTER_MASTER 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CODEC_COMMAND 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CODEC_READ_B 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CODEC_STATUS 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CODEC_BUSY_B 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CODEC_DATA 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define RING_BUS_CTRL_A 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define RAC_PME_ENABLE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define RAC_SDFS_ENABLE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define LAC_PME_ENABLE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define LAC_SDFS_ENABLE 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SERIAL_AC_LINK_ENABLE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IO_SRAM_ENABLE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IIS_INPUT_ENABLE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define RING_BUS_CTRL_B 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SECOND_CODEC_ID_MASK 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SPDIF_FUNC_ENABLE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SECOND_AC_ENABLE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SB_MODULE_INTF_ENABLE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SSPE_ENABLE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define M3I_DOCK_ENABLE 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SDO_OUT_DEST_CTRL 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define COMMAND_ADDR_OUT 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PCM_LR_OUT_LOCAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PCM_LR_OUT_REMOTE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PCM_LR_OUT_MUTE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PCM_LR_OUT_BOTH 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define LINE1_DAC_OUT_LOCAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define LINE1_DAC_OUT_REMOTE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define LINE1_DAC_OUT_MUTE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define LINE1_DAC_OUT_BOTH 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PCM_CLS_OUT_LOCAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PCM_CLS_OUT_REMOTE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PCM_CLS_OUT_MUTE 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PCM_CLS_OUT_BOTH 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PCM_RLF_OUT_LOCAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PCM_RLF_OUT_REMOTE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define PCM_RLF_OUT_MUTE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PCM_RLF_OUT_BOTH 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define LINE2_DAC_OUT_LOCAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define LINE2_DAC_OUT_REMOTE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define LINE2_DAC_OUT_MUTE 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define LINE2_DAC_OUT_BOTH 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define HANDSET_OUT_LOCAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define HANDSET_OUT_REMOTE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define HANDSET_OUT_MUTE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define HANDSET_OUT_BOTH 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IO_CTRL_OUT_LOCAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IO_CTRL_OUT_REMOTE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IO_CTRL_OUT_MUTE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IO_CTRL_OUT_BOTH 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SDO_IN_DEST_CTRL 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define STATUS_ADDR_IN 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define PCM_LR_IN_LOCAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define PCM_LR_IN_REMOTE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define PCM_LR_RESERVED 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define PCM_LR_IN_BOTH 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define LINE1_ADC_IN_LOCAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define LINE1_ADC_IN_REMOTE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define LINE1_ADC_IN_MUTE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MIC_ADC_IN_LOCAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MIC_ADC_IN_REMOTE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MIC_ADC_IN_MUTE 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define LINE2_DAC_IN_LOCAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define LINE2_DAC_IN_REMOTE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define LINE2_DAC_IN_MUTE 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define HANDSET_IN_LOCAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define HANDSET_IN_REMOTE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define HANDSET_IN_MUTE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IO_STATUS_IN_LOCAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IO_STATUS_IN_REMOTE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SPDIF_IN_CTRL 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SPDIF_IN_ENABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define GPIO_DATA 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define GPIO_DATA_MASK 0x0FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define GPIO_HV_STATUS 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define GPIO_PME_STATUS 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define GPIO_MASK 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define GPIO_DIRECTION 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define GPO_PRIMARY_AC97 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define GPI_LINEOUT_SENSE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define GPO_SECONDARY_AC97 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define GPI_VOL_DOWN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define GPI_VOL_UP 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define GPI_IIS_CLK 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define GPI_IIS_LRCLK 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define GPI_IIS_DATA 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define GPI_DOCKING_STATUS 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define GPI_HEADPHONE_SENSE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define GPO_EXT_AMP_SHUTDOWN 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define GPO_EXT_AMP_M3 1 /* default m3 amp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* M3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define GPO_M3_EXT_AMP_SHUTDN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define ASSP_INDEX_PORT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define ASSP_MEMORY_PORT 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define ASSP_DATA_PORT 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define MPU401_DATA_PORT 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define MPU401_STATUS_PORT 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CLK_MULT_DATA_PORT 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define ASSP_CONTROL_A 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define ASSP_0_WS_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define ASSP_CTRL_A_RESERVED1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define ASSP_CTRL_A_RESERVED2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define ASSP_CLK_49MHZ_SELECT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define FAST_PLU_ENABLE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define ASSP_CTRL_A_RESERVED3 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DSP_CLK_36MHZ_SELECT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define ASSP_CONTROL_B 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define RESET_ASSP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define RUN_ASSP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ENABLE_ASSP_CLOCK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define STOP_ASSP_CLOCK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define RESET_TOGGLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define ASSP_CONTROL_C 0xA6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define ASSP_HOST_INT_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define FM_ADDR_REMAP_DISABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define HOST_WRITE_PORT_ENABLE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define ASSP_HOST_INT_STATUS 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define DSP2HOST_REQ_PIORECORD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DSP2HOST_REQ_I2SRATE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define DSP2HOST_REQ_TIMER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * ASSP control regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define DSP_PORT_TIMER_COUNT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define DSP_PORT_MEMORY_INDEX 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define DSP_PORT_MEMORY_TYPE 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define MEMTYPE_INTERNAL_CODE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define MEMTYPE_INTERNAL_DATA 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define MEMTYPE_MASK 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DSP_PORT_MEMORY_DATA 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define DSP_PORT_CONTROL_REG_A 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define DSP_PORT_CONTROL_REG_B 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define DSP_PORT_CONTROL_REG_C 0xA6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define REV_A_CODE_MEMORY_BEGIN 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define REV_A_CODE_MEMORY_END 0x0FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define REV_B_CODE_MEMORY_BEGIN 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define REV_B_CODE_MEMORY_END 0x0BFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define REV_A_DATA_MEMORY_BEGIN 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define REV_A_DATA_MEMORY_END 0x2FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define REV_B_DATA_MEMORY_BEGIN 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define REV_B_DATA_MEMORY_END 0x2BFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define NUM_UNITS_KERNEL_CODE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define NUM_UNITS_KERNEL_DATA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * Kernel data layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define DP_SHIFT_COUNT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define KDATA_BASE_ADDR 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define KDATA_BASE_ADDR2 0x1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * second 'segment' (?) reserved for mixer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * buffers..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * client data area offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define CDATA_INSTANCE_READY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define CDATA_HOST_SRC_ADDRL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define CDATA_HOST_SRC_ADDRH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define CDATA_HOST_SRC_END_PLUS_1L 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define CDATA_HOST_SRC_END_PLUS_1H 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define CDATA_HOST_SRC_CURRENTL 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define CDATA_HOST_SRC_CURRENTH 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define CDATA_IN_BUF_CONNECT 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define CDATA_OUT_BUF_CONNECT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define CDATA_IN_BUF_BEGIN 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define CDATA_IN_BUF_END_PLUS_1 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define CDATA_IN_BUF_HEAD 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define CDATA_IN_BUF_TAIL 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define CDATA_OUT_BUF_BEGIN 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define CDATA_OUT_BUF_END_PLUS_1 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define CDATA_OUT_BUF_HEAD 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define CDATA_OUT_BUF_TAIL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define CDATA_DMA_CONTROL 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define CDATA_RESERVED 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define CDATA_FREQUENCY 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define CDATA_LEFT_VOLUME 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define CDATA_RIGHT_VOLUME 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define CDATA_LEFT_SUR_VOL 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define CDATA_RIGHT_SUR_VOL 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define CDATA_HEADER_LEN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define MINISRC_BIQUAD_STAGE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define MINISRC_COEF_LOC 0x175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define DMACONTROL_BLOCK_MASK 0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define DMAC_BLOCK0_SELECTOR 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define DMAC_BLOCK1_SELECTOR 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define DMAC_BLOCK2_SELECTOR 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define DMAC_BLOCK3_SELECTOR 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define DMAC_BLOCK4_SELECTOR 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define DMAC_BLOCK5_SELECTOR 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define DMAC_BLOCK6_SELECTOR 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define DMAC_BLOCK7_SELECTOR 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define DMAC_BLOCK8_SELECTOR 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define DMAC_BLOCK9_SELECTOR 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define DMAC_BLOCKA_SELECTOR 0x000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define DMAC_BLOCKB_SELECTOR 0x000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define DMAC_BLOCKC_SELECTOR 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define DMAC_BLOCKD_SELECTOR 0x000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define DMAC_BLOCKE_SELECTOR 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define DMAC_BLOCKF_SELECTOR 0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define DMACONTROL_PAGE_MASK 0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define DMAC_PAGE0_SELECTOR 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define DMAC_PAGE1_SELECTOR 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define DMAC_PAGE2_SELECTOR 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define DMAC_PAGE3_SELECTOR 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define DMACONTROL_AUTOREPEAT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define DMACONTROL_STOPPED 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define DMACONTROL_DIRECTION 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * an arbitrary volume we set the internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * volume settings to so that the ac97 volume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * range is a little less insane. 0x7fff is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * max.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define ARB_VOLUME ( 0x6800 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct m3_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int curlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) int max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct m3_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct assp_instance {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) unsigned short code, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) } inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) int running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int opened;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) unsigned long buffer_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) unsigned int hwptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int index[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct m3_list *index_list[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int in_lists;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct snd_m3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) unsigned long iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) unsigned int allegro_flag : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct snd_ac97 *ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int dacs_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int timer_users;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct m3_list msrc_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct m3_list mixer_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct m3_list adc1_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct m3_list dma_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* for storing reset state..*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u8 reset_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) int external_amp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) int amp_gpio; /* gpio pin # for external amp, -1 = default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) unsigned int hv_config; /* hardware-volume config bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) (e.g. for IrDA on Dell Inspirons) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* midi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* pcm streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int num_substreams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct m3_dma *substreams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #ifdef CONFIG_SND_MAESTRO3_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct input_dev *input_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) char phys[64]; /* physical device path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct snd_kcontrol *master_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct snd_kcontrol *master_volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct work_struct hwvol_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) unsigned int in_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u16 *suspend_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) const struct firmware *assp_kernel_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) const struct firmware *assp_minisrc_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * pci ids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const struct pci_device_id snd_m3_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {0,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) MODULE_DEVICE_TABLE(pci, snd_m3_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const struct snd_pci_quirk m3_amp_quirk_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) { } /* END */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static const struct snd_pci_quirk m3_irda_quirk_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) { } /* END */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* hardware volume quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static const struct snd_pci_quirk m3_hv_quirk_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* Allegro chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) SND_PCI_QUIRK(0x107B, 0x340A, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) SND_PCI_QUIRK(0x107B, 0x3450, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) SND_PCI_QUIRK(0x109F, 0x3134, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) SND_PCI_QUIRK(0x109F, 0x3161, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) SND_PCI_QUIRK(0x144D, 0x3280, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) SND_PCI_QUIRK(0x144D, 0x3281, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) SND_PCI_QUIRK(0x144D, 0xC002, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) SND_PCI_QUIRK(0x144D, 0xC003, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) SND_PCI_QUIRK(0x1509, 0x1740, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) SND_PCI_QUIRK(0x1610, 0x0010, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* Maestro3 chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) { } /* END */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* HP Omnibook quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static const struct snd_pci_quirk m3_omnibook_quirk_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) { } /* END */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * lowlevel functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) outw(value, chip->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return inw(chip->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) outb(value, chip->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return inb(chip->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * access 16bit words to the code or data regions of the dsp's memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * index addresses 16bit words.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static void snd_m3_assp_halt(struct snd_m3 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static void snd_m3_assp_continue(struct snd_m3 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * This makes me sad. the maestro3 has lists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * internally that must be packed.. 0 terminates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * apparently, or maybe all unused entries have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * to be 0, the lists have static lengths set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * by the binary code images.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) list->mem_addr + list->curlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return list->curlen++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) int lastindex = list->curlen - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (index != lastindex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) list->mem_addr + lastindex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) list->mem_addr + index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) list->mem_addr + lastindex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) list->curlen--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static void snd_m3_inc_timer_users(struct snd_m3 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) chip->timer_users++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (chip->timer_users != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) KDATA_TIMER_COUNT_RELOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) 240);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) KDATA_TIMER_COUNT_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) 240);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) snd_m3_outw(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) HOST_INT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static void snd_m3_dec_timer_users(struct snd_m3 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) chip->timer_users--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (chip->timer_users > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) KDATA_TIMER_COUNT_RELOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) KDATA_TIMER_COUNT_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) snd_m3_outw(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) HOST_INT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * start/stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* spinlock held! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (! s || ! subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) snd_m3_inc_timer_users(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) switch (subs->stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) case SNDRV_PCM_STREAM_PLAYBACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) chip->dacs_active++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) s->inst.data + CDATA_INSTANCE_READY, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) KDATA_MIXER_TASK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) chip->dacs_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) case SNDRV_PCM_STREAM_CAPTURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) KDATA_ADC1_REQUEST, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) s->inst.data + CDATA_INSTANCE_READY, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /* spinlock held! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (! s || ! subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) s->inst.data + CDATA_INSTANCE_READY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) snd_m3_dec_timer_users(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) switch (subs->stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) case SNDRV_PCM_STREAM_PLAYBACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) chip->dacs_active--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) KDATA_MIXER_TASK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) chip->dacs_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) case SNDRV_PCM_STREAM_CAPTURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) KDATA_ADC1_REQUEST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct snd_m3 *chip = snd_pcm_substream_chip(subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct m3_dma *s = subs->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) int err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (snd_BUG_ON(!s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (s->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) s->running = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) err = snd_m3_pcm_start(chip, s, subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (! s->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) err = 0; /* should return error? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) s->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) err = snd_m3_pcm_stop(chip, s, subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct snd_pcm_runtime *runtime = subs->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) s->period_size = frames_to_bytes(runtime, runtime->period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) s->hwptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) s->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define LO(x) ((x) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define HI(x) LO((x) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* host dma buffer pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) s->inst.data + CDATA_HOST_SRC_ADDRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) LO(s->buffer_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) s->inst.data + CDATA_HOST_SRC_ADDRH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) HI(s->buffer_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) LO(s->buffer_addr + s->dma_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) HI(s->buffer_addr + s->dma_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) s->inst.data + CDATA_HOST_SRC_CURRENTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) LO(s->buffer_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) s->inst.data + CDATA_HOST_SRC_CURRENTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) HI(s->buffer_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #undef LO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #undef HI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* dsp buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) s->inst.data + CDATA_IN_BUF_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) dsp_in_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) s->inst.data + CDATA_IN_BUF_END_PLUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) dsp_in_buffer + (dsp_in_size / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) s->inst.data + CDATA_IN_BUF_HEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dsp_in_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) s->inst.data + CDATA_IN_BUF_TAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) dsp_in_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) s->inst.data + CDATA_OUT_BUF_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) dsp_out_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) dsp_out_buffer + (dsp_out_size / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) s->inst.data + CDATA_OUT_BUF_HEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) dsp_out_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) s->inst.data + CDATA_OUT_BUF_TAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dsp_out_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct snd_pcm_runtime *runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * put us in the lists if we're not already there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (! s->in_lists) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) s->index[0] = snd_m3_add_list(chip, s->index_list[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) s->inst.data >> DP_SHIFT_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) s->index[1] = snd_m3_add_list(chip, s->index_list[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) s->inst.data >> DP_SHIFT_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) s->index[2] = snd_m3_add_list(chip, s->index_list[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) s->inst.data >> DP_SHIFT_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) s->in_lists = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* write to 'mono' word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) s->inst.data + SRC3_DIRECTION_OFFSET + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) runtime->channels == 2 ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /* write to '8bit' word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) s->inst.data + SRC3_DIRECTION_OFFSET + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* set up dac/adc rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) freq = ((runtime->rate << 15) + 24000 ) / 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) freq--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) s->inst.data + CDATA_FREQUENCY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static const struct play_vals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) u16 addr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) } pv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) {CDATA_LEFT_VOLUME, ARB_VOLUME},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {CDATA_RIGHT_VOLUME, ARB_VOLUME},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {SRC3_DIRECTION_OFFSET, 0} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /* +1, +2 are stereo/16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* the mode passed should be already shifted and masked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * some per client initializers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) s->inst.data + SRC3_DIRECTION_OFFSET + 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) s->inst.data + 40 + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) s->inst.data + SRC3_DIRECTION_OFFSET + 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) s->inst.code + MINISRC_COEF_LOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /* enable or disable low pass filter? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) s->inst.data + SRC3_DIRECTION_OFFSET + 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) subs->runtime->rate > 45000 ? 0xff : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* tell it which way dma is going? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) s->inst.data + CDATA_DMA_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * set an armload of static initializers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) for (i = 0; i < ARRAY_SIZE(pv); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) s->inst.data + pv[i].addr, pv[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * Native record driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static const struct rec_vals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) u16 addr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) } rv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {CDATA_LEFT_VOLUME, ARB_VOLUME},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {CDATA_RIGHT_VOLUME, ARB_VOLUME},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) {SRC3_DIRECTION_OFFSET, 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /* +1, +2 are stereo/16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * some per client initializers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) s->inst.data + SRC3_DIRECTION_OFFSET + 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) s->inst.data + 40 + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /* tell it which way dma is going? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) s->inst.data + CDATA_DMA_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * set an armload of static initializers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) for (i = 0; i < ARRAY_SIZE(rv); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) s->inst.data + rv[i].addr, rv[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) struct m3_dma *s = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* set buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) s->buffer_addr = substream->runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (s->buffer_addr & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) dev_err(substream->pcm->card->dev, "oh my, not aligned\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) s->buffer_addr = s->buffer_addr & ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) struct m3_dma *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (substream->runtime->private_data == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) s = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) s->buffer_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct snd_m3 *chip = snd_pcm_substream_chip(subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct snd_pcm_runtime *runtime = subs->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) struct m3_dma *s = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (snd_BUG_ON(!s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) runtime->format != SNDRV_PCM_FORMAT_S16_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (runtime->rate > 48000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) runtime->rate < 8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) snd_m3_pcm_setup1(chip, s, subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) snd_m3_playback_setup(chip, s, subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) snd_m3_capture_setup(chip, s, subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) snd_m3_pcm_setup2(chip, s, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * get current pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) u16 hi = 0, lo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) int retry = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * try and get a valid answer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) while (retry--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) s->inst.data + CDATA_HOST_SRC_CURRENTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) s->inst.data + CDATA_HOST_SRC_CURRENTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) s->inst.data + CDATA_HOST_SRC_CURRENTH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) addr = lo | ((u32)hi<<16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return (unsigned int)(addr - s->buffer_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) struct snd_m3 *chip = snd_pcm_substream_chip(subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) unsigned int ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) struct m3_dma *s = subs->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (snd_BUG_ON(!s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ptr = snd_m3_get_pointer(chip, s, subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return bytes_to_frames(subs->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* update pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) /* spinlock held! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) struct snd_pcm_substream *subs = s->substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) unsigned int hwptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) int diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (! s->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) hwptr = snd_m3_get_pointer(chip, s, subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* try to avoid expensive modulo divisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (hwptr >= s->dma_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) hwptr %= s->dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) diff = s->dma_size + hwptr - s->hwptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (diff >= s->dma_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) diff %= s->dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) s->hwptr = hwptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) s->count += diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (s->count >= (signed)s->period_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (s->count < 2 * (signed)s->period_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) s->count -= (signed)s->period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) s->count %= s->period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) snd_pcm_period_elapsed(subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) /* The m3's hardware volume works by incrementing / decrementing 2 counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) (without wrap around) in response to volume button presses and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) of a byte wide register. The meaning of bits 0 and 4 is unknown. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static void snd_m3_update_hw_volume(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct snd_m3 *chip = container_of(work, struct snd_m3, hwvol_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) int x, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* Figure out which volume control button was pushed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) based on differences from the default register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* Reset the volume counters to 4. Tests on the allegro integrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) into a Compaq N600C laptop, have revealed that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) 1) Writing any value will result in the 2 counters being reset to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) 4 so writing 0x88 is not strictly necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) 2) Writing to any of the 4 involved registers will reset all 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) of them (and reading them always returns the same value for all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) of them)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) It could be that a maestro deviates from this, so leave the code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) as is. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* Ignore spurious HV interrupts during suspend / resume, this avoids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) mistaking them for a mute button press. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (chip->in_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #ifndef CONFIG_SND_MAESTRO3_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (!chip->master_switch || !chip->master_volume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) val = snd_ac97_read(chip->ac97, AC97_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) switch (x) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) case 0x88:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) /* The counters have not changed, yet we've received a HV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) interrupt. According to tests run by various people this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) happens when pressing the mute button. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) val ^= 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) case 0xaa:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) /* counters increased by 1 -> volume up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if ((val & 0x7f) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) val--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if ((val & 0x7f00) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) val -= 0x0100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) case 0x66:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* counters decreased by 1 -> volume down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if ((val & 0x7f) < 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) val++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if ((val & 0x7f00) < 0x1f00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) val += 0x0100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) if (snd_ac97_update(chip->ac97, AC97_MASTER, val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) &chip->master_switch->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (!chip->input_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) switch (x) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) case 0x88:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /* The counters have not changed, yet we've received a HV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) interrupt. According to tests run by various people this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) happens when pressing the mute button. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) val = KEY_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) case 0xaa:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /* counters increased by 1 -> volume up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) val = KEY_VOLUMEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) case 0x66:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /* counters decreased by 1 -> volume down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) val = KEY_VOLUMEDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) input_report_key(chip->input_dev, val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) input_sync(chip->input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) input_report_key(chip->input_dev, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) input_sync(chip->input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) struct snd_m3 *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) status = inb(chip->iobase + HOST_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) if (status == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) if (status & HV_INT_PENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) schedule_work(&chip->hwvol_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * ack an assp int if its running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * and has an int pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (status & ASSP_INT_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (!(ctl & STOP_ASSP_CLOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (ctl & DSP2HOST_REQ_TIMER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* update adc/dac info if it was a timer int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) for (i = 0; i < chip->num_substreams; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) struct m3_dma *s = &chip->substreams[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (s->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) snd_m3_update_ptr(chip, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) #if 0 /* TODO: not supported yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if ((status & MPU401_INT_PENDING) && chip->rmidi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) /* ack ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) outb(status, chip->iobase + HOST_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static const struct snd_pcm_hardware snd_m3_playback =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /*SNDRV_PCM_INFO_PAUSE |*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) SNDRV_PCM_INFO_RESUME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .buffer_bytes_max = (512*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .period_bytes_max = (512*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static const struct snd_pcm_hardware snd_m3_capture =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) /*SNDRV_PCM_INFO_PAUSE |*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) SNDRV_PCM_INFO_RESUME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .buffer_bytes_max = (512*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .period_bytes_max = (512*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) struct m3_dma *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) for (i = 0; i < chip->num_substreams; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) s = &chip->substreams[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (! s->opened)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) goto __found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) __found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) s->opened = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) s->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) subs->runtime->private_data = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) s->substream = subs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) /* set list owners */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) s->index_list[0] = &chip->mixer_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) s->index_list[0] = &chip->adc1_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) s->index_list[1] = &chip->msrc_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) s->index_list[2] = &chip->dma_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) struct m3_dma *s = subs->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) if (s == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) return; /* not opened properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) if (s->substream && s->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (s->in_lists) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) s->in_lists = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) s->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) s->opened = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) snd_m3_playback_open(struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) struct snd_m3 *chip = snd_pcm_substream_chip(subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) struct snd_pcm_runtime *runtime = subs->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) if ((err = snd_m3_substream_open(chip, subs)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) runtime->hw = snd_m3_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) snd_m3_playback_close(struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) struct snd_m3 *chip = snd_pcm_substream_chip(subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) snd_m3_substream_close(chip, subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) snd_m3_capture_open(struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) struct snd_m3 *chip = snd_pcm_substream_chip(subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) struct snd_pcm_runtime *runtime = subs->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if ((err = snd_m3_substream_open(chip, subs)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) runtime->hw = snd_m3_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) snd_m3_capture_close(struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) struct snd_m3 *chip = snd_pcm_substream_chip(subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) snd_m3_substream_close(chip, subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) * create pcm instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) static const struct snd_pcm_ops snd_m3_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .open = snd_m3_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .close = snd_m3_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .hw_params = snd_m3_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .hw_free = snd_m3_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .prepare = snd_m3_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .trigger = snd_m3_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .pointer = snd_m3_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static const struct snd_pcm_ops snd_m3_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .open = snd_m3_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .close = snd_m3_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .hw_params = snd_m3_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .hw_free = snd_m3_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .prepare = snd_m3_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .trigger = snd_m3_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .pointer = snd_m3_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) snd_m3_pcm(struct snd_m3 * chip, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) err = snd_pcm_new(chip->card, chip->card->driver, device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) strcpy(pcm->name, chip->card->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) chip->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) &chip->pci->dev, 64*1024, 64*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) * ac97 interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) * Wait for the ac97 serial bus to be free.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) * return nonzero if the bus is still busy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) static int snd_m3_ac97_wait(struct snd_m3 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) int i = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (! (snd_m3_inb(chip, 0x30) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) } while (i-- > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) dev_err(chip->card->dev, "ac97 serial bus busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) static unsigned short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) struct snd_m3 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) unsigned short data = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) if (snd_m3_ac97_wait(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if (snd_m3_ac97_wait(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) data = snd_m3_inw(chip, CODEC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) struct snd_m3 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (snd_m3_ac97_wait(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) snd_m3_outw(chip, val, CODEC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) * Workaround for buggy ES1988 integrated AC'97 codec. It remains silent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) * until the MASTER volume or mute is touched (alsactl restore does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) * work).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (ac97->id == 0x45838308 && reg == AC97_MASTER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) snd_m3_ac97_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) snd_m3_outw(chip, val, CODEC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static void snd_m3_remote_codec_config(struct snd_m3 *chip, int isremote)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) int io = chip->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) isremote = isremote ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) tmp = inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /* enable dock on Dell Latitude C810 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (chip->pci->subsystem_vendor == 0x1028 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) chip->pci->subsystem_device == 0x00e5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) tmp |= M3I_DOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) outw(tmp | isremote, io + RING_BUS_CTRL_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) io + SDO_OUT_DEST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) io + SDO_IN_DEST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) * hack, returns non zero on err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static int snd_m3_try_read_vendor(struct snd_m3 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) u16 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (snd_m3_ac97_wait(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (snd_m3_ac97_wait(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) ret = snd_m3_inw(chip, 0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) return (ret == 0) || (ret == 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) static void snd_m3_ac97_reset(struct snd_m3 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) u16 dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) int delay1 = 0, delay2 = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) int io = chip->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) if (chip->allegro_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) * the onboard codec on the allegro seems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) * to want to wait a very long time before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) * coming back to life
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) delay1 = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) delay2 = 800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) /* maestro3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) delay1 = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) delay2 = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) dir = inw(io + GPIO_DIRECTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) if (!chip->irda_workaround)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) dir |= 0x10; /* assuming pci bus master? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) snd_m3_remote_codec_config(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) outw(0, io + GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) /* ok, bring back the ac-link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) outw(~0, io + GPIO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) if (! snd_m3_try_read_vendor(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) delay1 += 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) delay2 += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) "retrying codec reset with delays of %d and %d ms\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) delay1, delay2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) /* more gung-ho reset that doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) * seem to work anywhere :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) tmp = inw(io + RING_BUS_CTRL_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) outw(tmp, io + RING_BUS_CTRL_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) static int snd_m3_mixer(struct snd_m3 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) struct snd_ac97_bus *pbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) struct snd_ac97_template ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) #ifndef CONFIG_SND_MAESTRO3_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) struct snd_ctl_elem_id elem_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) static const struct snd_ac97_bus_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .write = snd_m3_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .read = snd_m3_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) ac97.private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) /* seems ac97 PCM needs initialization.. hack hack.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) schedule_timeout_uninterruptible(msecs_to_jiffies(100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) snd_ac97_write(chip->ac97, AC97_PCM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) #ifndef CONFIG_SND_MAESTRO3_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) memset(&elem_id, 0, sizeof(elem_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) strcpy(elem_id.name, "Master Playback Switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) memset(&elem_id, 0, sizeof(elem_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) strcpy(elem_id.name, "Master Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) * initialize ASSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) #define MINISRC_LPF_LEN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) static void snd_m3_assp_init(struct snd_m3 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) const __le16 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) /* zero kernel data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) KDATA_BASE_ADDR + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) /* zero mixer data? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) KDATA_BASE_ADDR2 + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) /* init dma pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) KDATA_CURRENT_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) KDATA_DMA_XFER0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) /* write kernel into code memory.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) data = (const __le16 *)chip->assp_kernel_image->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) REV_B_CODE_MEMORY_BEGIN + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) le16_to_cpu(data[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) * We only have this one client and we know that 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) * is free in our kernel's mem map, so lets just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) * drop it there. It seems that the minisrc doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) * need vectors, so we won't bother with them..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) data = (const __le16 *)chip->assp_minisrc_image->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) 0x400 + i, le16_to_cpu(data[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) * write the coefficients for the low pass filter?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) for (i = 0; i < MINISRC_LPF_LEN ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) 0x400 + MINISRC_COEF_LOC + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) minisrc_lpf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) * the minisrc is the only thing on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) * our task list..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) KDATA_TASK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) 0x400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) * init the mixer number..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) KDATA_MIXER_TASK_NUMBER,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) * EXTREME KERNEL MASTER VOLUME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) chip->mixer_list.curlen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) chip->adc1_list.curlen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) chip->dma_list.curlen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) chip->dma_list.mem_addr = KDATA_DMA_XFER0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) chip->msrc_list.curlen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) chip->msrc_list.max = MAX_INSTANCE_MINISRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) static int snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) MINISRC_IN_BUFFER_SIZE / 2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) int address, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) * the revb memory map has 0x1100 through 0x1c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) * free.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) * align instance address to 256 bytes so that its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) * shifted list address is aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) * list address = (mem address >> 1) >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) data_bytes = ALIGN(data_bytes, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) address = 0x1100 + ((data_bytes/2) * index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if ((address + (data_bytes/2)) >= 0x1c00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) "no memory for %d bytes at ind %d (addr 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) data_bytes, index, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) s->number = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) s->inst.code = 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) s->inst.data = address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) for (i = data_bytes / 2; i > 0; address++, i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) address, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) * this works for the reference board, have to find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) * out about others
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) * this needs more magic for 4 speaker, but..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) snd_m3_amp_enable(struct snd_m3 *chip, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) int io = chip->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) u16 gpo, polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) if (! chip->external_amp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) polarity = enable ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) polarity = polarity << chip->amp_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) gpo = 1 << chip->amp_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) outw(~gpo, io + GPIO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) outw(inw(io + GPIO_DIRECTION) | gpo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) io + GPIO_DIRECTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) io + GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) outw(0xffff, io + GPIO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) snd_m3_hv_init(struct snd_m3 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) unsigned long io = chip->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) if (!chip->is_omnibook)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) * Volume buttons on some HP OmniBook laptops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) * require some GPIO magic to work correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) outw(0xffff, io + GPIO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) outw(0x0000, io + GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) outw(~val, io + GPIO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) outw(val, io + GPIO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) outw(0xffff, io + GPIO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) snd_m3_chip_init(struct snd_m3 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) struct pci_dev *pcidev = chip->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) unsigned long io = chip->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) u32 n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) u8 t; /* makes as much sense as 'n', no? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) DISABLE_LEGACY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) n |= chip->hv_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) /* For some reason we must always use reduced debounce. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) n |= REDUCED_DEBOUNCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) n &= ~INT_CLK_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) if (!chip->allegro_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) n &= ~INT_CLK_MULT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) n |= INT_CLK_SRC_NOT_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) if (chip->allegro_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) n |= IN_CLK_12MHZ_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) t = inb(chip->iobase + ASSP_CONTROL_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) t |= ASSP_CLK_49MHZ_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) t |= ASSP_0_WS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) outb(t, chip->iobase + ASSP_CONTROL_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) outb(0x00, io + HARDWARE_VOL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) outb(0x88, io + SHADOW_MIX_REG_VOICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) outb(0x88, io + HW_VOL_COUNTER_VOICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) outb(0x88, io + SHADOW_MIX_REG_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) outb(0x88, io + HW_VOL_COUNTER_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) snd_m3_enable_ints(struct snd_m3 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) unsigned long io = chip->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) /* TODO: MPU401 not supported yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) if (chip->hv_config & HV_CTRL_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) val |= HV_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) outb(val, chip->iobase + HOST_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) outw(val, io + HOST_INT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) io + ASSP_CONTROL_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) static int snd_m3_free(struct snd_m3 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) struct m3_dma *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) cancel_work_sync(&chip->hwvol_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) #ifdef CONFIG_SND_MAESTRO3_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) if (chip->input_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) input_unregister_device(chip->input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) if (chip->substreams) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) for (i = 0; i < chip->num_substreams; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) s = &chip->substreams[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) /* check surviving pcms; this should not happen though.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) if (s->substream && s->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) snd_m3_pcm_stop(chip, s, s->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) kfree(chip->substreams);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) if (chip->iobase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) vfree(chip->suspend_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) if (chip->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) if (chip->iobase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) pci_release_regions(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) release_firmware(chip->assp_kernel_image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) release_firmware(chip->assp_minisrc_image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) pci_disable_device(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) * APM support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) static int m3_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) struct snd_m3 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) int i, dsp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) if (chip->suspend_mem == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) chip->in_suspend = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) cancel_work_sync(&chip->hwvol_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) snd_ac97_suspend(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) msleep(10); /* give the assp a chance to idle.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) snd_m3_assp_halt(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) /* save dsp image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) dsp_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) chip->suspend_mem[dsp_index++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) chip->suspend_mem[dsp_index++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) static int m3_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) struct snd_m3 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) int i, dsp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) if (chip->suspend_mem == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) /* first lets just bring everything back. .*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) snd_m3_outw(chip, 0, 0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) snd_m3_outw(chip, 0, 0x56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) snd_m3_chip_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) snd_m3_assp_halt(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) snd_m3_ac97_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) /* restore dsp image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) dsp_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) chip->suspend_mem[dsp_index++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) chip->suspend_mem[dsp_index++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) /* tell the dma engine to restart itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) KDATA_DMA_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) /* restore ac97 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) snd_ac97_resume(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) snd_m3_assp_continue(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) snd_m3_enable_ints(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) snd_m3_amp_enable(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) snd_m3_hv_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) chip->in_suspend = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) static SIMPLE_DEV_PM_OPS(m3_pm, m3_suspend, m3_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) #define M3_PM_OPS &m3_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) #define M3_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) #ifdef CONFIG_SND_MAESTRO3_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) static int snd_m3_input_register(struct snd_m3 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) struct input_dev *input_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) input_dev = input_allocate_device();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) if (!input_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) pci_name(chip->pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) input_dev->name = chip->card->driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) input_dev->phys = chip->phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) input_dev->id.bustype = BUS_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) input_dev->id.vendor = chip->pci->vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) input_dev->id.product = chip->pci->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) input_dev->dev.parent = &chip->pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) __set_bit(EV_KEY, input_dev->evbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) __set_bit(KEY_MUTE, input_dev->keybit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) __set_bit(KEY_VOLUMEUP, input_dev->keybit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) err = input_register_device(input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) input_free_device(input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) chip->input_dev = input_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) #endif /* CONFIG_INPUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) static int snd_m3_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) struct snd_m3 *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) return snd_m3_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) snd_m3_create(struct snd_card *card, struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) int enable_amp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) int amp_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) struct snd_m3 **chip_ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) struct snd_m3 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) const struct snd_pci_quirk *quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .dev_free = snd_m3_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) *chip_ret = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) if (pci_enable_device(pci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) /* check, if we can restrict PCI DMA transfers to 28 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) if (dma_set_mask(&pci->dev, DMA_BIT_MASK(28)) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(28)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) dev_err(card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) "architecture does not support 28bit PCI busmaster DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) chip = kzalloc(sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) if (chip == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) spin_lock_init(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) switch (pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) case PCI_DEVICE_ID_ESS_ALLEGRO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) case PCI_DEVICE_ID_ESS_ALLEGRO_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) case PCI_DEVICE_ID_ESS_CANYON3D_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) chip->allegro_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) INIT_WORK(&chip->hwvol_work, snd_m3_update_hw_volume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) chip->external_amp = enable_amp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) if (amp_gpio >= 0 && amp_gpio <= 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) chip->amp_gpio = amp_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) if (quirk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) dev_info(card->dev, "set amp-gpio for '%s'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) snd_pci_quirk_name(quirk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) chip->amp_gpio = quirk->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) } else if (chip->allegro_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) else /* presumably this is for all 'maestro3's.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) chip->amp_gpio = GPO_EXT_AMP_M3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) if (quirk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) dev_info(card->dev, "enabled irda workaround for '%s'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) snd_pci_quirk_name(quirk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) chip->irda_workaround = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) if (quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) chip->hv_config = quirk->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) chip->is_omnibook = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) chip->num_substreams = NR_DSPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) if (chip->substreams == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) err = request_firmware(&chip->assp_kernel_image,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) "ess/maestro3_assp_kernel.fw", &pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) goto free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) err = request_firmware(&chip->assp_minisrc_image,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) "ess/maestro3_assp_minisrc.fw", &pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) goto free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) err = pci_request_regions(pci, card->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) goto free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) chip->iobase = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) /* just to be sure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) snd_m3_chip_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) snd_m3_assp_halt(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) snd_m3_ac97_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) snd_m3_amp_enable(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) snd_m3_hv_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) KBUILD_MODNAME, chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) goto free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) chip->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) chip->suspend_mem =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) vmalloc(array_size(sizeof(u16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) REV_B_CODE_MEMORY_LENGTH +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) REV_B_DATA_MEMORY_LENGTH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) if (chip->suspend_mem == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) dev_warn(card->dev, "can't allocate apm buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) goto free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) if ((err = snd_m3_mixer(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) for (i = 0; i < chip->num_substreams; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) struct m3_dma *s = &chip->substreams[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) if ((err = snd_m3_pcm(chip, 0)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) #ifdef CONFIG_SND_MAESTRO3_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if (chip->hv_config & HV_CTRL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) err = snd_m3_input_register(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) dev_warn(card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) "Input device registration failed with error %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) snd_m3_enable_ints(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) snd_m3_assp_continue(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) *chip_ret = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) free_chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) snd_m3_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) struct snd_m3 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) /* don't pick up modems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) switch (pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) case PCI_DEVICE_ID_ESS_ALLEGRO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) case PCI_DEVICE_ID_ESS_ALLEGRO_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) strcpy(card->driver, "Allegro");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) case PCI_DEVICE_ID_ESS_CANYON3D_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) strcpy(card->driver, "Canyon3D-2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) strcpy(card->driver, "Maestro3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) err = snd_m3_create(card, pci, external_amp[dev], amp_gpio[dev], &chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) goto free_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) card->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) sprintf(card->shortname, "ESS %s PCI", card->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) sprintf(card->longname, "%s at 0x%lx, irq %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) card->shortname, chip->iobase, chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) goto free_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) #if 0 /* TODO: not supported yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) /* TODO enable MIDI IRQ and I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) chip->iobase + MPU401_DATA_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) -1, &chip->rmidi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) dev_warn(card->dev, "no MIDI support.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) free_card:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) static void snd_m3_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) static struct pci_driver m3_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) .id_table = snd_m3_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) .probe = snd_m3_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) .remove = snd_m3_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .pm = M3_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) module_pci_driver(m3_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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