^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* -*- linux-c -*- *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * ALSA driver for the digigram lx6464es interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * adapted upstream headers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef LX_DEFS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define LX_DEFS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* code adapted from ethersound.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define XES_FREQ_COUNT8_MASK 0x00001FFF /* compteur 25MHz entre 8 ech. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define XES_FREQ_COUNT8_44_MIN 0x00001288 /* 25M /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * [ 44k - ( 44.1k + 48k ) / 2 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * * 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define XES_FREQ_COUNT8_44_MAX 0x000010F0 /* 25M / [ ( 44.1k + 48k ) / 2 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * * 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define XES_FREQ_COUNT8_48_MAX 0x00000F08 /* 25M /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * [ 48k + ( 44.1k + 48k ) / 2 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * * 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* code adapted from LXES_registers.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IOCR_OUTPUTS_OFFSET 0 /* (rw) offset for the number of OUTs in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * ConfES register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IOCR_INPUTS_OFFSET 8 /* (rw) offset for the number of INs in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * ConfES register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FREQ_RATIO_OFFSET 19 /* (rw) offset for frequency ratio in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * ConfES register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FREQ_RATIO_SINGLE_MODE 0x01 /* value for single mode frequency ratio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * sample rate = frequency rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CONFES_READ_PART_MASK 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CONFES_WRITE_PART_MASK 0x00F80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* code adapted from if_drv_mb.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MASK_SYS_STATUS_ERROR (1L << 31) /* events that lead to a PCI irq if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * not yet pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MASK_SYS_STATUS_URUN (1L << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MASK_SYS_STATUS_ORUN (1L << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MASK_SYS_STATUS_EOBO (1L << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MASK_SYS_STATUS_EOBI (1L << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MASK_SYS_STATUS_FREQ (1L << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MASK_SYS_STATUS_ESA (1L << 25) /* reserved, this is set by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * XES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MASK_SYS_STATUS_TIMER (1L << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MASK_SYS_ASYNC_EVENTS (MASK_SYS_STATUS_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MASK_SYS_STATUS_URUN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MASK_SYS_STATUS_ORUN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MASK_SYS_STATUS_EOBO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MASK_SYS_STATUS_EOBI | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MASK_SYS_STATUS_FREQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MASK_SYS_STATUS_ESA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MASK_SYS_PCI_EVENTS (MASK_SYS_ASYNC_EVENTS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MASK_SYS_STATUS_TIMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MASK_SYS_TIMER_COUNT 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MASK_SYS_STATUS_EOT_PLX (1L << 22) /* event that remains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * internal: reserved fo end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * of plx dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MASK_SYS_STATUS_XES (1L << 21) /* event that remains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * internal: pending XES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MASK_SYS_STATUS_CMD_DONE (1L << 20) /* alternate command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * management: notify driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * instead of polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MAX_STREAM_BUFFER 5 /* max amount of stream buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MICROBLAZE_IBL_MIN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MICROBLAZE_IBL_DEFAULT 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MICROBLAZE_IBL_MAX 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* #define MASK_GRANULARITY (2*MICROBLAZE_IBL_MAX-1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* command opcodes, see reference for details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) the capture bit position in the object_id field in driver commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) depends upon the number of managed channels. For now, 64 IN + 64 OUT are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) supported. HOwever, the communication protocol forsees 1024 channels, hence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) bit 10 indicates a capture (input) object).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ID_IS_CAPTURE (1L << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ID_OFFSET 13 /* object ID is at the 13th bit in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * 1st command word.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ID_CH_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OPCODE_OFFSET 24 /* offset of the command opcode in the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * command word.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) enum cmd_mb_opcodes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) CMD_00_INFO_DEBUG = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) CMD_01_GET_SYS_CFG = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) CMD_02_SET_GRANULARITY = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) CMD_03_SET_TIMER_IRQ = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) CMD_04_GET_EVENT = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) CMD_05_GET_PIPES = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) CMD_06_ALLOCATE_PIPE = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) CMD_07_RELEASE_PIPE = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CMD_08_ASK_BUFFERS = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) CMD_09_STOP_PIPE = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) CMD_0A_GET_PIPE_SPL_COUNT = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) CMD_0B_TOGGLE_PIPE_STATE = 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) CMD_0C_DEF_STREAM = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) CMD_0D_SET_MUTE = 0x0d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) CMD_0E_GET_STREAM_SPL_COUNT = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) CMD_0F_UPDATE_BUFFER = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) CMD_10_GET_BUFFER = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) CMD_11_CANCEL_BUFFER = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) CMD_12_GET_PEAK = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) CMD_13_SET_STREAM_STATE = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) CMD_14_INVALID = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* pipe states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) enum pipe_state_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PSTATE_IDLE = 0, /* the pipe is not processed in the XES_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * (free or stopped, or paused). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PSTATE_RUN = 1, /* sustained play/record state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PSTATE_PURGE = 2, /* the ES channels are now off, render pipes do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * not DMA, record pipe do a last DMA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PSTATE_ACQUIRE = 3, /* the ES channels are now on, render pipes do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * not yet increase their sample count, record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * pipes do not DMA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PSTATE_CLOSING = 4, /* the pipe is releasing, and may not yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * receive an "alloc" command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* stream states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) enum stream_state_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) SSTATE_STOP = 0x00, /* setting to stop resets the stream spl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * count.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SSTATE_RUN = (0x01 << 0), /* start DMA and spl count handling. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) SSTATE_PAUSE = (0x01 << 1), /* pause DMA and spl count handling. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* buffer flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) enum buffer_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) BF_VALID = 0x80, /* set if the buffer is valid, clear if free.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) BF_CURRENT = 0x40, /* set if this is the current buffer (there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * always a current buffer).*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) BF_NOTIFY_EOB = 0x20, /* set if this buffer must cause a PCI event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * when finished.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) BF_CIRCULAR = 0x10, /* set if buffer[1] must be copied to buffer[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * by the end of this buffer.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) BF_64BITS_ADR = 0x08, /* set if the hi part of the address is valid.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) BF_xx = 0x04, /* future extension.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) BF_EOB = 0x02, /* set if finished, but not yet free.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) BF_PAUSE = 0x01, /* pause stream at buffer end.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) BF_ZERO = 0x00, /* no flags (init).*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Stream Flags definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) enum stream_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) SF_ZERO = 0x00000000, /* no flags (stream invalid). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SF_VALID = 0x10000000, /* the stream has a valid DMA_conf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * info (setstreamformat). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SF_XRUN = 0x20000000, /* the stream is un x-run state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SF_START = 0x40000000, /* the DMA is running.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SF_ASIO = 0x80000000, /* ASIO.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MASK_SPL_COUNT_HI 0x00FFFFFF /* 4 MSBits are status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PSTATE_OFFSET 28 /* 4 MSBits are status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MASK_STREAM_HAS_MAPPING (1L << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MASK_STREAM_IS_ASIO (1L << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define STREAM_FMT_OFFSET 10 /* the stream fmt bits start at the 10th
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * bit in the command word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define STREAM_FMT_16b 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define STREAM_FMT_intel 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define FREQ_FIELD_OFFSET 15 /* offset of the freq field in the response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define BUFF_FLAGS_OFFSET 24 /* offset of the buffer flags in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * response word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MASK_DATA_SIZE 0x00FFFFFF /* this must match the field size of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * datasize in the buffer_t structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MASK_BUFFER_ID 0xFF /* the cancel command awaits a buffer ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * may be 0xFF for "current". */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* code adapted from PcxErr_e.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Bits masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ERROR_MASK 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SOURCE_MASK 0x7800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define E_SOURCE_BOARD 0x4000 /* 8 >> 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define E_SOURCE_DRV 0x2000 /* 4 >> 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define E_SOURCE_API 0x1000 /* 2 >> 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Error tools */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define E_SOURCE_TOOLS 0x0800 /* 1 >> 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Error pcxaudio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define E_SOURCE_AUDIO 0x1800 /* 3 >> 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Error virtual pcx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define E_SOURCE_VPCX 0x2800 /* 5 >> 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Error dispatcher */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define E_SOURCE_DISPATCHER 0x3000 /* 6 >> 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Error from CobraNet firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define E_SOURCE_COBRANET 0x3800 /* 7 >> 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define E_SOURCE_USER 0x7800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CLASS_MASK 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CODE_MASK 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Bits values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Values for the error/warning bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ERROR_VALUE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define WARNING_VALUE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Class values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define E_CLASS_GENERAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define E_CLASS_INVALID_CMD 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define E_CLASS_INVALID_STD_OBJECT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define E_CLASS_RSRC_IMPOSSIBLE 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define E_CLASS_WRONG_CONTEXT 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define E_CLASS_BAD_SPECIFIC_PARAMETER 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define E_CLASS_REAL_TIME_ERROR 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define E_CLASS_DIRECTSHOW 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define E_CLASS_FREE 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Complete DRV error code for the general class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ED_GN (ERROR_VALUE | E_SOURCE_DRV | E_CLASS_GENERAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ED_CONCURRENCY (ED_GN | 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ED_DSP_CRASHED (ED_GN | 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ED_UNKNOWN_BOARD (ED_GN | 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ED_NOT_INSTALLED (ED_GN | 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ED_CANNOT_OPEN_SVC_MANAGER (ED_GN | 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ED_CANNOT_READ_REGISTRY (ED_GN | 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define ED_DSP_VERSION_MISMATCH (ED_GN | 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ED_UNAVAILABLE_FEATURE (ED_GN | 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ED_CANCELLED (ED_GN | 0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ED_NO_RESPONSE_AT_IRQA (ED_GN | 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ED_INVALID_ADDRESS (ED_GN | 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define ED_DSP_CORRUPTED (ED_GN | 0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define ED_PENDING_OPERATION (ED_GN | 0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define ED_NET_ALLOCATE_MEMORY_IMPOSSIBLE (ED_GN | 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define ED_NET_REGISTER_ERROR (ED_GN | 0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define ED_NET_THREAD_ERROR (ED_GN | 0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define ED_NET_OPEN_ERROR (ED_GN | 0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ED_NET_CLOSE_ERROR (ED_GN | 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ED_NET_NO_MORE_PACKET (ED_GN | 0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define ED_NET_NO_MORE_BUFFER (ED_GN | 0x1A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ED_NET_SEND_ERROR (ED_GN | 0x1B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ED_NET_RECEIVE_ERROR (ED_GN | 0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define ED_NET_WRONG_MSG_SIZE (ED_GN | 0x1D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ED_NET_WAIT_ERROR (ED_GN | 0x1E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ED_NET_EEPROM_ERROR (ED_GN | 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define ED_INVALID_RS232_COM_NUMBER (ED_GN | 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define ED_INVALID_RS232_INIT (ED_GN | 0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define ED_FILE_ERROR (ED_GN | 0x22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define ED_INVALID_GPIO_CMD (ED_GN | 0x23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ED_RS232_ALREADY_OPENED (ED_GN | 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define ED_RS232_NOT_OPENED (ED_GN | 0x25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ED_GPIO_ALREADY_OPENED (ED_GN | 0x26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ED_GPIO_NOT_OPENED (ED_GN | 0x27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ED_REGISTRY_ERROR (ED_GN | 0x28) /* <- NCX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ED_INVALID_SERVICE (ED_GN | 0x29) /* <- NCX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define ED_READ_FILE_ALREADY_OPENED (ED_GN | 0x2a) /* <- Decalage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * pour RCX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * (old 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ED_READ_FILE_INVALID_COMMAND (ED_GN | 0x2b) /* ~ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ED_READ_FILE_INVALID_PARAMETER (ED_GN | 0x2c) /* ~ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ED_READ_FILE_ALREADY_CLOSED (ED_GN | 0x2d) /* ~ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ED_READ_FILE_NO_INFORMATION (ED_GN | 0x2e) /* ~ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ED_READ_FILE_INVALID_HANDLE (ED_GN | 0x2f) /* ~ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define ED_READ_FILE_END_OF_FILE (ED_GN | 0x30) /* ~ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ED_READ_FILE_ERROR (ED_GN | 0x31) /* ~ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ED_DSP_CRASHED_EXC_DSPSTACK_OVERFLOW (ED_GN | 0x32) /* <- Decalage pour
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * PCX (old 0x14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ED_DSP_CRASHED_EXC_SYSSTACK_OVERFLOW (ED_GN | 0x33) /* ~ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define ED_DSP_CRASHED_EXC_ILLEGAL (ED_GN | 0x34) /* ~ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define ED_DSP_CRASHED_EXC_TIMER_REENTRY (ED_GN | 0x35) /* ~ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define ED_DSP_CRASHED_EXC_FATAL_ERROR (ED_GN | 0x36) /* ~ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define ED_FLASH_PCCARD_NOT_PRESENT (ED_GN | 0x37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define ED_NO_CURRENT_CLOCK (ED_GN | 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Complete DRV error code for real time class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define ED_RT (ERROR_VALUE | E_SOURCE_DRV | E_CLASS_REAL_TIME_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define ED_DSP_TIMED_OUT (ED_RT | 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define ED_DSP_CHK_TIMED_OUT (ED_RT | 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define ED_STREAM_OVERRUN (ED_RT | 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define ED_DSP_BUSY (ED_RT | 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define ED_DSP_SEMAPHORE_TIME_OUT (ED_RT | 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define ED_BOARD_TIME_OUT (ED_RT | 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define ED_XILINX_ERROR (ED_RT | 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define ED_COBRANET_ITF_NOT_RESPONDING (ED_RT | 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Complete BOARD error code for the invaid standard object class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define EB_ISO (ERROR_VALUE | E_SOURCE_BOARD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) E_CLASS_INVALID_STD_OBJECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define EB_INVALID_EFFECT (EB_ISO | 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define EB_INVALID_PIPE (EB_ISO | 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define EB_INVALID_STREAM (EB_ISO | 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define EB_INVALID_AUDIO (EB_ISO | 0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Complete BOARD error code for impossible resource allocation class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define EB_RI (ERROR_VALUE | E_SOURCE_BOARD | E_CLASS_RSRC_IMPOSSIBLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define EB_ALLOCATE_ALL_STREAM_TRANSFERT_BUFFERS_IMPOSSIBLE (EB_RI | 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define EB_ALLOCATE_PIPE_SAMPLE_BUFFER_IMPOSSIBLE (EB_RI | 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define EB_ALLOCATE_MEM_STREAM_IMPOSSIBLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) EB_ALLOCATE_ALL_STREAM_TRANSFERT_BUFFERS_IMPOSSIBLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define EB_ALLOCATE_MEM_PIPE_IMPOSSIBLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) EB_ALLOCATE_PIPE_SAMPLE_BUFFER_IMPOSSIBLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define EB_ALLOCATE_DIFFERED_CMD_IMPOSSIBLE (EB_RI | 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define EB_TOO_MANY_DIFFERED_CMD (EB_RI | 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define EB_RBUFFERS_TABLE_OVERFLOW (EB_RI | 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define EB_ALLOCATE_EFFECTS_IMPOSSIBLE (EB_RI | 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define EB_ALLOCATE_EFFECT_POS_IMPOSSIBLE (EB_RI | 0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define EB_RBUFFER_NOT_AVAILABLE (EB_RI | 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define EB_ALLOCATE_CONTEXT_LIII_IMPOSSIBLE (EB_RI | 0x0B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define EB_STATUS_DIALOG_IMPOSSIBLE (EB_RI | 0x1D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define EB_CONTROL_CMD_IMPOSSIBLE (EB_RI | 0x1E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define EB_STATUS_SEND_IMPOSSIBLE (EB_RI | 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define EB_ALLOCATE_PIPE_IMPOSSIBLE (EB_RI | 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define EB_ALLOCATE_STREAM_IMPOSSIBLE (EB_RI | 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define EB_ALLOCATE_AUDIO_IMPOSSIBLE (EB_RI | 0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Complete BOARD error code for wrong call context class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define EB_WCC (ERROR_VALUE | E_SOURCE_BOARD | E_CLASS_WRONG_CONTEXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define EB_CMD_REFUSED (EB_WCC | 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define EB_START_STREAM_REFUSED (EB_WCC | 0xFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define EB_SPC_REFUSED (EB_WCC | 0xFD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define EB_CSN_REFUSED (EB_WCC | 0xFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define EB_CSE_REFUSED (EB_WCC | 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #endif /* LX_DEFS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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