^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support for Digigram Lola PCI-e boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "lola.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Standard options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_PARM_DESC(index, "Index value for Digigram Lola driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_PARM_DESC(id, "ID string for Digigram Lola driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODULE_PARM_DESC(enable, "Enable Digigram Lola driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Lola-specific options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* for instance use always max granularity which is compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * with all sample rates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int granularity[SNDRV_CARDS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [0 ... (SNDRV_CARDS - 1)] = LOLA_GRANULARITY_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* below a sample_rate of 16kHz the analogue audio quality is NOT excellent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int sample_rate_min[SNDRV_CARDS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) [0 ... (SNDRV_CARDS - 1) ] = 16000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) module_param_array(granularity, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MODULE_PARM_DESC(granularity, "Granularity value");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) module_param_array(sample_rate_min, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MODULE_PARM_DESC(sample_rate_min, "Minimal sample rate");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MODULE_SUPPORTED_DEVICE("{{Digigram, Lola}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_DESCRIPTION("Digigram Lola driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifdef CONFIG_SND_DEBUG_VERBOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define verbose_debug(fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) do { if (debug > 1) pr_debug(SFX fmt, ##args); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define verbose_debug(fmt, args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * pseudo-codec read/write via CORB/RIRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int corb_send_verb(struct lola *chip, unsigned int nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int verb, unsigned int data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int extdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) chip->last_cmd_nid = nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) chip->last_verb = verb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) chip->last_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) chip->last_extdata = extdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) data |= (nid << 20) | (verb << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (chip->rirb.cmds < LOLA_CORB_ENTRIES - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int wp = chip->corb.wp + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) wp %= LOLA_CORB_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) chip->corb.wp = wp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) chip->corb.buf[wp * 2] = cpu_to_le32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) chip->corb.buf[wp * 2 + 1] = cpu_to_le32(extdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) lola_writew(chip, BAR0, CORBWP, wp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) chip->rirb.cmds++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void lola_queue_unsol_event(struct lola *chip, unsigned int res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int res_ex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) lola_update_ext_clock_freq(chip, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* retrieve RIRB entry - called from interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void lola_update_rirb(struct lola *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int rp, wp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 res, res_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) wp = lola_readw(chip, BAR0, RIRBWP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (wp == chip->rirb.wp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) chip->rirb.wp = wp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) while (chip->rirb.rp != wp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) chip->rirb.rp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) chip->rirb.rp %= LOLA_CORB_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) res = le32_to_cpu(chip->rirb.buf[rp]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (res_ex & LOLA_RIRB_EX_UNSOL_EV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) lola_queue_unsol_event(chip, res, res_ex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) else if (chip->rirb.cmds) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) chip->res = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) chip->res_ex = res_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) chip->rirb.cmds--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int rirb_get_response(struct lola *chip, unsigned int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int *extval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) timeout = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (chip->polling_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) lola_update_rirb(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!chip->rirb.cmds) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) *val = chip->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (extval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *extval = chip->res_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) verbose_debug("get_response: %x, %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) chip->res, chip->res_ex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (chip->res_ex & LOLA_RIRB_EX_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_warn(chip->card->dev, "RIRB ERROR: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "NID=%x, verb=%x, data=%x, ext=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) chip->last_cmd_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) chip->last_verb, chip->last_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) chip->last_extdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_warn(chip->card->dev, "RIRB response error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (!chip->polling_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_warn(chip->card->dev, "switching to polling mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) chip->polling_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* aynchronous write of a codec verb with data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int lola_codec_write(struct lola *chip, unsigned int nid, unsigned int verb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned int data, unsigned int extdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) verbose_debug("codec_write NID=%x, verb=%x, data=%x, ext=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) nid, verb, data, extdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return corb_send_verb(chip, nid, verb, data, extdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* write a codec verb with data and read the returned status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int lola_codec_read(struct lola *chip, unsigned int nid, unsigned int verb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int data, unsigned int extdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int *val, unsigned int *extval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) verbose_debug("codec_read NID=%x, verb=%x, data=%x, ext=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) nid, verb, data, extdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) err = corb_send_verb(chip, nid, verb, data, extdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) err = rirb_get_response(chip, val, extval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* flush all pending codec writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int lola_codec_flush(struct lola *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return rirb_get_response(chip, &tmp, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static irqreturn_t lola_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct lola *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int notify_ins, notify_outs, error_ins, error_outs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) notify_ins = notify_outs = error_ins = error_outs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int status, in_sts, out_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) status = lola_readl(chip, BAR1, DINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (!status || status == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) in_sts = lola_readl(chip, BAR1, DIINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) out_sts = lola_readl(chip, BAR1, DOINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* clear Input Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) for (i = 0; in_sts && i < chip->pcm[CAPT].num_streams; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!(in_sts & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) in_sts &= ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) reg = lola_dsd_read(chip, i, STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (reg & LOLA_DSD_STS_DESE) /* error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) error_ins |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (reg & LOLA_DSD_STS_BCIS) /* notify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) notify_ins |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) lola_dsd_write(chip, i, STS, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* clear Output Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) for (i = 0; out_sts && i < chip->pcm[PLAY].num_streams; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!(out_sts & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) out_sts &= ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) reg = lola_dsd_read(chip, i + MAX_STREAM_IN_COUNT, STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (reg & LOLA_DSD_STS_DESE) /* error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) error_outs |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (reg & LOLA_DSD_STS_BCIS) /* notify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) notify_outs |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) lola_dsd_write(chip, i + MAX_STREAM_IN_COUNT, STS, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (status & LOLA_DINT_CTRL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned char rbsts; /* ring status is byte access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) rbsts = lola_readb(chip, BAR0, RIRBSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) rbsts &= LOLA_RIRB_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (rbsts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) lola_writeb(chip, BAR0, RIRBSTS, rbsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) rbsts = lola_readb(chip, BAR0, CORBSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) rbsts &= LOLA_CORB_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (rbsts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) lola_writeb(chip, BAR0, CORBSTS, rbsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) lola_update_rirb(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (status & (LOLA_DINT_FIFOERR | LOLA_DINT_MUERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* clear global fifo error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) lola_writel(chip, BAR1, DINTSTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) (status & (LOLA_DINT_FIFOERR | LOLA_DINT_MUERR)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) lola_pcm_update(chip, &chip->pcm[CAPT], notify_ins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) lola_pcm_update(chip, &chip->pcm[PLAY], notify_outs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int reset_controller(struct lola *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int gctl = lola_readl(chip, BAR0, GCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned long end_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (gctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* to be sure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) lola_writel(chip, BAR1, BOARD_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) chip->cold_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) lola_writel(chip, BAR0, GCTL, LOLA_GCTL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) end_time = jiffies + msecs_to_jiffies(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) gctl = lola_readl(chip, BAR0, GCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (gctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } while (time_before(jiffies, end_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (!gctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(chip->card->dev, "cannot reset controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void lola_irq_enable(struct lola *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* enalbe all I/O streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) val = (1 << chip->pcm[PLAY].num_streams) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) lola_writel(chip, BAR1, DOINTCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) val = (1 << chip->pcm[CAPT].num_streams) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) lola_writel(chip, BAR1, DIINTCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* enable global irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) val = LOLA_DINT_GLOBAL | LOLA_DINT_CTRL | LOLA_DINT_FIFOERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) LOLA_DINT_MUERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) lola_writel(chip, BAR1, DINTCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void lola_irq_disable(struct lola *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) lola_writel(chip, BAR1, DINTCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) lola_writel(chip, BAR1, DIINTCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) lola_writel(chip, BAR1, DOINTCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int setup_corb_rirb(struct lola *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned char tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned long end_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PAGE_SIZE, &chip->rb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) chip->corb.addr = chip->rb.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) chip->corb.buf = (__le32 *)chip->rb.area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) chip->rirb.addr = chip->rb.addr + 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) chip->rirb.buf = (__le32 *)(chip->rb.area + 2048);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* disable ringbuffer DMAs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) lola_writeb(chip, BAR0, RIRBCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) lola_writeb(chip, BAR0, CORBCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) end_time = jiffies + msecs_to_jiffies(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (!lola_readb(chip, BAR0, RIRBCTL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) !lola_readb(chip, BAR0, CORBCTL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } while (time_before(jiffies, end_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* CORB set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) lola_writel(chip, BAR0, CORBLBASE, (u32)chip->corb.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) lola_writel(chip, BAR0, CORBUBASE, upper_32_bits(chip->corb.addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* set the corb size to 256 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) lola_writeb(chip, BAR0, CORBSIZE, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* set the corb write pointer to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) lola_writew(chip, BAR0, CORBWP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* reset the corb hw read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) lola_writew(chip, BAR0, CORBRP, LOLA_RBRWP_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* enable corb dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) lola_writeb(chip, BAR0, CORBCTL, LOLA_RBCTL_DMA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* clear flags if set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) tmp = lola_readb(chip, BAR0, CORBSTS) & LOLA_CORB_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) lola_writeb(chip, BAR0, CORBSTS, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) chip->corb.wp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* RIRB set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) lola_writel(chip, BAR0, RIRBLBASE, (u32)chip->rirb.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) lola_writel(chip, BAR0, RIRBUBASE, upper_32_bits(chip->rirb.addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* set the rirb size to 256 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) lola_writeb(chip, BAR0, RIRBSIZE, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* reset the rirb hw write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) lola_writew(chip, BAR0, RIRBWP, LOLA_RBRWP_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* set N=1, get RIRB response interrupt for new entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) lola_writew(chip, BAR0, RINTCNT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* enable rirb dma and response irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) lola_writeb(chip, BAR0, RIRBCTL, LOLA_RBCTL_DMA_EN | LOLA_RBCTL_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* clear flags if set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) tmp = lola_readb(chip, BAR0, RIRBSTS) & LOLA_RIRB_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) lola_writeb(chip, BAR0, RIRBSTS, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) chip->rirb.rp = chip->rirb.cmds = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void stop_corb_rirb(struct lola *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* disable ringbuffer DMAs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) lola_writeb(chip, BAR0, RIRBCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) lola_writeb(chip, BAR0, CORBCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void lola_reset_setups(struct lola *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* update the granularity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) lola_set_granularity(chip, chip->granularity, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* update the sample clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) lola_set_clock_index(chip, chip->clock.cur_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* enable unsolicited events of the clock widget */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) lola_enable_clock_events(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* update the analog gains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) lola_setup_all_analog_gains(chip, CAPT, false); /* input, update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* update SRC configuration if applicable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) lola_set_src_config(chip, chip->input_src_mask, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* update the analog outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) lola_setup_all_analog_gains(chip, PLAY, false); /* output, update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int lola_parse_tree(struct lola *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int nid, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) err = lola_read_param(chip, 0, LOLA_PAR_VENDOR_ID, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_err(chip->card->dev, "Can't read VENDOR_ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) val >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (val != 0x1369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_err(chip->card->dev, "Unknown codec vendor 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) err = lola_read_param(chip, 1, LOLA_PAR_FUNCTION_TYPE, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_err(chip->card->dev, "Can't read FUNCTION_TYPE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (val != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_err(chip->card->dev, "Unknown function type %d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) err = lola_read_param(chip, 1, LOLA_PAR_SPECIFIC_CAPS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_err(chip->card->dev, "Can't read SPECCAPS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) chip->lola_caps = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) chip->pin[CAPT].num_pins = LOLA_AFG_INPUT_PIN_COUNT(chip->lola_caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) chip->pin[PLAY].num_pins = LOLA_AFG_OUTPUT_PIN_COUNT(chip->lola_caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_dbg(chip->card->dev, "speccaps=0x%x, pins in=%d, out=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) chip->lola_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) chip->pin[CAPT].num_pins, chip->pin[PLAY].num_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (chip->pin[CAPT].num_pins > MAX_AUDIO_INOUT_COUNT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) chip->pin[PLAY].num_pins > MAX_AUDIO_INOUT_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev_err(chip->card->dev, "Invalid Lola-spec caps 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) nid = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) err = lola_init_pcm(chip, CAPT, &nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) err = lola_init_pcm(chip, PLAY, &nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) err = lola_init_pins(chip, CAPT, &nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) err = lola_init_pins(chip, PLAY, &nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (LOLA_AFG_CLOCK_WIDGET_PRESENT(chip->lola_caps)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) err = lola_init_clock_widget(chip, nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) nid++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (LOLA_AFG_MIXER_WIDGET_PRESENT(chip->lola_caps)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) err = lola_init_mixer_widget(chip, nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) nid++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* enable unsolicited events of the clock widget */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) err = lola_enable_clock_events(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* if last ResetController was not a ColdReset, we don't know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * the state of the card; initialize here again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (!chip->cold_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) lola_reset_setups(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) chip->cold_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* set the granularity if it is not the default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (chip->granularity != LOLA_GRANULARITY_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) lola_set_granularity(chip, chip->granularity, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void lola_stop_hw(struct lola *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) stop_corb_rirb(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) lola_irq_disable(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static void lola_free(struct lola *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (chip->initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) lola_stop_hw(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) lola_free_pcm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) lola_free_mixer(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (chip->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) free_irq(chip->irq, (void *)chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) iounmap(chip->bar[0].remap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) iounmap(chip->bar[1].remap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (chip->rb.area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) snd_dma_free_pages(&chip->rb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pci_release_regions(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pci_disable_device(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int lola_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) lola_free(device->device_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int lola_create(struct snd_card *card, struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int dev, struct lola **rchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct lola *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned int dever;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .dev_free = lola_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) *rchip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) err = pci_enable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) chip = kzalloc(sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (!chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) spin_lock_init(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mutex_init(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) chip->granularity = granularity[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) switch (chip->granularity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) chip->sample_rate_max = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) chip->sample_rate_max = 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) chip->sample_rate_max = 192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dev_warn(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) "Invalid granularity %d, reset to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) chip->granularity, LOLA_GRANULARITY_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) chip->granularity = LOLA_GRANULARITY_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) chip->sample_rate_max = 192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) chip->sample_rate_min = sample_rate_min[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (chip->sample_rate_min > chip->sample_rate_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev_warn(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) "Invalid sample_rate_min %d, reset to 16000\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) chip->sample_rate_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) chip->sample_rate_min = 16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) err = pci_request_regions(pci, DRVNAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) chip->bar[0].addr = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) chip->bar[0].remap_addr = pci_ioremap_bar(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) chip->bar[1].addr = pci_resource_start(pci, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) chip->bar[1].remap_addr = pci_ioremap_bar(pci, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (!chip->bar[0].remap_addr || !chip->bar[1].remap_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_err(chip->card->dev, "ioremap error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) err = reset_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (request_irq(pci->irq, lola_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) KBUILD_MODNAME, chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) chip->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dever = lola_readl(chip, BAR1, DEVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) chip->pcm[CAPT].num_streams = (dever >> 0) & 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) chip->pcm[PLAY].num_streams = (dever >> 10) & 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) chip->version = (dever >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dev_dbg(chip->card->dev, "streams in=%d, out=%d, version=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) chip->pcm[CAPT].num_streams, chip->pcm[PLAY].num_streams,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) chip->version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Test LOLA_BAR1_DEVER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (chip->pcm[CAPT].num_streams > MAX_STREAM_IN_COUNT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) chip->pcm[PLAY].num_streams > MAX_STREAM_OUT_COUNT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) (!chip->pcm[CAPT].num_streams &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) !chip->pcm[PLAY].num_streams)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dev_err(chip->card->dev, "invalid DEVER = %x\n", dever);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) err = setup_corb_rirb(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev_err(chip->card->dev, "Error creating device [card]!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) strcpy(card->driver, "Lola");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) strlcpy(card->shortname, "Digigram Lola", sizeof(card->shortname));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) snprintf(card->longname, sizeof(card->longname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) "%s at 0x%lx irq %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) card->shortname, chip->bar[0].addr, chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) strcpy(card->mixername, card->shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) lola_irq_enable(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) chip->initialized = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) *rchip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) errout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) lola_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static int lola_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct lola *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dev_err(&pci->dev, "Error creating card!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) err = lola_create(card, pci, dev, &chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) card->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) err = lola_parse_tree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) err = lola_create_pcm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) err = lola_create_mixer(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) lola_proc_debug_new(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static void lola_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* PCI IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const struct pci_device_id lola_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) { PCI_VDEVICE(DIGIGRAM, 0x0001) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) MODULE_DEVICE_TABLE(pci, lola_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* pci_driver definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static struct pci_driver lola_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .id_table = lola_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .probe = lola_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .remove = lola_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) module_pci_driver(lola_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags