^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for Intel ICH (i8x0) chipsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This code also contains alpha support for SiS 735 chipsets provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * for SiS735, so the code is not fully functional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) "{Intel,82901AB-ICH0},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "{Intel,82801BA-ICH2},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "{Intel,82801CA-ICH3},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "{Intel,82801DB-ICH4},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "{Intel,ICH5},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "{Intel,ICH6},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "{Intel,ICH7},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "{Intel,6300ESB},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "{Intel,ESB2},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "{Intel,MX440},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "{SiS,SI7012},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "{NVidia,nForce Audio},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "{NVidia,nForce2 Audio},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "{NVidia,nForce3 Audio},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "{NVidia,MCP04},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "{NVidia,MCP501},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "{NVidia,CK804},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "{NVidia,CK8},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "{NVidia,CK8S},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "{AMD,AMD768},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "{AMD,AMD8111},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "{ALI,M5455}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int ac97_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static char *ac97_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static bool buggy_semaphore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int buggy_irq = -1; /* auto-check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static bool xbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int spdif_aclink = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int inside_vm = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) module_param(index, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) module_param(id, charp, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) module_param(ac97_clock, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = allowlist + auto-detect, 1 = force autodetect).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) module_param(ac97_quirk, charp, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) module_param(buggy_semaphore, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) module_param(buggy_irq, bint, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) module_param(xbox, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) module_param(spdif_aclink, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) module_param(inside_vm, bint, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* just for backward compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static bool enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) module_param(enable, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int joystick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) module_param(joystick, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Direct registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ICHREG(x) ICH_REG_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DEFINE_REGSET(name,base) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) enum { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* busmaster blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DEFINE_REGSET(OFF, 0); /* offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DEFINE_REGSET(PI, 0x00); /* PCM in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DEFINE_REGSET(PO, 0x10); /* PCM out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DEFINE_REGSET(MC, 0x20); /* Mic in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* ICH4 busmaster blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DEFINE_REGSET(SP, 0x60); /* SPDIF out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* values for each busmaster block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* LVI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ICH_REG_LVI_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* SR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ICH_FIFOE 0x10 /* FIFO error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ICH_BCIS 0x08 /* buffer completion interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ICH_CELV 0x02 /* current equals last valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ICH_DCH 0x01 /* DMA controller halted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* PIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ICH_REG_PIV_MASK 0x1f /* mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ICH_IOCE 0x10 /* interrupt on completion enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ICH_FEIE 0x08 /* fifo error interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ICH_RESETREGS 0x02 /* reset busmaster registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ICH_STARTBM 0x01 /* start busmaster operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* global block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ICH_ACLINK 0x00000008 /* AClink shut off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ICH_GIE 0x00000001 /* GPI interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ICH_MD3 0x00020000 /* modem power down semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ICH_AD3 0x00010000 /* audio power down semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ICH_RCS 0x00008000 /* read completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ICH_POINT 0x00000040 /* playback interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ICH_PIINT 0x00000020 /* capture interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ICH_MOINT 0x00000004 /* modem playback interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ICH_MIINT 0x00000002 /* modem capture interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ICH_CAS 0x01 /* codec access semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ICH_REG_SDM 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ICH_DI2L_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ICH_DI1L_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ICH_SE 0x00000008 /* steer enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ICH_MAX_FRAGS 32 /* max hw frags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * registers for Ali5455
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* ALi 5455 busmaster blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ICH_REG_ALI_SCR = 0x00, /* System Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ICH_REG_ALI_SSR = 0x04, /* System Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ALI_CAS_SEM_BUSY 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ALI_CPR_ADDR_SECONDARY 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ALI_CPR_ADDR_READ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ALI_CSPSR_CODEC_READY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ALI_CSPSR_READ_OK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ALI_CSPSR_WRITE_OK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* interrupts for the whole chip by interrupt status register finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ALI_INT_MICIN2 (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ALI_INT_PCMIN2 (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define ALI_INT_I2SIN (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define ALI_INT_SPDIFIN (1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define ALI_INT_LFEOUT (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define ALI_INT_CENTEROUT (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define ALI_INT_CODECSPDIFOUT (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ALI_INT_MICIN (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ALI_INT_PCMOUT (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define ALI_INT_PCMIN (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ALI_INT_CPRAIS (1<<7) /* command port available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ALI_INT_SPRAIS (1<<5) /* status port available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define ALI_INT_GPIO (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define ICH_ALI_SC_RESET (1<<31) /* master reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define ICH_ALI_SC_AC97_DBL (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ICH_ALI_SC_IN_BITS (3<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define ICH_ALI_SC_OUT_BITS (3<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ICH_ALI_SC_6CH_CFG (3<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ICH_ALI_SC_PCM_4 (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ICH_ALI_SC_PCM_6 (2<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ICH_ALI_SC_PCM_246_MASK (3<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define ICH_ALI_SS_SEC_ID (3<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ICH_ALI_SS_PRI_ID (3<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ICH_ALI_IF_AC97SP (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ICH_ALI_IF_MC (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ICH_ALI_IF_PI (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ICH_ALI_IF_MC2 (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ICH_ALI_IF_PI2 (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ICH_ALI_IF_PO_SPDF (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ICH_ALI_IF_PO (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ICHD_PCMIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ICHD_PCMOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ICHD_MIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ICHD_MIC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ICHD_PCM2IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ICHD_SPBAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ICHD_LAST = ICHD_SPBAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) NVD_PCMIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) NVD_PCMOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) NVD_MIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) NVD_SPBAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) NVD_LAST = NVD_SPBAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ALID_PCMIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ALID_PCMOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ALID_MIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ALID_AC97SPDIFOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ALID_SPDIFIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ALID_SPDIFOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ALID_LAST = ALID_SPDIFOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define get_ichdev(substream) (substream->runtime->private_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct ichdev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int ichd; /* ich device number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned long reg_offset; /* offset to bmaddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) __le32 *bdbar; /* CPU address (32bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned int bdbar_addr; /* PCI bus address (32bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int physbuf; /* physical address (32bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int fragsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned int fragsize1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int position;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int pos_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int last_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int lvi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int lvi_frag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int civ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int ack_reload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned int ack_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned int roff_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned int roff_picb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned int int_sta_mask; /* interrupt status mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int ali_slot; /* ALI DMA slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct ac97_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int pcm_open_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int prepared:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int suspended: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct intel8x0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned int device_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) void __iomem *bmaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int pcm_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct snd_pcm *pcm[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct ichdev ichd[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned multi4: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) multi6: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) multi8 :1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dra: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) smp20bit: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned in_ac97_init: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) in_sdin_init: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned in_measurement: 1; /* during ac97 clock measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned fix_nocache: 1; /* workaround for 440MX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned buggy_irq: 1; /* workaround for buggy mobos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned inside_vm: 1; /* enable VM optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int sdm_saved; /* SDM reg value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct snd_ac97_bus *ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct snd_ac97 *ac97[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned int ac97_sdin[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int max_codecs, ncodecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) const unsigned int *codec_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned int codec_isr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned int codec_ready_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 bdbars_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct snd_dma_buffer bdbars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 int_sta_reg; /* interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 int_sta_mask; /* interrupt status mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const struct pci_device_id snd_intel8x0_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * Lowlevel I/O - busmaster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return ioread8(chip->bmaddr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static inline u16 igetword(struct intel8x0 *chip, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return ioread16(chip->bmaddr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return ioread32(chip->bmaddr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) iowrite8(val, chip->bmaddr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) iowrite16(val, chip->bmaddr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) iowrite32(val, chip->bmaddr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * Lowlevel I/O - AC'97 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return ioread16(chip->addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) iowrite16(val, chip->addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * Basic I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * access to AC97 codec via normal i/o (for ICH and SIS7012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (codec > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (chip->in_sdin_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* we don't know the ready bit assignment at the moment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* so we check any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) codec = chip->codec_isr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) codec = chip->codec_bit[chip->ac97_sdin[codec]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* codec ready ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (chip->buggy_semaphore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0; /* just ignore ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Anyone holding a semaphore for 1 msec should be shot... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) time = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) } while (time--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* access to some forbidden (non existent) ac97 registers will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * reset the semaphore. So even if you don't get the semaphore, still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * continue the access. We don't need the semaphore anyway. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) iagetword(chip, 0); /* clear semaphore flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* I don't care about the semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned short reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct intel8x0 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (! chip->in_ac97_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) "codec_write %d: semaphore is not ready for register 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ac97->num, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) iaputword(chip, reg + ac97->num * 0x80, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct intel8x0 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned short res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (! chip->in_ac97_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) "codec_read %d: semaphore is not ready for register 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ac97->num, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) res = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) res = iagetword(chip, reg + ac97->num * 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* reset RCS and preserve other R/WC bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) iputdword(chip, ICHREG(GLOB_STA), tmp &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ~(chip->codec_ready_bits | ICH_GSCI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (! chip->in_ac97_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) "codec_read %d: read timeout for register 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ac97->num, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) res = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned int codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) iagetword(chip, codec * 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* reset RCS and preserve other R/WC bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) iputdword(chip, ICHREG(GLOB_STA), tmp &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ~(chip->codec_ready_bits | ICH_GSCI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * access to AC97 for Ali5455
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) for (count = 0; count < 0x7f; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int val = igetbyte(chip, ICHREG(ALI_CSPSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (val & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (! chip->in_ac97_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int time = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (chip->buggy_semaphore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return 0; /* just ignore ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (! time && ! chip->in_ac97_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct intel8x0 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned short data = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (snd_intel8x0_ali_codec_semaphore(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) goto __err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) reg |= ALI_CPR_ADDR_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (ac97->num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) reg |= ALI_CPR_ADDR_SECONDARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) goto __err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) data = igetword(chip, ICHREG(ALI_SPR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) __err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct intel8x0 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (snd_intel8x0_ali_codec_semaphore(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) iputword(chip, ICHREG(ALI_CPR), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (ac97->num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) reg |= ALI_CPR_ADDR_SECONDARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * DMA I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) __le32 *bdbar = ichdev->bdbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) unsigned long port = ichdev->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (ichdev->size == ichdev->fragsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ichdev->ack_reload = ichdev->ack = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ichdev->fragsize1 = ichdev->fragsize >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ichdev->fragsize1 >> ichdev->pos_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ichdev->fragsize1 >> ichdev->pos_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ichdev->frags = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ichdev->ack_reload = ichdev->ack = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ichdev->fragsize1 = ichdev->fragsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) (((idx >> 1) * ichdev->fragsize) %
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ichdev->size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ichdev->fragsize >> ichdev->pos_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ichdev->frags = ichdev->size / ichdev->fragsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ichdev->civ = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ichdev->position = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ichdev->fragsize1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * Interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) unsigned long port = ichdev->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int status, civ, i, step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int ack = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (!(ichdev->prepared || chip->in_measurement) || ichdev->suspended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) status = igetbyte(chip, port + ichdev->roff_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (!(status & ICH_BCIS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) step = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) } else if (civ == ichdev->civ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) // snd_printd("civ same %d\n", civ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) step = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ichdev->civ++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ichdev->civ &= ICH_REG_LVI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) step = civ - ichdev->civ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (step < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) step += ICH_REG_LVI_MASK + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) // if (step != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ichdev->civ = civ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ichdev->position += step * ichdev->fragsize1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (! chip->in_measurement)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ichdev->position %= ichdev->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ichdev->lvi += step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ichdev->lvi &= ICH_REG_LVI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) for (i = 0; i < step; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ichdev->lvi_frag++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ichdev->lvi_frag %= ichdev->frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) inl(port + 4), inb(port + ICH_REG_OFF_CR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (--ichdev->ack == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ichdev->ack = ichdev->ack_reload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ack = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (ack && ichdev->substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) snd_pcm_period_elapsed(ichdev->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) iputbyte(chip, port + ichdev->roff_sr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct intel8x0 *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct ichdev *ichdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) status = igetdword(chip, chip->int_sta_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (status == 0xffffffff) /* we are not yet resumed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if ((status & chip->int_sta_mask) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) iputdword(chip, chip->int_sta_reg, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (! chip->buggy_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return IRQ_RETVAL(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) for (i = 0; i < chip->bdbars_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ichdev = &chip->ichd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (status & ichdev->int_sta_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) snd_intel8x0_update(chip, ichdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* ack them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * PCM part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct ichdev *ichdev = get_ichdev(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) unsigned char val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) unsigned long port = ichdev->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ichdev->suspended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) val = ICH_IOCE | ICH_STARTBM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ichdev->last_pos = ichdev->position;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ichdev->suspended = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) val = ICH_IOCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) iputbyte(chip, port + ICH_REG_OFF_CR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (cmd == SNDRV_PCM_TRIGGER_STOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* wait until DMA stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* reset whole DMA things */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct ichdev *ichdev = get_ichdev(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) unsigned long port = ichdev->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static const int fiforeg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) unsigned int val, fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) val = igetdword(chip, ICHREG(ALI_DMACR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ichdev->suspended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* clear FIFO for synchronization of channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) fifo &= ~(0xff << (ichdev->ali_slot % 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) fifo |= 0x83 << (ichdev->ali_slot % 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* start DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ichdev->suspended = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) iputbyte(chip, port + ICH_REG_OFF_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) while (igetbyte(chip, port + ICH_REG_OFF_CR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* reset whole DMA things */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) iputbyte(chip, port + ICH_REG_OFF_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) iputdword(chip, ICHREG(ALI_INTERRUPTSR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct ichdev *ichdev = get_ichdev(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) int dbl = params_rate(hw_params) > 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (ichdev->pcm_open_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) snd_ac97_pcm_close(ichdev->pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ichdev->pcm_open_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ichdev->prepared = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) params_channels(hw_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ichdev->pcm->r[dbl].slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (err >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ichdev->pcm_open_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* Force SPDIF setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) params_rate(hw_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct ichdev *ichdev = get_ichdev(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (ichdev->pcm_open_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) snd_ac97_pcm_close(ichdev->pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ichdev->pcm_open_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ichdev->prepared = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct snd_pcm_runtime *runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) unsigned int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) int dbl = runtime->rate > 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) switch (chip->device_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) case DEVICE_ALI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) cnt = igetdword(chip, ICHREG(ALI_SCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) cnt &= ~ICH_ALI_SC_PCM_246_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (runtime->channels == 4 || dbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) cnt |= ICH_ALI_SC_PCM_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) else if (runtime->channels == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) cnt |= ICH_ALI_SC_PCM_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) iputdword(chip, ICHREG(ALI_SCR), cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) case DEVICE_SIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) cnt = igetdword(chip, ICHREG(GLOB_CNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) cnt &= ~ICH_SIS_PCM_246_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (runtime->channels == 4 || dbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) cnt |= ICH_SIS_PCM_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) else if (runtime->channels == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) cnt |= ICH_SIS_PCM_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) iputdword(chip, ICHREG(GLOB_CNT), cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) cnt = igetdword(chip, ICHREG(GLOB_CNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (runtime->channels == 4 || dbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) cnt |= ICH_PCM_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) else if (runtime->channels == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) cnt |= ICH_PCM_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) else if (runtime->channels == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) cnt |= ICH_PCM_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (chip->device_type == DEVICE_NFORCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* reset to 2ch once to keep the 6 channel data in alignment,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * to start from Front Left always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (cnt & ICH_PCM_246_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) msleep(50); /* grrr... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) } else if (chip->device_type == DEVICE_INTEL_ICH4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (runtime->sample_bits > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) cnt |= ICH_PCM_20BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) iputdword(chip, ICHREG(GLOB_CNT), cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct ichdev *ichdev = get_ichdev(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ichdev->physbuf = runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ichdev->size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (ichdev->ichd == ICHD_PCMOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) snd_intel8x0_setup_pcm_out(chip, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (chip->device_type == DEVICE_INTEL_ICH4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) snd_intel8x0_setup_periods(chip, ichdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ichdev->prepared = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct ichdev *ichdev = get_ichdev(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) size_t ptr1, ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) int civ, timeout = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) unsigned int position;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) position = ichdev->position;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (ptr1 == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* IO read operation is very expensive inside virtual machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * as it is emulated. The probability that subsequent PICB read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * will return different result is high enough to loop till
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * timeout here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * Same CIV is strict enough condition to be sure that PICB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * is valid inside VM on emulated card. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (chip->inside_vm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) } while (timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ptr = ichdev->last_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (ptr1 != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ptr1 <<= ichdev->pos_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ptr = ichdev->fragsize1 - ptr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ptr += position;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (ptr < ichdev->last_pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) unsigned int pos_base, last_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) pos_base = position / ichdev->fragsize1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) last_base = ichdev->last_pos / ichdev->fragsize1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* another sanity check; ptr1 can go back to full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * before the base position is updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (pos_base == last_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) ptr = ichdev->last_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ichdev->last_pos = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (ptr >= ichdev->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static const struct snd_pcm_hardware snd_intel8x0_stream =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) SNDRV_PCM_INFO_RESUME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .rate_min = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .buffer_bytes_max = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .period_bytes_min = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .period_bytes_max = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static const unsigned int channels4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) 2, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .count = ARRAY_SIZE(channels4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .list = channels4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static const unsigned int channels6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) 2, 4, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .count = ARRAY_SIZE(channels6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .list = channels6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static const unsigned int channels8[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) 2, 4, 6, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .count = ARRAY_SIZE(channels8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .list = channels8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ichdev->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) runtime->hw = snd_intel8x0_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) runtime->hw.rates = ichdev->pcm->rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) snd_pcm_limit_hw_rates(runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (chip->device_type == DEVICE_SIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) runtime->hw.buffer_bytes_max = 64*1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) runtime->hw.period_bytes_max = 64*1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) runtime->private_data = ichdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (chip->multi8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) runtime->hw.channels_max = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) snd_pcm_hw_constraint_list(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) SNDRV_PCM_HW_PARAM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) &hw_constraints_channels8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) } else if (chip->multi6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) runtime->hw.channels_max = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) &hw_constraints_channels6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) } else if (chip->multi4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) runtime->hw.channels_max = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) &hw_constraints_channels4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (chip->dra) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) snd_ac97_pcm_double_rate_rules(runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (chip->smp20bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) chip->ichd[ICHD_PCMOUT].substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) chip->ichd[ICHD_PCMIN].substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) chip->ichd[ICHD_MIC].substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) chip->ichd[ICHD_MIC2].substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) chip->ichd[ICHD_PCM2IN].substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) chip->ichd[idx].substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) val = igetdword(chip, ICHREG(ALI_INTERFACECR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) val |= ICH_ALI_IF_AC97SP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) iputdword(chip, ICHREG(ALI_INTERFACECR), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* also needs to set ALI_SC_CODEC_SPDF correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) val = igetdword(chip, ICHREG(ALI_INTERFACECR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) val &= ~ICH_ALI_IF_AC97SP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) iputdword(chip, ICHREG(ALI_INTERFACECR), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #if 0 // NYI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) chip->ichd[ALID_SPDIFIN].substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct intel8x0 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) chip->ichd[ALID_SPDIFOUT].substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .open = snd_intel8x0_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .close = snd_intel8x0_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .hw_params = snd_intel8x0_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .hw_free = snd_intel8x0_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .prepare = snd_intel8x0_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .trigger = snd_intel8x0_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .pointer = snd_intel8x0_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .open = snd_intel8x0_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .close = snd_intel8x0_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .hw_params = snd_intel8x0_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .hw_free = snd_intel8x0_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .prepare = snd_intel8x0_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .trigger = snd_intel8x0_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .pointer = snd_intel8x0_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .open = snd_intel8x0_mic_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .close = snd_intel8x0_mic_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .hw_params = snd_intel8x0_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .hw_free = snd_intel8x0_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .prepare = snd_intel8x0_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .trigger = snd_intel8x0_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .pointer = snd_intel8x0_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .open = snd_intel8x0_mic2_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .close = snd_intel8x0_mic2_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .hw_params = snd_intel8x0_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .hw_free = snd_intel8x0_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .prepare = snd_intel8x0_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .trigger = snd_intel8x0_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .pointer = snd_intel8x0_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .open = snd_intel8x0_capture2_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .close = snd_intel8x0_capture2_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .hw_params = snd_intel8x0_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .hw_free = snd_intel8x0_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .prepare = snd_intel8x0_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .trigger = snd_intel8x0_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .pointer = snd_intel8x0_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .open = snd_intel8x0_spdif_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .close = snd_intel8x0_spdif_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .hw_params = snd_intel8x0_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .hw_free = snd_intel8x0_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .prepare = snd_intel8x0_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .trigger = snd_intel8x0_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .pointer = snd_intel8x0_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .open = snd_intel8x0_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .close = snd_intel8x0_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .hw_params = snd_intel8x0_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .hw_free = snd_intel8x0_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .prepare = snd_intel8x0_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .trigger = snd_intel8x0_ali_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .pointer = snd_intel8x0_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .open = snd_intel8x0_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .close = snd_intel8x0_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .hw_params = snd_intel8x0_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .hw_free = snd_intel8x0_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .prepare = snd_intel8x0_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .trigger = snd_intel8x0_ali_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .pointer = snd_intel8x0_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .open = snd_intel8x0_mic_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .close = snd_intel8x0_mic_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .hw_params = snd_intel8x0_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .hw_free = snd_intel8x0_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .prepare = snd_intel8x0_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .trigger = snd_intel8x0_ali_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .pointer = snd_intel8x0_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .open = snd_intel8x0_ali_ac97spdifout_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .close = snd_intel8x0_ali_ac97spdifout_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .hw_params = snd_intel8x0_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .hw_free = snd_intel8x0_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .prepare = snd_intel8x0_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .trigger = snd_intel8x0_ali_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .pointer = snd_intel8x0_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #if 0 // NYI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .open = snd_intel8x0_ali_spdifin_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .close = snd_intel8x0_ali_spdifin_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .hw_params = snd_intel8x0_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .hw_free = snd_intel8x0_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .prepare = snd_intel8x0_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .trigger = snd_intel8x0_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .pointer = snd_intel8x0_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .open = snd_intel8x0_ali_spdifout_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .close = snd_intel8x0_ali_spdifout_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .hw_params = snd_intel8x0_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .hw_free = snd_intel8x0_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .prepare = snd_intel8x0_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .trigger = snd_intel8x0_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .pointer = snd_intel8x0_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #endif // NYI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) struct ich_pcm_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) char *suffix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) const struct snd_pcm_ops *playback_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) const struct snd_pcm_ops *capture_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) size_t prealloc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) size_t prealloc_max_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) int ac97_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #define intel8x0_dma_type(chip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) ((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_UC : SNDRV_DMA_TYPE_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) const struct ich_pcm_table *rec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (rec->suffix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) sprintf(name, "Intel ICH - %s", rec->suffix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) strcpy(name, "Intel ICH");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) err = snd_pcm_new(chip->card, name, device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) rec->playback_ops ? 1 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) rec->capture_ops ? 1 : 0, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (rec->playback_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (rec->capture_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (rec->suffix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) strcpy(pcm->name, chip->card->shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) chip->pcm[device] = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) snd_pcm_set_managed_buffer_all(pcm, intel8x0_dma_type(chip),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) rec->prealloc_size, rec->prealloc_max_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (rec->playback_ops &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) rec->playback_ops->open == snd_intel8x0_playback_open) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) struct snd_pcm_chmap *chmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) int chs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (chip->multi8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) chs = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) else if (chip->multi6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) chs = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) else if (chip->multi4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) chs = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) snd_pcm_alt_chmaps, chs, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) &chmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static const struct ich_pcm_table intel_pcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .playback_ops = &snd_intel8x0_playback_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .capture_ops = &snd_intel8x0_capture_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .prealloc_size = 64 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .prealloc_max_size = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .suffix = "MIC ADC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .capture_ops = &snd_intel8x0_capture_mic_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .prealloc_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .prealloc_max_size = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .ac97_idx = ICHD_MIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .suffix = "MIC2 ADC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .capture_ops = &snd_intel8x0_capture_mic2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .prealloc_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .prealloc_max_size = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .ac97_idx = ICHD_MIC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .suffix = "ADC2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .capture_ops = &snd_intel8x0_capture2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .prealloc_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .prealloc_max_size = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .ac97_idx = ICHD_PCM2IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .suffix = "IEC958",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .playback_ops = &snd_intel8x0_spdif_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .prealloc_size = 64 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .prealloc_max_size = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .ac97_idx = ICHD_SPBAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) static const struct ich_pcm_table nforce_pcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .playback_ops = &snd_intel8x0_playback_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .capture_ops = &snd_intel8x0_capture_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .prealloc_size = 64 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .prealloc_max_size = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .suffix = "MIC ADC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .capture_ops = &snd_intel8x0_capture_mic_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .prealloc_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .prealloc_max_size = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .ac97_idx = NVD_MIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .suffix = "IEC958",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .playback_ops = &snd_intel8x0_spdif_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .prealloc_size = 64 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .prealloc_max_size = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .ac97_idx = NVD_SPBAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static const struct ich_pcm_table ali_pcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .playback_ops = &snd_intel8x0_ali_playback_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .capture_ops = &snd_intel8x0_ali_capture_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .prealloc_size = 64 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .prealloc_max_size = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .suffix = "MIC ADC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .prealloc_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .prealloc_max_size = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .ac97_idx = ALID_MIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .suffix = "IEC958",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .prealloc_size = 64 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .prealloc_max_size = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .ac97_idx = ALID_AC97SPDIFOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) #if 0 // NYI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .suffix = "HW IEC958",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .playback_ops = &snd_intel8x0_ali_spdifout_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .prealloc_size = 64 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .prealloc_max_size = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static int snd_intel8x0_pcm(struct intel8x0 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) int i, tblsize, device, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) const struct ich_pcm_table *tbl, *rec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) switch (chip->device_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) case DEVICE_INTEL_ICH4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) tbl = intel_pcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) tblsize = ARRAY_SIZE(intel_pcms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (spdif_aclink)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) tblsize--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) case DEVICE_NFORCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) tbl = nforce_pcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) tblsize = ARRAY_SIZE(nforce_pcms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (spdif_aclink)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) tblsize--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) case DEVICE_ALI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) tbl = ali_pcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) tblsize = ARRAY_SIZE(ali_pcms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) tbl = intel_pcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) tblsize = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) device = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) for (i = 0; i < tblsize; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) rec = tbl + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if (i > 0 && rec->ac97_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /* activate PCM only when associated AC'97 codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (! chip->ichd[rec->ac97_idx].pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) err = snd_intel8x0_pcm1(chip, device, rec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) device++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) chip->pcm_devs = device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * Mixer part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct intel8x0 *chip = bus->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) chip->ac97_bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) struct intel8x0 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) chip->ac97[ac97->num] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static const struct ac97_pcm ac97_pcm_defs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) /* front PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .exclusive = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .r = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .slots = (1 << AC97_SLOT_PCM_LEFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) (1 << AC97_SLOT_PCM_RIGHT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) (1 << AC97_SLOT_PCM_CENTER) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) (1 << AC97_SLOT_PCM_SLEFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) (1 << AC97_SLOT_PCM_SRIGHT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) (1 << AC97_SLOT_LFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .slots = (1 << AC97_SLOT_PCM_LEFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) (1 << AC97_SLOT_PCM_RIGHT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) (1 << AC97_SLOT_PCM_LEFT_0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) (1 << AC97_SLOT_PCM_RIGHT_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) /* PCM IN #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .stream = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .exclusive = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .r = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .slots = (1 << AC97_SLOT_PCM_LEFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) (1 << AC97_SLOT_PCM_RIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) /* MIC IN #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .stream = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .exclusive = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .r = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .slots = (1 << AC97_SLOT_MIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) /* S/PDIF PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .exclusive = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .spdif = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .r = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) (1 << AC97_SLOT_SPDIF_RIGHT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* PCM IN #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .stream = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .exclusive = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .r = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .slots = (1 << AC97_SLOT_PCM_LEFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) (1 << AC97_SLOT_PCM_RIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) /* MIC IN #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .stream = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .exclusive = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .r = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .slots = (1 << AC97_SLOT_MIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static const struct ac97_quirk ac97_quirks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .subvendor = 0x0e11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .subdevice = 0x000e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .name = "Compaq Deskpro EN", /* AD1885 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .subvendor = 0x0e11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .subdevice = 0x008a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .name = "Compaq Evo W4000", /* AD1885 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .subvendor = 0x0e11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .subdevice = 0x00b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .name = "Compaq Evo D510C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .subvendor = 0x0e11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .subdevice = 0x0860,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .name = "HP/Compaq nx7010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .type = AC97_TUNE_MUTE_LED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .subvendor = 0x1014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .subdevice = 0x0534,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .name = "ThinkPad X31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .type = AC97_TUNE_INV_EAPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .subvendor = 0x1014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .subdevice = 0x1f00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .name = "MS-9128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .type = AC97_TUNE_ALC_JACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .subvendor = 0x1014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .subdevice = 0x0267,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .name = "IBM NetVista A30p", /* AD1981B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .subvendor = 0x1025,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .subdevice = 0x0082,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .name = "Acer Travelmate 2310",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .subvendor = 0x1025,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .subdevice = 0x0083,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .name = "Acer Aspire 3003LCi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .subdevice = 0x00d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .name = "Dell Precision 530", /* AD1885 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .subdevice = 0x010d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .name = "Dell", /* which model? AD1885 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .subdevice = 0x0126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .name = "Dell Optiplex GX260", /* AD1981A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .subdevice = 0x012c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .name = "Dell Precision 650", /* AD1981A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .subdevice = 0x012d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .name = "Dell Precision 450", /* AD1981B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .subdevice = 0x0147,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .name = "Dell", /* which model? AD1981B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .subdevice = 0x0151,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .name = "Dell Optiplex GX270", /* AD1981B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .subdevice = 0x014e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .name = "Dell D800", /* STAC9750/51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .subdevice = 0x0163,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .name = "Dell Unknown", /* STAC9750/51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .subdevice = 0x016a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .name = "Dell Inspiron 8600", /* STAC9750/51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .subdevice = 0x0182,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .name = "Dell Latitude D610", /* STAC9750/51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .subdevice = 0x0186,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .name = "Dell Latitude D810", /* cf. Malone #41015 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .type = AC97_TUNE_HP_MUTE_LED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .subdevice = 0x0188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .name = "Dell Inspiron 6000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .subdevice = 0x0189,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .name = "Dell Inspiron 9300",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .type = AC97_TUNE_HP_MUTE_LED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .subvendor = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .subdevice = 0x0191,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .name = "Dell Inspiron 8600",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .subvendor = 0x103c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .subdevice = 0x006d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .name = "HP zv5000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .type = AC97_TUNE_MUTE_LED /*AD1981B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) { /* FIXME: which codec? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .subvendor = 0x103c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .subdevice = 0x00c3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .name = "HP xw6000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .subvendor = 0x103c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .subdevice = 0x088c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .name = "HP nc8000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .type = AC97_TUNE_HP_MUTE_LED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .subvendor = 0x103c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .subdevice = 0x0890,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .name = "HP nc6000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .type = AC97_TUNE_MUTE_LED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .subvendor = 0x103c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .subdevice = 0x129d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .name = "HP xw8000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .subvendor = 0x103c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .subdevice = 0x0938,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .name = "HP nc4200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .type = AC97_TUNE_HP_MUTE_LED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .subvendor = 0x103c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .subdevice = 0x099c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .name = "HP nx6110/nc6120",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .type = AC97_TUNE_HP_MUTE_LED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .subvendor = 0x103c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .subdevice = 0x0944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .name = "HP nc6220",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .type = AC97_TUNE_HP_MUTE_LED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .subvendor = 0x103c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .subdevice = 0x0934,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .name = "HP nc8220",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .type = AC97_TUNE_HP_MUTE_LED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .subvendor = 0x103c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .subdevice = 0x12f1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .name = "HP xw8200", /* AD1981B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .subvendor = 0x103c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .subdevice = 0x12f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .name = "HP xw6200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .subvendor = 0x103c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .subdevice = 0x3008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .name = "HP xw4200", /* AD1981B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .subvendor = 0x104d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .subdevice = 0x8144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .name = "Sony",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .type = AC97_TUNE_INV_EAPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .subvendor = 0x104d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .subdevice = 0x8197,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .name = "Sony S1XP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .type = AC97_TUNE_INV_EAPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .subvendor = 0x104d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .subdevice = 0x81c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .name = "Sony VAIO VGN-T350P", /*AD1981B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .type = AC97_TUNE_INV_EAPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .subvendor = 0x104d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .subdevice = 0x81c5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .type = AC97_TUNE_INV_EAPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .subvendor = 0x1043,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .subdevice = 0x80f3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .name = "ASUS ICH5/AD1985",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .type = AC97_TUNE_AD_SHARING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .subvendor = 0x10cf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .subdevice = 0x11c3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .name = "Fujitsu-Siemens E4010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .subvendor = 0x10cf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .subdevice = 0x1225,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .name = "Fujitsu-Siemens T3010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .subvendor = 0x10cf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .subdevice = 0x1253,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .name = "Fujitsu S6210", /* STAC9750/51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .subvendor = 0x10cf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .subdevice = 0x127d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .name = "Fujitsu Lifebook P7010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .subvendor = 0x10cf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .subdevice = 0x127e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .name = "Fujitsu Lifebook C1211D",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .subvendor = 0x10cf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .subdevice = 0x12ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .name = "Fujitsu-Siemens 4010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .subvendor = 0x10cf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .subdevice = 0x12f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .name = "Fujitsu-Siemens Celsius H320",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .type = AC97_TUNE_SWAP_HP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .subvendor = 0x10f1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .subdevice = 0x2665,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .name = "Fujitsu-Siemens Celsius", /* AD1981? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .subvendor = 0x10f1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .subdevice = 0x2885,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .name = "AMD64 Mobo", /* ALC650 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .subvendor = 0x10f1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .subdevice = 0x2895,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .name = "Tyan Thunder K8WE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .subvendor = 0x10f7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .subdevice = 0x834c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .name = "Panasonic CF-R4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .type = AC97_TUNE_HP_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .subvendor = 0x110a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .subdevice = 0x0056,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .name = "Fujitsu-Siemens Scenic", /* AD1981? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .subvendor = 0x11d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .subdevice = 0x5375,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .name = "ADI AD1985 (discrete)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .subvendor = 0x1462,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .subdevice = 0x5470,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .name = "MSI P4 ATX 645 Ultra",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .subvendor = 0x161f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .subdevice = 0x202f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .name = "Gateway M520",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .type = AC97_TUNE_INV_EAPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .subvendor = 0x161f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .subdevice = 0x203a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .name = "Gateway 4525GZ", /* AD1981B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .type = AC97_TUNE_INV_EAPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .subvendor = 0x1734,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .subdevice = 0x0088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .name = "Fujitsu-Siemens D1522", /* AD1981 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .subvendor = 0x8086,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .subdevice = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .mask = 0xfff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .name = "Intel ICH5/AD1985",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .type = AC97_TUNE_AD_SHARING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .subvendor = 0x8086,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .subdevice = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .mask = 0xfff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .name = "Intel ICH5/AD1985",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .type = AC97_TUNE_AD_SHARING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .subvendor = 0x8086,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .subdevice = 0x4856,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .name = "Intel D845WN (82801BA)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .type = AC97_TUNE_SWAP_HP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .subvendor = 0x8086,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .subdevice = 0x4d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .name = "Intel D850EMV2", /* AD1885 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .subvendor = 0x8086,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .subdevice = 0x4d56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .name = "Intel ICH/AD1885",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .subvendor = 0x8086,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .subdevice = 0x6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .mask = 0xfff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .name = "Intel ICH5/AD1985",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .type = AC97_TUNE_AD_SHARING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .subvendor = 0x8086,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .subdevice = 0xe000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .mask = 0xfff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .name = "Intel ICH5/AD1985",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .type = AC97_TUNE_AD_SHARING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) #if 0 /* FIXME: this seems wrong on most boards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .subvendor = 0x8086,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .subdevice = 0xa000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .mask = 0xfff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .name = "Intel ICH5/AD1985",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) { } /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) const char *quirk_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) struct snd_ac97_bus *pbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) struct snd_ac97_template ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) unsigned int i, codecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) unsigned int glob_sta = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) const struct snd_ac97_bus_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) static const struct snd_ac97_bus_ops standard_bus_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .write = snd_intel8x0_codec_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .read = snd_intel8x0_codec_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) static const struct snd_ac97_bus_ops ali_bus_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .write = snd_intel8x0_ali_codec_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .read = snd_intel8x0_ali_codec_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) if (!spdif_aclink) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) switch (chip->device_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) case DEVICE_NFORCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) chip->spdif_idx = NVD_SPBAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) case DEVICE_ALI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) chip->spdif_idx = ALID_AC97SPDIFOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) case DEVICE_INTEL_ICH4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) chip->spdif_idx = ICHD_SPBAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) chip->in_ac97_init = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) ac97.private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) ac97.private_free = snd_intel8x0_mixer_free_ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) if (chip->xbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) if (chip->device_type != DEVICE_ALI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) glob_sta = igetdword(chip, ICHREG(GLOB_STA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) ops = &standard_bus_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) chip->in_sdin_init = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) codecs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) for (i = 0; i < chip->max_codecs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) if (! (glob_sta & chip->codec_bit[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) if (chip->device_type == DEVICE_INTEL_ICH4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) snd_intel8x0_codec_read_test(chip, codecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) chip->ac97_sdin[codecs] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) chip->ac97_sdin[codecs] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) chip->ac97_sdin[codecs] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) codecs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) chip->in_sdin_init = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) if (! codecs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) codecs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) ops = &ali_bus_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) codecs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) /* detect the secondary codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) for (i = 0; i < 100; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) if (reg & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) codecs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) goto __err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) if (ac97_clock >= 8000 && ac97_clock <= 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) pbus->clock = ac97_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) /* FIXME: my test board doesn't work well with VRA... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) if (chip->device_type == DEVICE_ALI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) pbus->no_vra = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) pbus->dra = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) chip->ac97_bus = pbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) chip->ncodecs = codecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) ac97.pci = chip->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) for (i = 0; i < codecs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) ac97.num = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (err != -EACCES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) "Unable to initialize codec #%d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) goto __err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) /* tune up the primary codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) /* enable separate SDINs for ICH4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) if (chip->device_type == DEVICE_INTEL_ICH4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) pbus->isdin = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) /* find the available PCM streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) i = ARRAY_SIZE(ac97_pcm_defs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) if (chip->device_type != DEVICE_INTEL_ICH4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) i -= 2; /* do not allocate PCM2IN and MIC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) if (chip->spdif_idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) i--; /* do not allocate S/PDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) goto __err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) if (chip->spdif_idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) if (chip->device_type == DEVICE_INTEL_ICH4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) /* enable separate SDINs for ICH4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) if (chip->device_type == DEVICE_INTEL_ICH4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) u8 tmp = igetbyte(chip, ICHREG(SDM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) if (pcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) tmp |= ICH_SE; /* steer enable for multiple SDINs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) for (i = 1; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) if (pcm->r[0].codec[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) tmp &= ~ICH_SE; /* steer disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) iputbyte(chip, ICHREG(SDM), tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) chip->multi4 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) chip->multi6 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) if (chip->ac97[0]->flags & AC97_HAS_8CH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) chip->multi8 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if (pbus->pcms[0].r[1].rslots[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) chip->dra = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) if (chip->device_type == DEVICE_INTEL_ICH4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) chip->smp20bit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) /* 48kHz only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) /* use slot 10/11 for SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) val |= ICH_PCM_SPDIF_1011;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) iputdword(chip, ICHREG(GLOB_CNT), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) chip->in_ac97_init = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) __err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) /* clear the cold-reset bit for the next chance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) if (chip->device_type != DEVICE_ALI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) iputdword(chip, ICHREG(GLOB_CNT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) static void do_ali_reset(struct intel8x0 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) iputdword(chip, ICHREG(ALI_INTERFACECR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) ICH_ALI_IF_PI|ICH_ALI_IF_PO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) #ifdef CONFIG_SND_AC97_POWER_SAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) static const struct snd_pci_quirk ich_chip_reset_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) { } /* end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) unsigned int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) /* ACLink on, 2 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) cnt = igetdword(chip, ICHREG(GLOB_CNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) /* do cold reset - the full ac97 powerdown may leave the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) * in a warm state but actually it cannot communicate with the codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) cnt = igetdword(chip, ICHREG(GLOB_CNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) #define snd_intel8x0_ich_chip_cold_reset(chip) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) unsigned long end_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) unsigned int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) /* ACLink on, 2 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) cnt = igetdword(chip, ICHREG(GLOB_CNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) /* finish cold or do warm reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) iputdword(chip, ICHREG(GLOB_CNT), cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) end_time = (jiffies + (HZ / 4)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) } while (time_after_eq(end_time, jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) igetdword(chip, ICHREG(GLOB_CNT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) unsigned long end_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) unsigned int status, nstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) unsigned int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) /* put logic to right state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) /* first clear status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) if (chip->device_type == DEVICE_NFORCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) status |= ICH_NVSPINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) cnt = igetdword(chip, ICHREG(GLOB_STA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) iputdword(chip, ICHREG(GLOB_STA), cnt & status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) if (snd_intel8x0_ich_chip_can_cold_reset(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) err = snd_intel8x0_ich_chip_cold_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) err = snd_intel8x0_ich_chip_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) if (probing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) /* wait for any codec ready status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) * Once it becomes ready it should remain ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) * as long as we do not disable the ac97 link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) end_time = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) status = igetdword(chip, ICHREG(GLOB_STA)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) chip->codec_isr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) } while (time_after_eq(end_time, jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) if (! status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) /* no codec is found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) "codec_ready: codec is not ready [0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) igetdword(chip, ICHREG(GLOB_STA)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) /* wait for other codecs ready status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) end_time = jiffies + HZ / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) while (status != chip->codec_isr_bits &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) time_after_eq(end_time, jiffies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) status |= igetdword(chip, ICHREG(GLOB_STA)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) chip->codec_isr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) /* resume phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) for (i = 0; i < chip->ncodecs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) if (chip->ac97[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) status |= chip->codec_bit[chip->ac97_sdin[i]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) /* wait until all the probed codecs are ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) end_time = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) chip->codec_isr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) if (status == nstatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) } while (time_after_eq(end_time, jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) if (chip->device_type == DEVICE_SIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) /* unmute the output on SIS7012 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) /* enable SPDIF interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) pci_read_config_dword(chip->pci, 0x4c, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) val |= 0x1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) pci_write_config_dword(chip->pci, 0x4c, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) reg = igetdword(chip, ICHREG(ALI_SCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) if ((reg & 2) == 0) /* Cold required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) reg |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) reg |= 1; /* Warm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) reg &= ~0x80000000; /* ACLink on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) iputdword(chip, ICHREG(ALI_SCR), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) for (i = 0; i < HZ / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) goto __ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) dev_err(chip->card->dev, "AC'97 reset failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) if (probing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) __ok:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) for (i = 0; i < HZ / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) reg = igetdword(chip, ICHREG(ALI_RTSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) if (reg & 0x80) /* primary codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) do_ali_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) unsigned int i, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) if (chip->device_type != DEVICE_ALI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) iagetword(chip, 0); /* clear semaphore flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) for (i = 0; i < chip->bdbars_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) /* reset channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) for (i = 0; i < chip->bdbars_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) for (i = 0; i < chip->bdbars_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) timeout = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) while (--timeout != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) dev_err(chip->card->dev, "reset of registers failed?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) /* initialize Buffer Descriptor Lists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) for (i = 0; i < chip->bdbars_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) chip->ichd[i].bdbar_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) static int snd_intel8x0_free(struct intel8x0 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) if (chip->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) goto __hw_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) for (i = 0; i < chip->bdbars_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) /* reset channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) for (i = 0; i < chip->bdbars_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) /* stop the spdif interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) pci_read_config_dword(chip->pci, 0x4c, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) val &= ~0x1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) pci_write_config_dword(chip->pci, 0x4c, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) /* --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) __hw_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) if (chip->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) if (chip->bdbars.area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) snd_dma_free_pages(&chip->bdbars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) if (chip->addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) pci_iounmap(chip->pci, chip->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) if (chip->bmaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) pci_iounmap(chip->pci, chip->bmaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) pci_release_regions(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) pci_disable_device(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) * power management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) static int intel8x0_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) struct intel8x0 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) for (i = 0; i < chip->ncodecs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) snd_ac97_suspend(chip->ac97[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) if (chip->device_type == DEVICE_INTEL_ICH4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) if (chip->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) card->sync_irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) static int intel8x0_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) struct pci_dev *pci = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) struct intel8x0 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) snd_intel8x0_chip_init(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) if (request_irq(pci->irq, snd_intel8x0_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) IRQF_SHARED, KBUILD_MODNAME, chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) dev_err(dev, "unable to grab IRQ %d, disabling device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) snd_card_disconnect(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) chip->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) /* re-initialize mixer stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) /* enable separate SDINs for ICH4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) /* use slot 10/11 for SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) iputdword(chip, ICHREG(GLOB_CNT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) ICH_PCM_SPDIF_1011);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) for (i = 0; i < chip->ncodecs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) snd_ac97_resume(chip->ac97[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) /* resume status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) for (i = 0; i < chip->bdbars_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) struct ichdev *ichdev = &chip->ichd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) unsigned long port = ichdev->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) if (! ichdev->substream || ! ichdev->suspended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) if (ichdev->ichd == ICHD_PCMOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) #define INTEL8X0_PM_OPS &intel8x0_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) #define INTEL8X0_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) struct snd_pcm_substream *subs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) struct ichdev *ichdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) unsigned long pos, pos1, t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) int civ, timeout = 1000, attempt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) ktime_t start_time, stop_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) if (chip->ac97_bus->clock != 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) return; /* specified in module option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) __again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) subs = chip->pcm[0]->streams[0].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) dev_warn(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) "no playback buffer allocated - aborting measure ac97 clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) ichdev = &chip->ichd[ICHD_PCMOUT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) ichdev->physbuf = subs->dma_buffer.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) ichdev->substream = NULL; /* don't process interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) /* set rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) chip->ac97_bus->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) snd_intel8x0_setup_periods(chip, ichdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) port = ichdev->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) chip->in_measurement = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) /* trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) if (chip->device_type != DEVICE_ALI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) start_time = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) /* check the position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) if (pos1 == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) } while (timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) if (pos1 == 0) { /* oops, this value is not reliable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) pos = ichdev->fragsize1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) pos -= pos1 << ichdev->pos_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) pos += ichdev->position;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) chip->in_measurement = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) stop_time = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) /* stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) if (chip->device_type == DEVICE_ALI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) iputbyte(chip, port + ICH_REG_OFF_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) while (igetbyte(chip, port + ICH_REG_OFF_CR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) iputbyte(chip, port + ICH_REG_OFF_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) if (pos == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) "measure - unreliable DMA position..\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) __retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) if (attempt < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) msleep(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) attempt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) goto __again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) goto __end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) pos /= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) t = ktime_us_delta(stop_time, start_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) dev_info(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) if (t == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) dev_err(chip->card->dev, "?? calculation error..\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) goto __retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) pos *= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) if (pos < 40000 || pos >= 60000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) /* abnormal value. hw problem? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) goto __retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) } else if (pos > 40500 && pos < 41500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) /* first exception - 41000Hz reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) chip->ac97_bus->clock = 41000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) else if (pos > 43600 && pos < 44600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) /* second exception - 44100HZ reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) chip->ac97_bus->clock = 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) else if (pos < 47500 || pos > 48500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) /* not 48000Hz, tuning the clock.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) __end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) static const struct snd_pci_quirk intel8x0_clock_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) { } /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) static int intel8x0_in_clock_list(struct intel8x0 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) struct pci_dev *pci = chip->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) const struct snd_pci_quirk *wl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) if (!wl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) dev_info(chip->card->dev, "allow list rate for %04x:%04x is %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) pci->subsystem_vendor, pci->subsystem_device, wl->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) chip->ac97_bus->clock = wl->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) struct intel8x0 *chip = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) snd_iprintf(buffer, "Intel8x0\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) if (chip->device_type == DEVICE_ALI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) tmp = igetdword(chip, ICHREG(GLOB_STA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) if (chip->device_type == DEVICE_INTEL_ICH4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) snd_iprintf(buffer, "AC'97 codecs ready :");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) if (tmp & chip->codec_isr_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) static const char *codecs[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) "primary", "secondary", "tertiary"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) for (i = 0; i < chip->max_codecs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) if (tmp & chip->codec_bit[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) snd_iprintf(buffer, " %s", codecs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) snd_iprintf(buffer, " none");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) if (chip->device_type == DEVICE_INTEL_ICH4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) chip->device_type == DEVICE_SIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) chip->ac97_sdin[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) chip->ac97_sdin[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) chip->ac97_sdin[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) static void snd_intel8x0_proc_init(struct intel8x0 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) snd_card_ro_proc_new(chip->card, "intel8x0", chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) snd_intel8x0_proc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) static int snd_intel8x0_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) struct intel8x0 *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) return snd_intel8x0_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) struct ich_reg_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) unsigned int int_sta_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) static const unsigned int ich_codec_bits[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) ICH_PCR, ICH_SCR, ICH_TCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) static const unsigned int sis_codec_bits[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) ICH_PCR, ICH_SCR, ICH_SIS_TCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) static int snd_intel8x0_inside_vm(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) int result = inside_vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) char *msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) /* check module parameter first (override detection) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) if (result >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) msg = result ? "enable (forced) VM" : "disable (forced) VM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) goto fini;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) /* check for known (emulated) devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) /* KVM emulated sound, PCI SSID: 1af4:1100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) msg = "enable KVM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) result = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) } else if (pci->subsystem_vendor == 0x1ab8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) msg = "enable Parallels VM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) result = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) fini:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) if (msg != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) dev_info(&pci->dev, "%s optimization\n", msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) static int snd_intel8x0_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) unsigned long device_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) struct intel8x0 **r_intel8x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) struct intel8x0 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) unsigned int int_sta_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) struct ichdev *ichdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) .dev_free = snd_intel8x0_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) static const unsigned int bdbars[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) 3, /* DEVICE_INTEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) 6, /* DEVICE_INTEL_ICH4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) 3, /* DEVICE_SIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) 6, /* DEVICE_ALI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) 4, /* DEVICE_NFORCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) static const struct ich_reg_info intel_regs[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) { ICH_PIINT, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) { ICH_POINT, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) { ICH_MCINT, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) { ICH_M2INT, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) { ICH_P2INT, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) { ICH_SPINT, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) static const struct ich_reg_info nforce_regs[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) { ICH_PIINT, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) { ICH_POINT, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) { ICH_MCINT, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) { ICH_NVSPINT, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) static const struct ich_reg_info ali_regs[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) { ALI_INT_PCMIN, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) { ALI_INT_PCMOUT, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) { ALI_INT_MICIN, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) { ALI_INT_CODECSPDIFOUT, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) { ALI_INT_SPDIFIN, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) { ALI_INT_SPDIFOUT, 0xb0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) const struct ich_reg_info *tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) *r_intel8x0 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) if ((err = pci_enable_device(pci)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) chip = kzalloc(sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) if (chip == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) spin_lock_init(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) chip->device_type = device_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) /* module parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) chip->buggy_irq = buggy_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) chip->buggy_semaphore = buggy_semaphore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) if (xbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) chip->xbox = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) chip->inside_vm = snd_intel8x0_inside_vm(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) * Intel 82443MX running a 100MHz processor system bus has a hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) * bug, which aborts PCI busmaster for audio transfer. A workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) * is to set the pages as non-cached. For details, see the errata in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) if (pci->vendor == PCI_VENDOR_ID_INTEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) pci->device == PCI_DEVICE_ID_INTEL_440MX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) chip->fix_nocache = 1; /* enable workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) if ((err = pci_request_regions(pci, card->shortname)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) if (device_type == DEVICE_ALI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) /* ALI5455 has no ac97 region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) chip->bmaddr = pci_iomap(pci, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) goto port_inited;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) chip->addr = pci_iomap(pci, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) chip->addr = pci_iomap(pci, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) if (!chip->addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) dev_err(card->dev, "AC'97 space ioremap problem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) snd_intel8x0_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) chip->bmaddr = pci_iomap(pci, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) chip->bmaddr = pci_iomap(pci, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) port_inited:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) if (!chip->bmaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) dev_err(card->dev, "Controller space ioremap problem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) snd_intel8x0_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) chip->bdbars_count = bdbars[device_type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) /* initialize offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) switch (device_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) case DEVICE_NFORCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) tbl = nforce_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) case DEVICE_ALI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) tbl = ali_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) tbl = intel_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) for (i = 0; i < chip->bdbars_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) ichdev = &chip->ichd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) ichdev->ichd = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) ichdev->reg_offset = tbl[i].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) ichdev->int_sta_mask = tbl[i].int_sta_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) if (device_type == DEVICE_SIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) /* SiS 7012 swaps the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) ichdev->roff_sr = ICH_REG_OFF_PICB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) ichdev->roff_picb = ICH_REG_OFF_SR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) ichdev->roff_sr = ICH_REG_OFF_SR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) ichdev->roff_picb = ICH_REG_OFF_PICB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) if (device_type == DEVICE_ALI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) /* SIS7012 handles the pcm data in bytes, others are in samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) /* allocate buffer descriptor lists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) /* the start of each lists must be aligned to 8 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) if (snd_dma_alloc_pages(intel8x0_dma_type(chip), &pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) &chip->bdbars) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) snd_intel8x0_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) dev_err(card->dev, "cannot allocate buffer descriptors\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) /* tables must be aligned to 8 bytes here, but the kernel pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) are much bigger, so we don't care (on i386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) int_sta_masks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) for (i = 0; i < chip->bdbars_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) ichdev = &chip->ichd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) ichdev->bdbar = ((__le32 *)chip->bdbars.area) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) (i * ICH_MAX_FRAGS * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) ichdev->bdbar_addr = chip->bdbars.addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) int_sta_masks |= ichdev->int_sta_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) chip->int_sta_reg = device_type == DEVICE_ALI ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) chip->int_sta_mask = int_sta_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) switch(chip->device_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) case DEVICE_INTEL_ICH4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) /* ICH4 can have three codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) chip->max_codecs = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) chip->codec_bit = ich_codec_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) case DEVICE_SIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) /* recent SIS7012 can have three codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) chip->max_codecs = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) chip->codec_bit = sis_codec_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) /* others up to two codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) chip->max_codecs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) chip->codec_bit = ich_codec_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) chip->codec_ready_bits = ICH_PRI | ICH_SRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) for (i = 0; i < chip->max_codecs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) chip->codec_isr_bits |= chip->codec_bit[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) snd_intel8x0_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) /* request irq after initializaing int_sta_mask, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) if (request_irq(pci->irq, snd_intel8x0_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) IRQF_SHARED, KBUILD_MODNAME, chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) snd_intel8x0_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) chip->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) snd_intel8x0_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) *r_intel8x0 = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) static struct shortname_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) const char *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) } shortnames[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) { 0x003a, "NVidia MCP04" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) { 0x746d, "AMD AMD8111" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) { 0x7445, "AMD AMD768" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) { 0x5455, "ALi M5455" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) { 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) static const struct snd_pci_quirk spdif_aclink_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) { } /* end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) /* look up allow/deny list for SPDIF over ac-link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) static int check_default_spdif_aclink(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) const struct snd_pci_quirk *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) if (w) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) if (w->value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) dev_dbg(&pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) "Using SPDIF over AC-Link for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) snd_pci_quirk_name(w));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) dev_dbg(&pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) "Using integrated SPDIF DMA for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) snd_pci_quirk_name(w));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) return w->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) static int snd_intel8x0_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) struct intel8x0 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) struct shortname_table *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) if (spdif_aclink < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) spdif_aclink = check_default_spdif_aclink(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) strcpy(card->driver, "ICH");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) if (!spdif_aclink) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) switch (pci_id->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) case DEVICE_NFORCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) strcpy(card->driver, "NFORCE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) case DEVICE_INTEL_ICH4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) strcpy(card->driver, "ICH4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) strcpy(card->shortname, "Intel ICH");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) for (name = shortnames; name->id; name++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) if (pci->device == name->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) strcpy(card->shortname, name->s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) if (buggy_irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) /* some Nforce[2] and ICH boards have problems with IRQ handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) * Needs to return IRQ_HANDLED for unknown irqs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) if (pci_id->driver_data == DEVICE_NFORCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) buggy_irq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) buggy_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) &chip)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) card->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) if ((err = snd_intel8x0_pcm(chip)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) snd_intel8x0_proc_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) snprintf(card->longname, sizeof(card->longname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) "%s with %s at irq %i", card->shortname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) if (ac97_clock == 0 || ac97_clock == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) if (ac97_clock == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) if (intel8x0_in_clock_list(chip) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) intel8x0_measure_ac97_clock(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) intel8x0_measure_ac97_clock(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) if ((err = snd_card_register(card)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) static void snd_intel8x0_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) static struct pci_driver intel8x0_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) .id_table = snd_intel8x0_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) .probe = snd_intel8x0_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) .remove = snd_intel8x0_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) .pm = INTEL8X0_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) module_pci_driver(intel8x0_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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