Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __SOUND_WM8776_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __SOUND_WM8776_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *   ALSA driver for ICEnsemble VT17xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *   Lowlevel functions for WM8776 codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *	Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define WM8776_REG_HPLVOL	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define WM8776_REG_HPRVOL	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define WM8776_REG_HPMASTER	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define WM8776_HPVOL_MASK		0x17f		/* incl. update bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define WM8776_VOL_HPZCEN		(1 << 7)	/* zero cross detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define WM8776_VOL_UPDATE		(1 << 8)	/* update volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define WM8776_REG_DACLVOL	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define WM8776_REG_DACRVOL	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define WM8776_REG_DACMASTER	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define WM8776_DACVOL_MASK		0x1ff		/* incl. update bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define WM8776_REG_PHASESWAP	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define WM8776_PHASE_INVERTL		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define WM8776_PHASE_INVERTR		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define WM8776_REG_DACCTRL1	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define WM8776_DAC_DZCEN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define WM8776_DAC_ATC			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define WM8776_DAC_IZD			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define WM8776_DAC_TOD			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define WM8776_DAC_PL_MASK		0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define WM8776_DAC_PL_LL		(1 << 4)	/* L chan: L signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define WM8776_DAC_PL_LR		(2 << 4)	/* L chan: R signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define WM8776_DAC_PL_LB		(3 << 4)	/* L chan: both */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define WM8776_DAC_PL_RL		(1 << 6)	/* R chan: L signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define WM8776_DAC_PL_RR		(2 << 6)	/* R chan: R signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define WM8776_DAC_PL_RB		(3 << 6)	/* R chan: both */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define WM8776_REG_DACMUTE	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define WM8776_DACMUTE			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define WM8776_REG_DACCTRL2	0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define WM8776_DAC2_DEEMPH		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define WM8776_DAC2_ZFLAG_DISABLE	(0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define WM8776_DAC2_ZFLAG_OWN		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define WM8776_DAC2_ZFLAG_BOTH		(2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define WM8776_DAC2_ZFLAG_EITHER	(3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define WM8776_REG_DACIFCTRL	0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define WM8776_FMT_RIGHTJ		(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define WM8776_FMT_LEFTJ		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define WM8776_FMT_I2S			(2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define WM8776_FMT_DSP			(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define WM8776_FMT_DSP_LATE		(1 << 2)	/* in DSP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define WM8776_FMT_LRC_INVERTED		(1 << 2)	/* in other modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define WM8776_FMT_BCLK_INVERTED	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define WM8776_FMT_16BIT		(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define WM8776_FMT_20BIT		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define WM8776_FMT_24BIT		(2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define WM8776_FMT_32BIT		(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define WM8776_REG_ADCIFCTRL	0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define WM8776_FMT_ADCMCLK_INVERTED	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define WM8776_FMT_ADCHPD		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define WM8776_REG_MSTRCTRL	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define WM8776_IF_ADC256FS		(2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define WM8776_IF_ADC384FS		(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define WM8776_IF_ADC512FS		(4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define WM8776_IF_ADC768FS		(5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define WM8776_IF_OVERSAMP64		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define WM8776_IF_DAC128FS		(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define WM8776_IF_DAC192FS		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define WM8776_IF_DAC256FS		(2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define WM8776_IF_DAC384FS		(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define WM8776_IF_DAC512FS		(4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define WM8776_IF_DAC768FS		(5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define WM8776_IF_DAC_MASTER		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define WM8776_IF_ADC_MASTER		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define WM8776_REG_PWRDOWN	0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define WM8776_PWR_PDWN			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define WM8776_PWR_ADCPD		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define WM8776_PWR_DACPD		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define WM8776_PWR_HPPD			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define WM8776_PWR_AINPD		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define WM8776_REG_ADCLVOL	0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define WM8776_REG_ADCRVOL	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define WM8776_ADC_GAIN_MASK		0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define WM8776_ADC_ZCEN			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define WM8776_REG_ALCCTRL1	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define WM8776_ALC1_LCT_MASK		0x0f	/* 0=-16dB, 1=-15dB..15=-1dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define WM8776_ALC1_MAXGAIN_MASK	0x70	/* 0,1=0dB, 2=+4dB...7=+24dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define WM8776_ALC1_LCSEL_MASK		0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define WM8776_ALC1_LCSEL_LIMITER	(0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define WM8776_ALC1_LCSEL_ALCR		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define WM8776_ALC1_LCSEL_ALCL		(2 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define WM8776_ALC1_LCSEL_ALCSTEREO	(3 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define WM8776_REG_ALCCTRL2	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define WM8776_ALC2_HOLD_MASK		0x0f	/*0=0ms, 1=2.67ms, 2=5.33ms.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define WM8776_ALC2_ZCEN		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define WM8776_ALC2_LCEN		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define WM8776_REG_ALCCTRL3	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define WM8776_ALC3_ATK_MASK		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define WM8776_ALC3_DCY_MASK		0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define WM8776_ALC3_FDECAY		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define WM8776_REG_NOISEGATE	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define WM8776_NGAT_ENABLE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define WM8776_NGAT_THR_MASK		0x1c	/*0=-78dB, 1=-72dB...7=-36dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define WM8776_REG_LIMITER	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define WM8776_LIM_MAXATTEN_MASK	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WM8776_LIM_TRANWIN_MASK		0x70	/*0=0us, 1=62.5us, 2=125us.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define WM8776_REG_ADCMUX	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define WM8776_ADC_MUX_AIN1		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define WM8776_ADC_MUX_AIN2		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define WM8776_ADC_MUX_AIN3		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define WM8776_ADC_MUX_AIN4		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define WM8776_ADC_MUX_AIN5		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define WM8776_ADC_MUTER		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define WM8776_ADC_MUTEL		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define WM8776_ADC_LRBOTH		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define WM8776_REG_OUTMUX	0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WM8776_OUTMUX_DAC		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define WM8776_OUTMUX_AUX		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define WM8776_OUTMUX_BYPASS		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define WM8776_REG_RESET	0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define WM8776_REG_COUNT	0x17	/* don't cache the RESET register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct snd_wm8776;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct snd_wm8776_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	void (*write)(struct snd_wm8776 *wm, u8 addr, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) enum snd_wm8776_ctl_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	WM8776_CTL_DAC_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	WM8776_CTL_DAC_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	WM8776_CTL_DAC_ZC_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	WM8776_CTL_HP_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	WM8776_CTL_HP_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	WM8776_CTL_HP_ZC_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	WM8776_CTL_AUX_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	WM8776_CTL_BYPASS_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	WM8776_CTL_DAC_IZD_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	WM8776_CTL_PHASE_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	WM8776_CTL_DEEMPH_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	WM8776_CTL_ADC_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	WM8776_CTL_ADC_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	WM8776_CTL_INPUT1_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	WM8776_CTL_INPUT2_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	WM8776_CTL_INPUT3_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	WM8776_CTL_INPUT4_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	WM8776_CTL_INPUT5_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	WM8776_CTL_AGC_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	WM8776_CTL_LIM_THR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	WM8776_CTL_LIM_ATK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	WM8776_CTL_LIM_DCY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	WM8776_CTL_LIM_TRANWIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	WM8776_CTL_LIM_MAXATTN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	WM8776_CTL_ALC_TGT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	WM8776_CTL_ALC_ATK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	WM8776_CTL_ALC_DCY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	WM8776_CTL_ALC_MAXGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	WM8776_CTL_ALC_MAXATTN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	WM8776_CTL_ALC_HLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	WM8776_CTL_NGT_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	WM8776_CTL_NGT_THR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	WM8776_CTL_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define WM8776_ENUM_MAX		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define WM8776_FLAG_STEREO	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define WM8776_FLAG_VOL_UPDATE	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define WM8776_FLAG_INVERT	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define WM8776_FLAG_LIM		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define WM8776_FLAG_ALC		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct snd_wm8776_ctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	snd_ctl_elem_type_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	const char *const enum_names[WM8776_ENUM_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	const unsigned int *tlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u16 reg1, reg2, mask1, mask2, min, max, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	void (*set)(struct snd_wm8776 *wm, u16 ch1, u16 ch2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	void (*get)(struct snd_wm8776 *wm, u16 *ch1, u16 *ch2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) enum snd_wm8776_agc_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	WM8776_AGC_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	WM8776_AGC_LIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	WM8776_AGC_ALC_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	WM8776_AGC_ALC_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	WM8776_AGC_ALC_STEREO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct snd_wm8776 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct snd_wm8776_ctl ctl[WM8776_CTL_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	enum snd_wm8776_agc_mode agc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct snd_wm8776_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u16 regs[WM8776_REG_COUNT];	/* 9-bit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) void snd_wm8776_init(struct snd_wm8776 *wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void snd_wm8776_resume(struct snd_wm8776 *wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void snd_wm8776_set_power(struct snd_wm8776 *wm, u16 power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void snd_wm8776_volume_restore(struct snd_wm8776 *wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int snd_wm8776_build_controls(struct snd_wm8776 *wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif /* __SOUND_WM8776_H */