^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for ICEnsemble VT17xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Lowlevel functions for WM8776 codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "wm8776.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* low-level access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static void snd_wm8776_write(struct snd_wm8776 *wm, u16 addr, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u8 bus_addr = addr << 1 | data >> 8; /* addr + 9th data bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u8 bus_data = data & 0xff; /* remaining 8 data bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) if (addr < WM8776_REG_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) wm->regs[addr] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) wm->ops.write(wm, bus_addr, bus_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* register-level functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void snd_wm8776_activate_ctl(struct snd_wm8776 *wm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) const char *ctl_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) bool active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct snd_card *card = wm->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct snd_kcontrol_volatile *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct snd_ctl_elem_id elem_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int index_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) memset(&elem_id, 0, sizeof(elem_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) strlcpy(elem_id.name, ctl_name, sizeof(elem_id.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) kctl = snd_ctl_find_id(card, &elem_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (!kctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) index_offset = snd_ctl_get_ioff(kctl, &kctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) vd = &kctl->vd[index_offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) vd->access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) vd->access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) snd_ctl_notify(card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void snd_wm8776_update_agc_ctl(struct snd_wm8776 *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int i, flags_on = 0, flags_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) switch (wm->agc_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case WM8776_AGC_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) flags_off = WM8776_FLAG_LIM | WM8776_FLAG_ALC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case WM8776_AGC_LIM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) flags_off = WM8776_FLAG_ALC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) flags_on = WM8776_FLAG_LIM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case WM8776_AGC_ALC_R:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case WM8776_AGC_ALC_L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) case WM8776_AGC_ALC_STEREO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) flags_off = WM8776_FLAG_LIM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) flags_on = WM8776_FLAG_ALC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) for (i = 0; i < WM8776_CTL_COUNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (wm->ctl[i].flags & flags_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) snd_wm8776_activate_ctl(wm, wm->ctl[i].name, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) else if (wm->ctl[i].flags & flags_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) snd_wm8776_activate_ctl(wm, wm->ctl[i].name, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void snd_wm8776_set_agc(struct snd_wm8776 *wm, u16 agc, u16 nothing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u16 alc1 = wm->regs[WM8776_REG_ALCCTRL1] & ~WM8776_ALC1_LCT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u16 alc2 = wm->regs[WM8776_REG_ALCCTRL2] & ~WM8776_ALC2_LCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) switch (agc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case 0: /* Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) wm->agc_mode = WM8776_AGC_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case 1: /* Limiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) alc2 |= WM8776_ALC2_LCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) wm->agc_mode = WM8776_AGC_LIM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case 2: /* ALC Right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) alc1 |= WM8776_ALC1_LCSEL_ALCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) alc2 |= WM8776_ALC2_LCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) wm->agc_mode = WM8776_AGC_ALC_R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case 3: /* ALC Left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) alc1 |= WM8776_ALC1_LCSEL_ALCL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) alc2 |= WM8776_ALC2_LCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) wm->agc_mode = WM8776_AGC_ALC_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case 4: /* ALC Stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) alc1 |= WM8776_ALC1_LCSEL_ALCSTEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) alc2 |= WM8776_ALC2_LCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) wm->agc_mode = WM8776_AGC_ALC_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) snd_wm8776_write(wm, WM8776_REG_ALCCTRL1, alc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) snd_wm8776_write(wm, WM8776_REG_ALCCTRL2, alc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) snd_wm8776_update_agc_ctl(wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void snd_wm8776_get_agc(struct snd_wm8776 *wm, u16 *mode, u16 *nothing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *mode = wm->agc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* mixer controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const DECLARE_TLV_DB_SCALE(wm8776_hp_tlv, -7400, 100, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const DECLARE_TLV_DB_SCALE(wm8776_dac_tlv, -12750, 50, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const DECLARE_TLV_DB_SCALE(wm8776_adc_tlv, -10350, 50, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const DECLARE_TLV_DB_SCALE(wm8776_lct_tlv, -1600, 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const DECLARE_TLV_DB_SCALE(wm8776_maxgain_tlv, 0, 400, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const DECLARE_TLV_DB_SCALE(wm8776_ngth_tlv, -7800, 600, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const DECLARE_TLV_DB_SCALE(wm8776_maxatten_lim_tlv, -1200, 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const DECLARE_TLV_DB_SCALE(wm8776_maxatten_alc_tlv, -2100, 400, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct snd_wm8776_ctl snd_wm8776_default_ctl[WM8776_CTL_COUNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [WM8776_CTL_DAC_VOL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .name = "Master Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .tlv = wm8776_dac_tlv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .reg1 = WM8776_REG_DACLVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .reg2 = WM8776_REG_DACRVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .mask1 = WM8776_DACVOL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .mask2 = WM8776_DACVOL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .max = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .flags = WM8776_FLAG_STEREO | WM8776_FLAG_VOL_UPDATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [WM8776_CTL_DAC_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "Master Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .reg1 = WM8776_REG_DACCTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .reg2 = WM8776_REG_DACCTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .mask1 = WM8776_DAC_PL_LL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .mask2 = WM8776_DAC_PL_RR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .flags = WM8776_FLAG_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [WM8776_CTL_DAC_ZC_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "Master Zero Cross Detect Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .reg1 = WM8776_REG_DACCTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .mask1 = WM8776_DAC_DZCEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [WM8776_CTL_HP_VOL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .name = "Headphone Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .tlv = wm8776_hp_tlv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .reg1 = WM8776_REG_HPLVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .reg2 = WM8776_REG_HPRVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .mask1 = WM8776_HPVOL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .mask2 = WM8776_HPVOL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .min = 0x2f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .max = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .flags = WM8776_FLAG_STEREO | WM8776_FLAG_VOL_UPDATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [WM8776_CTL_HP_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .name = "Headphone Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .reg1 = WM8776_REG_PWRDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .mask1 = WM8776_PWR_HPPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .flags = WM8776_FLAG_INVERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [WM8776_CTL_HP_ZC_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .name = "Headphone Zero Cross Detect Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .reg1 = WM8776_REG_HPLVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .reg2 = WM8776_REG_HPRVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .mask1 = WM8776_VOL_HPZCEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .mask2 = WM8776_VOL_HPZCEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .flags = WM8776_FLAG_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [WM8776_CTL_AUX_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .name = "AUX Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .reg1 = WM8776_REG_OUTMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .mask1 = WM8776_OUTMUX_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [WM8776_CTL_BYPASS_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "Bypass Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .reg1 = WM8776_REG_OUTMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .mask1 = WM8776_OUTMUX_BYPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [WM8776_CTL_DAC_IZD_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .name = "Infinite Zero Detect Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .reg1 = WM8776_REG_DACCTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .mask1 = WM8776_DAC_IZD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) [WM8776_CTL_PHASE_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .name = "Phase Invert Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .reg1 = WM8776_REG_PHASESWAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .reg2 = WM8776_REG_PHASESWAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .mask1 = WM8776_PHASE_INVERTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .mask2 = WM8776_PHASE_INVERTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .flags = WM8776_FLAG_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [WM8776_CTL_DEEMPH_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .name = "Deemphasis Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .reg1 = WM8776_REG_DACCTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .mask1 = WM8776_DAC2_DEEMPH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) [WM8776_CTL_ADC_VOL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .name = "Input Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .tlv = wm8776_adc_tlv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .reg1 = WM8776_REG_ADCLVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .reg2 = WM8776_REG_ADCRVOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .mask1 = WM8776_ADC_GAIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .mask2 = WM8776_ADC_GAIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .max = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .flags = WM8776_FLAG_STEREO | WM8776_FLAG_VOL_UPDATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) [WM8776_CTL_ADC_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .name = "Input Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .reg1 = WM8776_REG_ADCMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .reg2 = WM8776_REG_ADCMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .mask1 = WM8776_ADC_MUTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .mask2 = WM8776_ADC_MUTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .flags = WM8776_FLAG_STEREO | WM8776_FLAG_INVERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [WM8776_CTL_INPUT1_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "AIN1 Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .reg1 = WM8776_REG_ADCMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .mask1 = WM8776_ADC_MUX_AIN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [WM8776_CTL_INPUT2_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .name = "AIN2 Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .reg1 = WM8776_REG_ADCMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .mask1 = WM8776_ADC_MUX_AIN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [WM8776_CTL_INPUT3_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .name = "AIN3 Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .reg1 = WM8776_REG_ADCMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .mask1 = WM8776_ADC_MUX_AIN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) [WM8776_CTL_INPUT4_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .name = "AIN4 Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .reg1 = WM8776_REG_ADCMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .mask1 = WM8776_ADC_MUX_AIN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) [WM8776_CTL_INPUT5_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .name = "AIN5 Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .reg1 = WM8776_REG_ADCMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .mask1 = WM8776_ADC_MUX_AIN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [WM8776_CTL_AGC_SEL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .name = "AGC Select Capture Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .enum_names = { "Off", "Limiter", "ALC Right", "ALC Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "ALC Stereo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .max = 5, /* .enum_names item count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .set = snd_wm8776_set_agc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .get = snd_wm8776_get_agc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [WM8776_CTL_LIM_THR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .name = "Limiter Threshold Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .tlv = wm8776_lct_tlv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .reg1 = WM8776_REG_ALCCTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .mask1 = WM8776_ALC1_LCT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .max = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .flags = WM8776_FLAG_LIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) [WM8776_CTL_LIM_ATK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .name = "Limiter Attack Time Capture Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .enum_names = { "0.25 ms", "0.5 ms", "1 ms", "2 ms", "4 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "8 ms", "16 ms", "32 ms", "64 ms", "128 ms", "256 ms" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .max = 11, /* .enum_names item count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .reg1 = WM8776_REG_ALCCTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .mask1 = WM8776_ALC3_ATK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .flags = WM8776_FLAG_LIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [WM8776_CTL_LIM_DCY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .name = "Limiter Decay Time Capture Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .enum_names = { "1.2 ms", "2.4 ms", "4.8 ms", "9.6 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "19.2 ms", "38.4 ms", "76.8 ms", "154 ms", "307 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "614 ms", "1.23 s" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .max = 11, /* .enum_names item count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .reg1 = WM8776_REG_ALCCTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .mask1 = WM8776_ALC3_DCY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .flags = WM8776_FLAG_LIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [WM8776_CTL_LIM_TRANWIN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .name = "Limiter Transient Window Capture Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .enum_names = { "0 us", "62.5 us", "125 us", "250 us", "500 us",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "1 ms", "2 ms", "4 ms" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .max = 8, /* .enum_names item count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .reg1 = WM8776_REG_LIMITER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .mask1 = WM8776_LIM_TRANWIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .flags = WM8776_FLAG_LIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [WM8776_CTL_LIM_MAXATTN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .name = "Limiter Maximum Attenuation Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .tlv = wm8776_maxatten_lim_tlv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .reg1 = WM8776_REG_LIMITER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .mask1 = WM8776_LIM_MAXATTEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .min = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .max = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .flags = WM8776_FLAG_LIM | WM8776_FLAG_INVERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [WM8776_CTL_ALC_TGT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .name = "ALC Target Level Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .tlv = wm8776_lct_tlv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .reg1 = WM8776_REG_ALCCTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .mask1 = WM8776_ALC1_LCT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .max = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .flags = WM8776_FLAG_ALC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) [WM8776_CTL_ALC_ATK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .name = "ALC Attack Time Capture Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .enum_names = { "8.40 ms", "16.8 ms", "33.6 ms", "67.2 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "134 ms", "269 ms", "538 ms", "1.08 s", "2.15 s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "4.3 s", "8.6 s" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .max = 11, /* .enum_names item count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .reg1 = WM8776_REG_ALCCTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .mask1 = WM8776_ALC3_ATK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .flags = WM8776_FLAG_ALC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [WM8776_CTL_ALC_DCY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .name = "ALC Decay Time Capture Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .enum_names = { "33.5 ms", "67.0 ms", "134 ms", "268 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "536 ms", "1.07 s", "2.14 s", "4.29 s", "8.58 s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) "17.2 s", "34.3 s" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .max = 11, /* .enum_names item count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .reg1 = WM8776_REG_ALCCTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .mask1 = WM8776_ALC3_DCY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .flags = WM8776_FLAG_ALC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) [WM8776_CTL_ALC_MAXGAIN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .name = "ALC Maximum Gain Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .tlv = wm8776_maxgain_tlv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .reg1 = WM8776_REG_ALCCTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .mask1 = WM8776_ALC1_MAXGAIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .max = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .flags = WM8776_FLAG_ALC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) [WM8776_CTL_ALC_MAXATTN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .name = "ALC Maximum Attenuation Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .tlv = wm8776_maxatten_alc_tlv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .reg1 = WM8776_REG_LIMITER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .mask1 = WM8776_LIM_MAXATTEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .min = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .max = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .flags = WM8776_FLAG_ALC | WM8776_FLAG_INVERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) [WM8776_CTL_ALC_HLD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .name = "ALC Hold Time Capture Enum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .enum_names = { "0 ms", "2.67 ms", "5.33 ms", "10.6 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "21.3 ms", "42.7 ms", "85.3 ms", "171 ms", "341 ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) "683 ms", "1.37 s", "2.73 s", "5.46 s", "10.9 s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) "21.8 s", "43.7 s" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .max = 16, /* .enum_names item count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .reg1 = WM8776_REG_ALCCTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .mask1 = WM8776_ALC2_HOLD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .flags = WM8776_FLAG_ALC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) [WM8776_CTL_NGT_SW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .name = "Noise Gate Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .reg1 = WM8776_REG_NOISEGATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .mask1 = WM8776_NGAT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .flags = WM8776_FLAG_ALC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) [WM8776_CTL_NGT_THR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .name = "Noise Gate Threshold Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .tlv = wm8776_ngth_tlv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .reg1 = WM8776_REG_NOISEGATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .mask1 = WM8776_NGAT_THR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .max = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .flags = WM8776_FLAG_ALC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* exported functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) void snd_wm8776_init(struct snd_wm8776 *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const u16 default_values[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 0x000, 0x100, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 0x000, 0x100, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 0x000, 0x090, 0x000, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 0x022, 0x022, 0x022,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0x008, 0x0cf, 0x0cf, 0x07b, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 0x032, 0x000, 0x0a6, 0x001, 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) memcpy(wm->ctl, snd_wm8776_default_ctl, sizeof(wm->ctl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) snd_wm8776_write(wm, WM8776_REG_RESET, 0x00); /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* load defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) for (i = 0; i < ARRAY_SIZE(default_values); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) snd_wm8776_write(wm, i, default_values[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) void snd_wm8776_resume(struct snd_wm8776 *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) for (i = 0; i < WM8776_REG_COUNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) snd_wm8776_write(wm, i, wm->regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) void snd_wm8776_set_power(struct snd_wm8776 *wm, u16 power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) snd_wm8776_write(wm, WM8776_REG_PWRDOWN, power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) void snd_wm8776_volume_restore(struct snd_wm8776 *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u16 val = wm->regs[WM8776_REG_DACRVOL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* restore volume after MCLK stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) snd_wm8776_write(wm, WM8776_REG_DACRVOL, val | WM8776_VOL_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* mixer callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int snd_wm8776_volume_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int n = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) uinfo->count = (wm->ctl[n].flags & WM8776_FLAG_STEREO) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) uinfo->value.integer.min = wm->ctl[n].min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) uinfo->value.integer.max = wm->ctl[n].max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int snd_wm8776_enum_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int n = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return snd_ctl_enum_info(uinfo, 1, wm->ctl[n].max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) wm->ctl[n].enum_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int snd_wm8776_ctl_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int n = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u16 val1, val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (wm->ctl[n].get)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) wm->ctl[n].get(wm, &val1, &val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) val1 >>= __ffs(wm->ctl[n].mask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (wm->ctl[n].flags & WM8776_FLAG_STEREO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) val2 >>= __ffs(wm->ctl[n].mask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (wm->ctl[n].flags & WM8776_FLAG_VOL_UPDATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) val2 &= ~WM8776_VOL_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (wm->ctl[n].flags & WM8776_FLAG_INVERT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) val1 = wm->ctl[n].max - (val1 - wm->ctl[n].min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (wm->ctl[n].flags & WM8776_FLAG_STEREO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) val2 = wm->ctl[n].max - (val2 - wm->ctl[n].min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ucontrol->value.integer.value[0] = val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (wm->ctl[n].flags & WM8776_FLAG_STEREO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ucontrol->value.integer.value[1] = val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int snd_wm8776_ctl_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int n = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u16 val, regval1, regval2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* this also works for enum because value is a union */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) regval1 = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) regval2 = ucontrol->value.integer.value[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (wm->ctl[n].flags & WM8776_FLAG_INVERT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) regval1 = wm->ctl[n].max - (regval1 - wm->ctl[n].min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) regval2 = wm->ctl[n].max - (regval2 - wm->ctl[n].min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (wm->ctl[n].set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) wm->ctl[n].set(wm, regval1, regval2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) val |= regval1 << __ffs(wm->ctl[n].mask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* both stereo controls in one register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (wm->ctl[n].flags & WM8776_FLAG_STEREO &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) wm->ctl[n].reg1 == wm->ctl[n].reg2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) val &= ~wm->ctl[n].mask2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) val |= regval2 << __ffs(wm->ctl[n].mask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) snd_wm8776_write(wm, wm->ctl[n].reg1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* stereo controls in different registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (wm->ctl[n].flags & WM8776_FLAG_STEREO &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) wm->ctl[n].reg1 != wm->ctl[n].reg2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) val |= regval2 << __ffs(wm->ctl[n].mask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (wm->ctl[n].flags & WM8776_FLAG_VOL_UPDATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) val |= WM8776_VOL_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) snd_wm8776_write(wm, wm->ctl[n].reg2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int snd_wm8776_add_control(struct snd_wm8776 *wm, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct snd_kcontrol_new cont;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct snd_kcontrol *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) memset(&cont, 0, sizeof(cont));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) cont.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) cont.private_value = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) cont.name = wm->ctl[num].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) cont.access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (wm->ctl[num].flags & WM8776_FLAG_LIM ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) wm->ctl[num].flags & WM8776_FLAG_ALC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) cont.access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) cont.tlv.p = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) cont.get = snd_wm8776_ctl_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) cont.put = snd_wm8776_ctl_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) switch (wm->ctl[num].type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case SNDRV_CTL_ELEM_TYPE_INTEGER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) cont.info = snd_wm8776_volume_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) cont.access |= SNDRV_CTL_ELEM_ACCESS_TLV_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) cont.tlv.p = wm->ctl[num].tlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case SNDRV_CTL_ELEM_TYPE_BOOLEAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) wm->ctl[num].max = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (wm->ctl[num].flags & WM8776_FLAG_STEREO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) cont.info = snd_ctl_boolean_stereo_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) cont.info = snd_ctl_boolean_mono_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case SNDRV_CTL_ELEM_TYPE_ENUMERATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) cont.info = snd_wm8776_enum_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ctl = snd_ctl_new1(&cont, wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (!ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return snd_ctl_add(wm->card, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int snd_wm8776_build_controls(struct snd_wm8776 *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) for (i = 0; i < WM8776_CTL_COUNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (wm->ctl[i].name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) err = snd_wm8776_add_control(wm, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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