^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __SOUND_WM8766_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __SOUND_WM8766_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * ALSA driver for ICEnsemble VT17xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Lowlevel functions for WM8766 codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define WM8766_REG_DACL1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define WM8766_REG_DACR1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define WM8766_VOL_MASK 0x1ff /* incl. update bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define WM8766_VOL_UPDATE (1 << 8) /* update volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define WM8766_REG_DACCTRL1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define WM8766_DAC_MUTEALL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define WM8766_DAC_DEEMPALL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define WM8766_DAC_PDWN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define WM8766_DAC_ATC (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define WM8766_DAC_IZD (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define WM8766_DAC_PL_MASK 0x1e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WM8766_DAC_PL_LL (1 << 5) /* L chan: L signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WM8766_DAC_PL_LR (2 << 5) /* L chan: R signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WM8766_DAC_PL_LB (3 << 5) /* L chan: both */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define WM8766_DAC_PL_RL (1 << 7) /* R chan: L signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WM8766_DAC_PL_RR (2 << 7) /* R chan: R signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WM8766_DAC_PL_RB (3 << 7) /* R chan: both */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WM8766_REG_IFCTRL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define WM8766_IF_FMT_RIGHTJ (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define WM8766_IF_FMT_LEFTJ (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define WM8766_IF_FMT_I2S (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define WM8766_IF_FMT_DSP (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define WM8766_IF_DSP_LATE (1 << 2) /* in DSP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WM8766_IF_LRC_INVERTED (1 << 2) /* in other modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define WM8766_IF_BCLK_INVERTED (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define WM8766_IF_IWL_16BIT (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define WM8766_IF_IWL_20BIT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WM8766_IF_IWL_24BIT (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WM8766_IF_IWL_32BIT (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WM8766_IF_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define WM8766_PHASE_INVERT1 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define WM8766_PHASE_INVERT2 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define WM8766_PHASE_INVERT3 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define WM8766_REG_DACL2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define WM8766_REG_DACR2 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WM8766_REG_DACL3 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define WM8766_REG_DACR3 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WM8766_REG_MASTDA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define WM8766_REG_DACCTRL2 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define WM8766_DAC2_ZCD (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WM8766_DAC2_ZFLAG_ALL (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WM8766_DAC2_ZFLAG_1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define WM8766_DAC2_ZFLAG_2 (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WM8766_DAC2_ZFLAG_3 (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define WM8766_DAC2_MUTE1 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define WM8766_DAC2_MUTE2 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define WM8766_DAC2_MUTE3 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define WM8766_DAC2_DEEMP1 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define WM8766_DAC2_DEEMP2 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define WM8766_DAC2_DEEMP3 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define WM8766_REG_DACCTRL3 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define WM8766_DAC3_DACPD1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define WM8766_DAC3_DACPD2 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define WM8766_DAC3_DACPD3 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define WM8766_DAC3_PWRDNALL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define WM8766_DAC3_POWER_MASK 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define WM8766_DAC3_MASTER (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define WM8766_DAC3_DAC128FS (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define WM8766_DAC3_DAC192FS (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define WM8766_DAC3_DAC256FS (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define WM8766_DAC3_DAC384FS (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define WM8766_DAC3_DAC512FS (4 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define WM8766_DAC3_DAC768FS (5 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define WM8766_DAC3_MSTR_MASK 0x1e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define WM8766_REG_MUTE1 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define WM8766_MUTE1_MPD (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define WM8766_REG_MUTE2 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define WM8766_MUTE2_MPD (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define WM8766_REG_RESET 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define WM8766_REG_COUNT 0x10 /* don't cache the RESET register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct snd_wm8766;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct snd_wm8766_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void (*write)(struct snd_wm8766 *wm, u16 addr, u16 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enum snd_wm8766_ctl_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) WM8766_CTL_CH1_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) WM8766_CTL_CH2_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) WM8766_CTL_CH3_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) WM8766_CTL_CH1_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) WM8766_CTL_CH2_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) WM8766_CTL_CH3_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) WM8766_CTL_PHASE1_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) WM8766_CTL_PHASE2_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) WM8766_CTL_PHASE3_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) WM8766_CTL_DEEMPH1_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) WM8766_CTL_DEEMPH2_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) WM8766_CTL_DEEMPH3_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) WM8766_CTL_IZD_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) WM8766_CTL_ZC_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) WM8766_CTL_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define WM8766_ENUM_MAX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define WM8766_FLAG_STEREO (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define WM8766_FLAG_VOL_UPDATE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define WM8766_FLAG_INVERT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define WM8766_FLAG_LIM (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define WM8766_FLAG_ALC (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct snd_wm8766_ctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) snd_ctl_elem_type_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const char *const enum_names[WM8766_ENUM_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const unsigned int *tlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u16 reg1, reg2, mask1, mask2, min, max, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void (*set)(struct snd_wm8766 *wm, u16 ch1, u16 ch2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void (*get)(struct snd_wm8766 *wm, u16 *ch1, u16 *ch2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum snd_wm8766_agc_mode { WM8766_AGC_OFF, WM8766_AGC_LIM, WM8766_AGC_ALC };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct snd_wm8766 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct snd_wm8766_ctl ctl[WM8766_CTL_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) enum snd_wm8766_agc_mode agc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct snd_wm8766_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u16 regs[WM8766_REG_COUNT]; /* 9-bit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void snd_wm8766_init(struct snd_wm8766 *wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void snd_wm8766_resume(struct snd_wm8766 *wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void snd_wm8766_set_if(struct snd_wm8766 *wm, u16 dac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) void snd_wm8766_volume_restore(struct snd_wm8766 *wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int snd_wm8766_build_controls(struct snd_wm8766 *wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif /* __SOUND_WM8766_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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