^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for ICEnsemble VT1724 (Envy24HT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Lowlevel functions for ONKYO WAVIO SE-90PCI and SE-200PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2007 Shin-ya Okada sh_okada(at)d4.dion.ne.jp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (at) -> @
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ice1712.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "envy24ht.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "se.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct se_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned char ch1, ch2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) } vol[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* ONKYO WAVIO SE-200PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * system configuration ICE_EEP2_SYSCONF=0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * XIN1 49.152MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * not have UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * one stereo ADC and a S/PDIF receiver connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * four stereo DACs connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * AC-Link configuration ICE_EEP2_ACLINK=0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * use I2C, not use AC97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * I2S converters feature ICE_EEP2_I2S=0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * I2S codec has no volume/mute control feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * I2S codec supports 96KHz and 192KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * I2S codec 24bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * S/PDIF configuration ICE_EEP2_SPDIF=0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Enable integrated S/PDIF transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * internal S/PDIF out implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * S/PDIF is stereo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * External S/PDIF out implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * ** connected chips **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * WM8740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * A 2ch-DAC of main outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * It setuped as I2S mode by wire, so no way to setup from software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * The sample-rate are automatically changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * ML/I2S (28pin) --------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * MC/DM1 (27pin) -- 5V |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * MD/DM0 (26pin) -- GND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * MUTEB (25pin) -- NC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * MODE (24pin) -- GND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * CSBIW (23pin) --------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * RSTB (22pin) --R(1K)-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Probably it reduce the noise from the control line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * WM8766
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * A 6ch-DAC for surrounds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * It's control wire was connected to GPIOxx (3-wire serial interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * ML/I2S (11pin) -- GPIO18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * MC/IWL (12pin) -- GPIO17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * MD/DM (13pin) -- GPIO16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * MUTE (14pin) -- GPIO01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * WM8776
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * A 2ch-ADC(with 10ch-selector) plus 2ch-DAC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * It's control wire was connected to SDA/SCLK (2-wire serial interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * MODE (16pin) -- R(1K) -- GND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * CE (17pin) -- R(1K) -- GND 2-wire mode (address=0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * DI (18pin) -- SDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * CL (19pin) -- SCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * ** output pins and device names **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * 7.1ch name -- output connector color -- device (-D option)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * FRONT 2ch -- green -- plughw:0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * CENTER(Lch) SUBWOOFER(Rch) -- black -- plughw:0,2,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * SURROUND 2ch -- orange -- plughw:0,2,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * SURROUND BACK 2ch -- white -- plughw:0,2,2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* WM8740 interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void se200pci_WM8740_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void se200pci_WM8740_set_pro_rate(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* WM8766 interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void se200pci_WM8766_write(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int addr, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const unsigned int DATA = 0x010000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const unsigned int CLOCK = 0x020000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const unsigned int LOAD = 0x040000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const unsigned int ALL_MASK = (DATA | CLOCK | LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) snd_ice1712_save_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) st = ((addr & 0x7f) << 9) | (data & 0x1ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) snd_ice1712_gpio_set_dir(ice, ice->gpio.direction | ALL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask & ~ALL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bits = snd_ice1712_gpio_read(ice) & ~ALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) snd_ice1712_gpio_write(ice, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) bits &= ~CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) st = (st << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (st & 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bits |= DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) bits &= ~DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) snd_ice1712_gpio_write(ice, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) bits |= CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) snd_ice1712_gpio_write(ice, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bits |= LOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) snd_ice1712_gpio_write(ice, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) bits |= (DATA | CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) snd_ice1712_gpio_write(ice, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) snd_ice1712_restore_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void se200pci_WM8766_set_volume(struct snd_ice1712 *ice, int ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int vol1, unsigned int vol2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) switch (ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) se200pci_WM8766_write(ice, 0x000, vol1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) se200pci_WM8766_write(ice, 0x001, vol2 | 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) se200pci_WM8766_write(ice, 0x004, vol1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) se200pci_WM8766_write(ice, 0x005, vol2 | 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) se200pci_WM8766_write(ice, 0x006, vol1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) se200pci_WM8766_write(ice, 0x007, vol2 | 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void se200pci_WM8766_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) se200pci_WM8766_write(ice, 0x1f, 0x000); /* RESET ALL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) se200pci_WM8766_set_volume(ice, 0, 0, 0); /* volume L=0 R=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) se200pci_WM8766_set_volume(ice, 1, 0, 0); /* volume L=0 R=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) se200pci_WM8766_set_volume(ice, 2, 0, 0); /* volume L=0 R=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) se200pci_WM8766_write(ice, 0x03, 0x022); /* serial mode I2S-24bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) se200pci_WM8766_write(ice, 0x0a, 0x080); /* MCLK=256fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) se200pci_WM8766_write(ice, 0x12, 0x000); /* MDP=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) se200pci_WM8766_write(ice, 0x15, 0x000); /* MDP=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) se200pci_WM8766_write(ice, 0x09, 0x000); /* demp=off mute=off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) se200pci_WM8766_write(ice, 0x02, 0x124); /* ch-assign L=L R=R RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) se200pci_WM8766_write(ice, 0x02, 0x120); /* ch-assign L=L R=R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void se200pci_WM8766_set_pro_rate(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (rate > 96000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) se200pci_WM8766_write(ice, 0x0a, 0x000); /* MCLK=128fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) se200pci_WM8766_write(ice, 0x0a, 0x080); /* MCLK=256fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* WM8776 interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void se200pci_WM8776_write(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int addr, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) val = (addr << 9) | data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) snd_vt1724_write_i2c(ice, 0x34, val >> 8, val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void se200pci_WM8776_set_output_volume(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned int vol1, unsigned int vol2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) se200pci_WM8776_write(ice, 0x03, vol1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) se200pci_WM8776_write(ice, 0x04, vol2 | 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void se200pci_WM8776_set_input_volume(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned int vol1, unsigned int vol2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) se200pci_WM8776_write(ice, 0x0e, vol1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) se200pci_WM8776_write(ice, 0x0f, vol2 | 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const char * const se200pci_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "LINE-IN", "CD-IN", "MIC-IN", "ALL-MIX", NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void se200pci_WM8776_set_input_selector(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned int sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const unsigned char vals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* LINE, CD, MIC, ALL, GND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0x10, 0x04, 0x08, 0x1c, 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (sel > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sel = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) se200pci_WM8776_write(ice, 0x15, vals[sel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void se200pci_WM8776_set_afl(struct snd_ice1712 *ice, unsigned int afl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* AFL -- After Fader Listening */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (afl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) se200pci_WM8776_write(ice, 0x16, 0x005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) se200pci_WM8776_write(ice, 0x16, 0x001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const char * const se200pci_agc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "Off", "LimiterMode", "ALCMode", NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static void se200pci_WM8776_set_agc(struct snd_ice1712 *ice, unsigned int agc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* AGC -- Auto Gain Control of the input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) switch (agc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) se200pci_WM8776_write(ice, 0x11, 0x000); /* Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) se200pci_WM8776_write(ice, 0x10, 0x07b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) se200pci_WM8776_write(ice, 0x11, 0x100); /* LimiterMode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) se200pci_WM8776_write(ice, 0x10, 0x1fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) se200pci_WM8776_write(ice, 0x11, 0x100); /* ALCMode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void se200pci_WM8776_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const unsigned short default_values[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 0x100, 0x100, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 0x100, 0x100, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 0x000, 0x090, 0x000, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0x022, 0x022, 0x022,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0x008, 0x0cf, 0x0cf, 0x07b, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0x032, 0x000, 0x0a6, 0x001, 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) se200pci_WM8776_write(ice, 0x17, 0x000); /* reset all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* ADC and DAC interface is I2S 24bits mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* The sample-rate are automatically changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* BUT my board can not do reset all, so I load all by manually. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) for (i = 0; i < ARRAY_SIZE(default_values); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) se200pci_WM8776_write(ice, i, default_values[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) se200pci_WM8776_set_input_selector(ice, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) se200pci_WM8776_set_afl(ice, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) se200pci_WM8776_set_agc(ice, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) se200pci_WM8776_set_input_volume(ice, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) se200pci_WM8776_set_output_volume(ice, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* head phone mute and power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) se200pci_WM8776_write(ice, 0x00, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) se200pci_WM8776_write(ice, 0x01, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) se200pci_WM8776_write(ice, 0x02, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) se200pci_WM8776_write(ice, 0x0d, 0x080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void se200pci_WM8776_set_pro_rate(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* runtime interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void se200pci_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) se200pci_WM8740_set_pro_rate(ice, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) se200pci_WM8766_set_pro_rate(ice, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) se200pci_WM8776_set_pro_rate(ice, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct se200pci_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) WM8766,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) WM8776in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) WM8776out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) WM8776sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) WM8776agc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) WM8776afl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) } target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) enum { VOLUME1, VOLUME2, BOOLEAN, ENUM } type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) const char * const *member;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) const char *comment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct se200pci_control se200pci_cont[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .name = "Front Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .target = WM8776out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .type = VOLUME1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .comment = "Front(green)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .name = "Side Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .target = WM8766,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .type = VOLUME1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .ch = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .comment = "Surround(orange)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .name = "Surround Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .target = WM8766,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .type = VOLUME1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .ch = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .comment = "SurroundBack(white)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .name = "CLFE Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .target = WM8766,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .type = VOLUME1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .ch = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .comment = "Center(Lch)&SubWoofer(Rch)(black)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .name = "Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .target = WM8776in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .type = VOLUME2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .name = "Capture Select",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .target = WM8776sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .type = ENUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .member = se200pci_sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .name = "AGC Capture Mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .target = WM8776agc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .type = ENUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .member = se200pci_agc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .name = "AFL Bypass Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .target = WM8776afl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .type = BOOLEAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int se200pci_get_enum_count(int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) const char * const *member;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) member = se200pci_cont[n].member;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (!member)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) for (c = 0; member[c]; c++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int se200pci_cont_volume_info(struct snd_kcontrol *kc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) uinfo->value.integer.min = 0; /* mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) uinfo->value.integer.max = 0xff; /* 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define se200pci_cont_boolean_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int se200pci_cont_enum_info(struct snd_kcontrol *kc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int n, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) n = kc->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) c = se200pci_get_enum_count(n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return snd_ctl_enum_info(uinfo, 1, c, se200pci_cont[n].member);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int se200pci_cont_volume_get(struct snd_kcontrol *kc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct snd_ctl_elem_value *uc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct snd_ice1712 *ice = snd_kcontrol_chip(kc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct se_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int n = kc->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) uc->value.integer.value[0] = spec->vol[n].ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) uc->value.integer.value[1] = spec->vol[n].ch2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int se200pci_cont_boolean_get(struct snd_kcontrol *kc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct snd_ctl_elem_value *uc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct snd_ice1712 *ice = snd_kcontrol_chip(kc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct se_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int n = kc->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) uc->value.integer.value[0] = spec->vol[n].ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int se200pci_cont_enum_get(struct snd_kcontrol *kc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct snd_ctl_elem_value *uc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct snd_ice1712 *ice = snd_kcontrol_chip(kc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct se_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int n = kc->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) uc->value.enumerated.item[0] = spec->vol[n].ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static void se200pci_cont_update(struct snd_ice1712 *ice, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct se_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) switch (se200pci_cont[n].target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case WM8766:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) se200pci_WM8766_set_volume(ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) se200pci_cont[n].ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) spec->vol[n].ch1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) spec->vol[n].ch2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case WM8776in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) se200pci_WM8776_set_input_volume(ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) spec->vol[n].ch1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) spec->vol[n].ch2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case WM8776out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) se200pci_WM8776_set_output_volume(ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) spec->vol[n].ch1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) spec->vol[n].ch2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case WM8776sel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) se200pci_WM8776_set_input_selector(ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) spec->vol[n].ch1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case WM8776agc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) se200pci_WM8776_set_agc(ice, spec->vol[n].ch1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) case WM8776afl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) se200pci_WM8776_set_afl(ice, spec->vol[n].ch1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int se200pci_cont_volume_put(struct snd_kcontrol *kc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct snd_ctl_elem_value *uc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct snd_ice1712 *ice = snd_kcontrol_chip(kc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct se_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int n = kc->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned int vol1, vol2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) changed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) vol1 = uc->value.integer.value[0] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) vol2 = uc->value.integer.value[1] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (spec->vol[n].ch1 != vol1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) spec->vol[n].ch1 = vol1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) changed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (spec->vol[n].ch2 != vol2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) spec->vol[n].ch2 = vol2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) changed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) se200pci_cont_update(ice, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int se200pci_cont_boolean_put(struct snd_kcontrol *kc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct snd_ctl_elem_value *uc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct snd_ice1712 *ice = snd_kcontrol_chip(kc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct se_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int n = kc->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned int vol1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) vol1 = !!uc->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (spec->vol[n].ch1 != vol1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) spec->vol[n].ch1 = vol1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) se200pci_cont_update(ice, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int se200pci_cont_enum_put(struct snd_kcontrol *kc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct snd_ctl_elem_value *uc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct snd_ice1712 *ice = snd_kcontrol_chip(kc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct se_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int n = kc->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned int vol1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) vol1 = uc->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (vol1 >= se200pci_get_enum_count(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (spec->vol[n].ch1 != vol1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) spec->vol[n].ch1 = vol1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) se200pci_cont_update(ice, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static const DECLARE_TLV_DB_SCALE(db_scale_gain1, -12750, 50, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const DECLARE_TLV_DB_SCALE(db_scale_gain2, -10350, 50, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int se200pci_add_controls(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct snd_kcontrol_new cont;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) memset(&cont, 0, sizeof(cont));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) cont.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) for (i = 0; i < ARRAY_SIZE(se200pci_cont); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) cont.private_value = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cont.name = se200pci_cont[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) cont.access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) cont.tlv.p = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) switch (se200pci_cont[i].type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) case VOLUME1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) case VOLUME2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) cont.info = se200pci_cont_volume_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) cont.get = se200pci_cont_volume_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) cont.put = se200pci_cont_volume_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) cont.access |= SNDRV_CTL_ELEM_ACCESS_TLV_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (se200pci_cont[i].type == VOLUME1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) cont.tlv.p = db_scale_gain1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) cont.tlv.p = db_scale_gain2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case BOOLEAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) cont.info = se200pci_cont_boolean_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) cont.get = se200pci_cont_boolean_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) cont.put = se200pci_cont_boolean_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case ENUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) cont.info = se200pci_cont_enum_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) cont.get = se200pci_cont_enum_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) cont.put = se200pci_cont_enum_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) err = snd_ctl_add(ice->card, snd_ctl_new1(&cont, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* ONKYO WAVIO SE-90PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * system configuration ICE_EEP2_SYSCONF=0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * AC-Link configuration ICE_EEP2_ACLINK=0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * I2S converters feature ICE_EEP2_I2S=0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * S/PDIF configuration ICE_EEP2_SPDIF=0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * ** connected chip **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * WM8716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * A 2ch-DAC of main outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * It setuped as I2S mode by wire, so no way to setup from software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * ML/I2S (28pin) -- +5V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * MC/DM1 (27pin) -- GND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * MC/DM0 (26pin) -- GND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * MUTEB (25pin) -- open (internal pull-up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * MODE (24pin) -- GND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * CSBIWO (23pin) -- +5V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Nothing to do for this chip. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* probe/initialize/setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int se_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct se_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) spec = kzalloc(sizeof(*spec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (!spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ice->spec = spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (ice->eeprom.subvendor == VT1724_SUBDEVICE_SE90PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ice->num_total_dacs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ice->num_total_adcs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ice->vt1720 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) } else if (ice->eeprom.subvendor == VT1724_SUBDEVICE_SE200PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ice->num_total_dacs = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ice->num_total_adcs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) se200pci_WM8740_init(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) se200pci_WM8766_init(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) se200pci_WM8776_init(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ice->gpio.set_pro_rate = se200pci_set_pro_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int se_add_controls(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* nothing to do for VT1724_SUBDEVICE_SE90PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (ice->eeprom.subvendor == VT1724_SUBDEVICE_SE200PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) err = se200pci_add_controls(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* entry point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static const unsigned char se200pci_eeprom[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) [ICE_EEP2_SYSCONF] = 0x4b, /* 49.152Hz, spdif-in/ADC, 4DACs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) [ICE_EEP2_ACLINK] = 0x80, /* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) [ICE_EEP2_I2S] = 0x78, /* 96k-ok, 24bit, 192k-ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) [ICE_EEP2_GPIO_DIR] = 0x02, /* WM8766 mute 1=output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) [ICE_EEP2_GPIO_DIR1] = 0x00, /* not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) [ICE_EEP2_GPIO_DIR2] = 0x07, /* WM8766 ML/MC/MD 1=output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) [ICE_EEP2_GPIO_MASK] = 0x00, /* 0=writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) [ICE_EEP2_GPIO_MASK1] = 0x00, /* 0=writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) [ICE_EEP2_GPIO_MASK2] = 0x00, /* 0=writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) [ICE_EEP2_GPIO_STATE] = 0x00, /* WM8766 mute=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) [ICE_EEP2_GPIO_STATE1] = 0x00, /* not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) [ICE_EEP2_GPIO_STATE2] = 0x07, /* WM8766 ML/MC/MD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static const unsigned char se90pci_eeprom[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) [ICE_EEP2_SYSCONF] = 0x4b, /* 49.152Hz, spdif-in/ADC, 4DACs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) [ICE_EEP2_ACLINK] = 0x80, /* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) [ICE_EEP2_I2S] = 0x78, /* 96k-ok, 24bit, 192k-ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* ALL GPIO bits are in input mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct snd_ice1712_card_info snd_vt1724_se_cards[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .subvendor = VT1724_SUBDEVICE_SE200PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .name = "ONKYO SE200PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .model = "se200pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .chip_init = se_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .build_controls = se_add_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .eeprom_size = sizeof(se200pci_eeprom),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .eeprom_data = se200pci_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .subvendor = VT1724_SUBDEVICE_SE90PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .name = "ONKYO SE90PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .model = "se90pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .chip_init = se_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .build_controls = se_add_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .eeprom_size = sizeof(se90pci_eeprom),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .eeprom_data = se90pci_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {} /*terminator*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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