^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for ICEnsemble VT1724 (Envy24HT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Lowlevel functions for Infrasonic Quartet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2009 Pavel Hofman <pavel.hofman@ivitera.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ice1712.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "envy24ht.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/ak4113.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "quartet.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct qtet_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct ak4113 *ak4113;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned int scr; /* system control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned int mcr; /* monitoring control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned int cpld; /* cpld register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct qtet_kcontrol_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void (*set_register)(struct snd_ice1712 *ice, unsigned int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned int (*get_register)(struct snd_ice1712 *ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) const char * const texts[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) IN12_SEL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) IN34_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) AIN34_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) COAX_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) IN12_MON12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) IN12_MON34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) IN34_MON12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) IN34_MON34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) OUT12_MON34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) OUT34_MON12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const char * const ext_clock_names[3] = {"IEC958 In", "Word Clock 1xFS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "Word Clock 256xFS"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* chip address on I2C bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AK4113_ADDR 0x26 /* S/PDIF receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* chip address on SPI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AK4620_ADDR 0x02 /* ADC/DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * GPIO pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* GPIO0 - O - DATA0, def. 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GPIO_D0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* GPIO1 - I/O - DATA1, Jack Detect Input0 (0:present, 1:missing), def. 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GPIO_D1_JACKDTC0 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* GPIO2 - I/O - DATA2, Jack Detect Input1 (0:present, 1:missing), def. 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GPIO_D2_JACKDTC1 (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* GPIO3 - I/O - DATA3, def. 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GPIO_D3 (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* GPIO4 - I/O - DATA4, SPI CDTO, def. 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GPIO_D4_SPI_CDTO (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* GPIO5 - I/O - DATA5, SPI CCLK, def. 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GPIO_D5_SPI_CCLK (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* GPIO6 - I/O - DATA6, Cable Detect Input (0:detected, 1:not detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GPIO_D6_CD (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* GPIO7 - I/O - DATA7, Device Detect Input (0:detected, 1:not detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GPIO_D7_DD (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* GPIO8 - O - CPLD Chip Select, def. 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GPIO_CPLD_CSN (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* GPIO9 - O - CPLD register read/write (0:write, 1:read), def. 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GPIO_CPLD_RW (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* GPIO10 - O - SPI Chip Select for CODEC#0, def. 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GPIO_SPI_CSN0 (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* GPIO11 - O - SPI Chip Select for CODEC#1, def. 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GPIO_SPI_CSN1 (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* GPIO12 - O - Ex. Register Output Enable (0:enable, 1:disable), def. 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * init 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GPIO_EX_GPIOE (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* GPIO13 - O - Ex. Register0 Chip Select for System Control Register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * def. 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GPIO_SCR (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* GPIO14 - O - Ex. Register1 Chip Select for Monitor Control Register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * def. 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GPIO_MCR (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GPIO_SPI_ALL (GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) GPIO_SPI_CSN0 | GPIO_SPI_CSN1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GPIO_DATA_MASK (GPIO_D0 | GPIO_D1_JACKDTC0 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) GPIO_D2_JACKDTC1 | GPIO_D3 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) GPIO_D6_CD | GPIO_D7_DD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* System Control Register GPIO_SCR data bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Mic/Line select relay (0:line, 1:mic) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SCR_RELAY GPIO_D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Phantom power drive control (0:5V, 1:48V) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SCR_PHP_V GPIO_D1_JACKDTC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* H/W mute control (0:Normal, 1:Mute) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SCR_MUTE GPIO_D2_JACKDTC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Phantom power control (0:Phantom on, 1:off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SCR_PHP GPIO_D3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Analog input 1/2 Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SCR_AIN12_SEL0 GPIO_D4_SPI_CDTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SCR_AIN12_SEL1 GPIO_D5_SPI_CCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Analog input 3/4 Source Select (0:line, 1:hi-z) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SCR_AIN34_SEL GPIO_D6_CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Codec Power Down (0:power down, 1:normal) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SCR_CODEC_PDN GPIO_D7_DD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SCR_AIN12_LINE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SCR_AIN12_MIC (SCR_AIN12_SEL0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SCR_AIN12_LOWCUT (SCR_AIN12_SEL1 | SCR_AIN12_SEL0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Monitor Control Register GPIO_MCR data bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Input 1/2 to Monitor 1/2 (0:off, 1:on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MCR_IN12_MON12 GPIO_D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Input 1/2 to Monitor 3/4 (0:off, 1:on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MCR_IN12_MON34 GPIO_D1_JACKDTC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Input 3/4 to Monitor 1/2 (0:off, 1:on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MCR_IN34_MON12 GPIO_D2_JACKDTC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Input 3/4 to Monitor 3/4 (0:off, 1:on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MCR_IN34_MON34 GPIO_D3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Output to Monitor 1/2 (0:off, 1:on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MCR_OUT34_MON12 GPIO_D4_SPI_CDTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Output to Monitor 3/4 (0:off, 1:on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MCR_OUT12_MON34 GPIO_D5_SPI_CCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* CPLD Register DATA bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Clock Rate Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CPLD_CKS0 GPIO_D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CPLD_CKS1 GPIO_D1_JACKDTC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CPLD_CKS2 GPIO_D2_JACKDTC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Sync Source Select (0:Internal, 1:External) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CPLD_SYNC_SEL GPIO_D3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Word Clock FS Select (0:FS, 1:256FS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CPLD_WORD_SEL GPIO_D4_SPI_CDTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Coaxial Output Source (IS-Link) (0:SPDIF, 1:I2S) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CPLD_COAX_OUT GPIO_D5_SPI_CCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Input 1/2 Source Select (0:Analog12, 1:An34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CPLD_IN12_SEL GPIO_D6_CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Input 3/4 Source Select (0:Analog34, 1:Digital In) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CPLD_IN34_SEL GPIO_D7_DD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* internal clock (CPLD_SYNC_SEL = 0) options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CPLD_CKS_44100HZ (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CPLD_CKS_48000HZ (CPLD_CKS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CPLD_CKS_88200HZ (CPLD_CKS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CPLD_CKS_96000HZ (CPLD_CKS1 | CPLD_CKS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CPLD_CKS_176400HZ (CPLD_CKS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CPLD_CKS_192000HZ (CPLD_CKS2 | CPLD_CKS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CPLD_CKS_MASK (CPLD_CKS0 | CPLD_CKS1 | CPLD_CKS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* external clock (CPLD_SYNC_SEL = 1) options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* external clock - SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CPLD_EXT_SPDIF (0 | CPLD_SYNC_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* external clock - WordClock 1xfs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CPLD_EXT_WORDCLOCK_1FS (CPLD_CKS1 | CPLD_SYNC_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* external clock - WordClock 256xfs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CPLD_EXT_WORDCLOCK_256FS (CPLD_CKS1 | CPLD_WORD_SEL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CPLD_SYNC_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define EXT_SPDIF_TYPE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define EXT_WORDCLOCK_1FS_TYPE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define EXT_WORDCLOCK_256FS_TYPE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AK4620_DFS0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AK4620_DFS1 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AK4620_CKS0 (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define AK4620_CKS1 (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Clock and Format Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AK4620_DFS_REG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Deem and Volume Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AK4620_DEEMVOL_REG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AK4620_SMUTE (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * Conversion from int value to its binary form. Used for debugging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * The output buffer must be allocated prior to calling the function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static char *get_binary(char *buffer, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int i, j, pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) for (i = 0; i < 4; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) for (j = 0; j < 8; ++j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (value & (1 << (31-(i*8 + j))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) buffer[pos] = '1';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) buffer[pos] = '0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (i < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) buffer[pos] = ' ';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) buffer[pos] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Initial setup of the conversion array GPIO <-> rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const unsigned int qtet_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 44100, 48000, 88200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 96000, 176400, 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const unsigned int cks_vals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) CPLD_CKS_44100HZ, CPLD_CKS_48000HZ, CPLD_CKS_88200HZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) CPLD_CKS_96000HZ, CPLD_CKS_176400HZ, CPLD_CKS_192000HZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct snd_pcm_hw_constraint_list qtet_rates_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .count = ARRAY_SIZE(qtet_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .list = qtet_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void qtet_ak4113_write(void *private_data, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) snd_vt1724_write_i2c((struct snd_ice1712 *)private_data, AK4113_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static unsigned char qtet_ak4113_read(void *private_data, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return snd_vt1724_read_i2c((struct snd_ice1712 *)private_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) AK4113_ADDR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * AK4620 section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Write data to addr register of ak4620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void qtet_akm_write(struct snd_akm4xxx *ak, int chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned char addr, unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int tmp, orig_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int addrdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct snd_ice1712 *ice = ak->private_data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (snd_BUG_ON(chip < 0 || chip >= 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*dev_dbg(ice->card->dev, "Writing to AK4620: chip=%d, addr=0x%x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) data=0x%x\n", chip, addr, data);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) orig_dir = ice->gpio.get_dir(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ice->gpio.set_dir(ice, orig_dir | GPIO_SPI_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* set mask - only SPI bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ice->gpio.set_mask(ice, ~GPIO_SPI_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) tmp = ice->gpio.get_data(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* high all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) tmp |= GPIO_SPI_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ice->gpio.set_data(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* drop chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* CODEC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) tmp &= ~GPIO_SPI_CSN1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) tmp &= ~GPIO_SPI_CSN0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ice->gpio.set_data(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* build I2C address + data byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) addrdata = (AK4620_ADDR << 6) | 0x20 | (addr & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) addrdata = (addrdata << 8) | data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) for (idx = 15; idx >= 0; idx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* drop clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) tmp &= ~GPIO_D5_SPI_CCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ice->gpio.set_data(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* set data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (addrdata & (1 << idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) tmp |= GPIO_D4_SPI_CDTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) tmp &= ~GPIO_D4_SPI_CDTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ice->gpio.set_data(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* raise clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) tmp |= GPIO_D5_SPI_CCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ice->gpio.set_data(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* all back to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) tmp |= GPIO_SPI_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ice->gpio.set_data(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* return all gpios to non-writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ice->gpio.set_mask(ice, 0xffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* restore GPIOs direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ice->gpio.set_dir(ice, orig_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void qtet_akm_set_regs(struct snd_akm4xxx *ak, unsigned char addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned char mask, unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned char tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) for (chip = 0; chip < ak->num_chips; chip++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) tmp = snd_akm4xxx_get(ak, chip, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* clear the bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) tmp &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* set the new bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) tmp |= value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) snd_akm4xxx_write(ak, chip, addr, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * change the rate of AK4620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void qtet_akm_set_rate_val(struct snd_akm4xxx *ak, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned char ak4620_dfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (rate == 0) /* no hint - S/PDIF input is master or the new spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) input rate undetected, simply return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* adjust DFS on codecs - see datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (rate > 108000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ak4620_dfs = AK4620_DFS1 | AK4620_CKS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) else if (rate > 54000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ak4620_dfs = AK4620_DFS0 | AK4620_CKS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ak4620_dfs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* set new value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) qtet_akm_set_regs(ak, AK4620_DFS_REG, AK4620_DFS0 | AK4620_DFS1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) AK4620_CKS0 | AK4620_CKS1, ak4620_dfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define AK_CONTROL(xname, xch) { .name = xname, .num_channels = xch }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PCM_12_PLAYBACK_VOLUME "PCM 1/2 Playback Volume"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PCM_34_PLAYBACK_VOLUME "PCM 3/4 Playback Volume"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define PCM_12_CAPTURE_VOLUME "PCM 1/2 Capture Volume"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PCM_34_CAPTURE_VOLUME "PCM 3/4 Capture Volume"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct snd_akm4xxx_dac_channel qtet_dac[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) AK_CONTROL(PCM_12_PLAYBACK_VOLUME, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) AK_CONTROL(PCM_34_PLAYBACK_VOLUME, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const struct snd_akm4xxx_adc_channel qtet_adc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) AK_CONTROL(PCM_12_CAPTURE_VOLUME, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) AK_CONTROL(PCM_34_CAPTURE_VOLUME, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const struct snd_akm4xxx akm_qtet_dac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .type = SND_AK4620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .num_dacs = 4, /* DAC1 - Output 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .num_adcs = 4, /* ADC1 - Input 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .write = qtet_akm_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .set_rate_val = qtet_akm_set_rate_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .dac_info = qtet_dac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .adc_info = qtet_adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Communication routines with the CPLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Writes data to external register reg, both reg and data are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * GPIO representations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void reg_write(struct snd_ice1712 *ice, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* set direction of used GPIOs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* all outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) tmp = 0x00ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ice->gpio.set_dir(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* mask - writable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ice->gpio.set_mask(ice, ~(tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* write the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) tmp = ice->gpio.get_data(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) tmp &= ~GPIO_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) tmp |= data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ice->gpio.set_data(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* drop output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) tmp &= ~GPIO_EX_GPIOE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ice->gpio.set_data(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* drop the register gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) tmp &= ~reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ice->gpio.set_data(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* raise the register GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tmp |= reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ice->gpio.set_data(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* raise all data gpios */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) tmp |= GPIO_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ice->gpio.set_data(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* mask - immutable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ice->gpio.set_mask(ice, 0xffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* outputs only 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ice->gpio.set_dir(ice, 0x00ff00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static unsigned int get_scr(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct qtet_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return spec->scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static unsigned int get_mcr(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct qtet_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return spec->mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static unsigned int get_cpld(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct qtet_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return spec->cpld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void set_scr(struct snd_ice1712 *ice, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct qtet_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) reg_write(ice, GPIO_SCR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) spec->scr = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static void set_mcr(struct snd_ice1712 *ice, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct qtet_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) reg_write(ice, GPIO_MCR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) spec->mcr = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static void set_cpld(struct snd_ice1712 *ice, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct qtet_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) reg_write(ice, GPIO_CPLD_CSN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) spec->cpld = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static void proc_regs_read(struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct snd_ice1712 *ice = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) char bin_buffer[36];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) snd_iprintf(buffer, "SCR: %s\n", get_binary(bin_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) get_scr(ice)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) snd_iprintf(buffer, "MCR: %s\n", get_binary(bin_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) get_mcr(ice)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) snd_iprintf(buffer, "CPLD: %s\n", get_binary(bin_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) get_cpld(ice)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static void proc_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) snd_card_ro_proc_new(ice->card, "quartet", ice, proc_regs_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int qtet_mute_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) val = get_scr(ice) & SCR_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ucontrol->value.integer.value[0] = (val) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int qtet_mute_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned int old, new, smute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) old = get_scr(ice) & SCR_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (ucontrol->value.integer.value[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* unmute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) new = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* un-smuting DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) smute = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) new = SCR_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* smuting DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) smute = AK4620_SMUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (old != new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct snd_akm4xxx *ak = ice->akm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) set_scr(ice, (get_scr(ice) & ~SCR_MUTE) | new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* set smute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) qtet_akm_set_regs(ak, AK4620_DEEMVOL_REG, AK4620_SMUTE, smute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* no change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int qtet_ain12_enum_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const char * const texts[3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {"Line In 1/2", "Mic", "Mic + Low-cut"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(texts), texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int qtet_ain12_sw_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) unsigned int val, result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) val = get_scr(ice) & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case SCR_AIN12_LINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case SCR_AIN12_MIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) result = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) case SCR_AIN12_LOWCUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) result = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* BUG - no other combinations allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ucontrol->value.integer.value[0] = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int qtet_ain12_sw_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned int old, new, tmp, masked_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) old = new = get_scr(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) masked_old = old & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) tmp = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (tmp == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) tmp = 3; /* binary 10 is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) tmp <<= 4; /* shifting to SCR_AIN12_SEL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (tmp != masked_old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* change requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) switch (tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case SCR_AIN12_LINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) new = old & ~(SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) set_scr(ice, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* turn off relay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) new &= ~SCR_RELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) set_scr(ice, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case SCR_AIN12_MIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* turn on relay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) new = old | SCR_RELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) set_scr(ice, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) new = (new & ~SCR_AIN12_SEL1) | SCR_AIN12_SEL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) set_scr(ice, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case SCR_AIN12_LOWCUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* turn on relay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) new = old | SCR_RELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) set_scr(ice, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) new |= SCR_AIN12_SEL1 | SCR_AIN12_SEL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) set_scr(ice, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* no change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int qtet_php_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* if phantom voltage =48V, phantom on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) val = get_scr(ice) & SCR_PHP_V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ucontrol->value.integer.value[0] = val ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int qtet_php_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) unsigned int old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) old = new = get_scr(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (ucontrol->value.integer.value[0] /* phantom on requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) && (~old & SCR_PHP_V)) /* 0 = voltage 5V */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* is off, turn on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* turn voltage on first, = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) new = old | SCR_PHP_V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) set_scr(ice, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* turn phantom on, = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) new &= ~SCR_PHP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) set_scr(ice, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) } else if (!ucontrol->value.integer.value[0] && (old & SCR_PHP_V)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* phantom off requested and 1 = voltage 48V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* is on, turn off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* turn voltage off first, = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) new = old & ~SCR_PHP_V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) set_scr(ice, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* turn phantom off, = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) new |= SCR_PHP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) set_scr(ice, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (old != new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* no change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define PRIV_SW(xid, xbit, xreg) [xid] = {.bit = xbit,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .set_register = set_##xreg,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .get_register = get_##xreg, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define PRIV_ENUM2(xid, xbit, xreg, xtext1, xtext2) [xid] = {.bit = xbit,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .set_register = set_##xreg,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .get_register = get_##xreg,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .texts = {xtext1, xtext2} }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const struct qtet_kcontrol_private qtet_privates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PRIV_ENUM2(IN12_SEL, CPLD_IN12_SEL, cpld, "An In 1/2", "An In 3/4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) PRIV_ENUM2(IN34_SEL, CPLD_IN34_SEL, cpld, "An In 3/4", "IEC958 In"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PRIV_ENUM2(AIN34_SEL, SCR_AIN34_SEL, scr, "Line In 3/4", "Hi-Z"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PRIV_ENUM2(COAX_OUT, CPLD_COAX_OUT, cpld, "IEC958", "I2S"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PRIV_SW(IN12_MON12, MCR_IN12_MON12, mcr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PRIV_SW(IN12_MON34, MCR_IN12_MON34, mcr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PRIV_SW(IN34_MON12, MCR_IN34_MON12, mcr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PRIV_SW(IN34_MON34, MCR_IN34_MON34, mcr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PRIV_SW(OUT12_MON34, MCR_OUT12_MON34, mcr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PRIV_SW(OUT34_MON12, MCR_OUT34_MON12, mcr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int qtet_enum_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct qtet_kcontrol_private private =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) qtet_privates[kcontrol->private_value];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(private.texts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) private.texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static int qtet_sw_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct qtet_kcontrol_private private =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) qtet_privates[kcontrol->private_value];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ucontrol->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) (private.get_register(ice) & private.bit) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int qtet_sw_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct qtet_kcontrol_private private =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) qtet_privates[kcontrol->private_value];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned int old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) old = private.get_register(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (ucontrol->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) new = old | private.bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) new = old & ~private.bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (old != new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) private.set_register(ice, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* no change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define qtet_sw_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define QTET_CONTROL(xname, xtype, xpriv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {.iface = SNDRV_CTL_ELEM_IFACE_MIXER,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .name = xname,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .info = qtet_##xtype##_info,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .get = qtet_sw_get,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .put = qtet_sw_put,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .private_value = xpriv }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static const struct snd_kcontrol_new qtet_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .name = "Master Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .info = qtet_sw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .get = qtet_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .put = qtet_mute_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .private_value = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .name = "Phantom Power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .info = qtet_sw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .get = qtet_php_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .put = qtet_php_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .private_value = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .name = "Analog In 1/2 Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .info = qtet_ain12_enum_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .get = qtet_ain12_sw_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .put = qtet_ain12_sw_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .private_value = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) QTET_CONTROL("Analog In 3/4 Capture Switch", enum, AIN34_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) QTET_CONTROL("PCM In 1/2 Capture Switch", enum, IN12_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) QTET_CONTROL("PCM In 3/4 Capture Switch", enum, IN34_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) QTET_CONTROL("Coax Output Source", enum, COAX_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) QTET_CONTROL("Analog In 1/2 to Monitor 1/2", sw, IN12_MON12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) QTET_CONTROL("Analog In 1/2 to Monitor 3/4", sw, IN12_MON34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) QTET_CONTROL("Analog In 3/4 to Monitor 1/2", sw, IN34_MON12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) QTET_CONTROL("Analog In 3/4 to Monitor 3/4", sw, IN34_MON34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) QTET_CONTROL("Output 1/2 to Monitor 3/4", sw, OUT12_MON34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) QTET_CONTROL("Output 3/4 to Monitor 1/2", sw, OUT34_MON12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const char * const follower_vols[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PCM_12_PLAYBACK_VOLUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PCM_34_PLAYBACK_VOLUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) DECLARE_TLV_DB_SCALE(qtet_master_db_scale, -6350, 50, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static struct snd_kcontrol *ctl_find(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct snd_ctl_elem_id sid = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) strlcpy(sid.name, name, sizeof(sid.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) sid.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return snd_ctl_find_id(card, &sid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static void add_followers(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct snd_kcontrol *master, const char * const *list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) for (; *list; list++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct snd_kcontrol *follower = ctl_find(card, *list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (follower)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) snd_ctl_add_follower(master, follower);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static int qtet_add_controls(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct qtet_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct snd_kcontrol *vmaster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) err = snd_ice1712_akm4xxx_build_controls(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) for (i = 0; i < ARRAY_SIZE(qtet_controls); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) err = snd_ctl_add(ice->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) snd_ctl_new1(&qtet_controls[i], ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Create virtual master control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) vmaster = snd_ctl_make_virtual_master("Master Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) qtet_master_db_scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (!vmaster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) add_followers(ice->card, vmaster, follower_vols);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) err = snd_ctl_add(ice->card, vmaster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* only capture SPDIF over AK4113 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return snd_ak4113_build(spec->ak4113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ice->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static inline int qtet_is_spdif_master(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* CPLD_SYNC_SEL: 0 = internal, 1 = external (i.e. spdif master) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return (get_cpld(ice) & CPLD_SYNC_SEL) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static unsigned int qtet_get_rate(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) unsigned char result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) result = get_cpld(ice) & CPLD_CKS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) for (i = 0; i < ARRAY_SIZE(cks_vals); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (cks_vals[i] == result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return qtet_rates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static int get_cks_val(int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) for (i = 0; i < ARRAY_SIZE(qtet_rates); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (qtet_rates[i] == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return cks_vals[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* setting new rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static void qtet_set_rate(struct snd_ice1712 *ice, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) unsigned int new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* switching ice1724 to external clock - supplied by ext. circuits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) val = inb(ICEMT1724(ice, RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) new = (get_cpld(ice) & ~CPLD_CKS_MASK) | get_cks_val(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* switch to internal clock, drop CPLD_SYNC_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) new &= ~CPLD_SYNC_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* dev_dbg(ice->card->dev, "QT - set_rate: old %x, new %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) get_cpld(ice), new); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) set_cpld(ice, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static inline unsigned char qtet_set_mclk(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* no change in master clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* setting clock to external - SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static int qtet_set_spdif_clock(struct snd_ice1712 *ice, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) unsigned int old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) old = new = get_cpld(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) new &= ~(CPLD_CKS_MASK | CPLD_WORD_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) case EXT_SPDIF_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) new |= CPLD_EXT_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) case EXT_WORDCLOCK_1FS_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) new |= CPLD_EXT_WORDCLOCK_1FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) case EXT_WORDCLOCK_256FS_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) new |= CPLD_EXT_WORDCLOCK_256FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (old != new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) set_cpld(ice, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int qtet_get_spdif_master_type(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) val = get_cpld(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* checking only rate/clock-related bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) val &= (CPLD_CKS_MASK | CPLD_WORD_SEL | CPLD_SYNC_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (!(val & CPLD_SYNC_SEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* switched to internal clock, is not any external type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) result = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) case (CPLD_EXT_SPDIF):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) result = EXT_SPDIF_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) case (CPLD_EXT_WORDCLOCK_1FS):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) result = EXT_WORDCLOCK_1FS_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case (CPLD_EXT_WORDCLOCK_256FS):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) result = EXT_WORDCLOCK_256FS_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* undefined combination of external clock setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* Called when ak4113 detects change in the input SPDIF stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static void qtet_ak4113_change(struct ak4113 *ak4113, unsigned char c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) unsigned char c1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct snd_ice1712 *ice = ak4113->change_callback_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if ((qtet_get_spdif_master_type(ice) == EXT_SPDIF_TYPE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) c1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* only for SPDIF master mode, rate was changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) rate = snd_ak4113_external_rate(ak4113);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* dev_dbg(ice->card->dev, "ak4113 - input rate changed to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) rate); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) qtet_akm_set_rate_val(ice->akm, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * If clock slaved to SPDIF-IN, setting runtime rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * to the detected external rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static void qtet_spdif_in_open(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct qtet_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (qtet_get_spdif_master_type(ice) != EXT_SPDIF_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* not external SPDIF, no rate limitation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* only external SPDIF can detect incoming sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) rate = snd_ak4113_external_rate(spec->ak4113);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (rate >= runtime->hw.rate_min && rate <= runtime->hw.rate_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) runtime->hw.rate_min = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) runtime->hw.rate_max = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * initialize the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int qtet_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static const unsigned char ak4113_init_vals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* AK4113_REG_PWRDN */ AK4113_RST | AK4113_PWN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) AK4113_OCKS0 | AK4113_OCKS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* AK4113_REQ_FORMAT */ AK4113_DIF_I24I2S | AK4113_VTX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) AK4113_DEM_OFF | AK4113_DEAU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* AK4113_REG_IO0 */ AK4113_OPS2 | AK4113_TXE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) AK4113_XTL_24_576M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* AK4113_REG_IO1 */ AK4113_EFH_1024LRCLK | AK4113_IPS(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* AK4113_REG_INT0_MASK */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* AK4113_REG_INT1_MASK */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* AK4113_REG_DATDTS */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct qtet_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct snd_akm4xxx *ak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* switching ice1724 to external clock - supplied by ext. circuits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) val = inb(ICEMT1724(ice, RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) spec = kzalloc(sizeof(*spec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (!spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* qtet is clocked by Xilinx array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) ice->hw_rates = &qtet_rates_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ice->is_spdif_master = qtet_is_spdif_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ice->get_rate = qtet_get_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ice->set_rate = qtet_set_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ice->set_mclk = qtet_set_mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ice->set_spdif_clock = qtet_set_spdif_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ice->get_spdif_master_type = qtet_get_spdif_master_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ice->ext_clock_names = ext_clock_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* since Qtet can detect correct SPDIF-in rate, all streams can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * limited to this specific rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ice->spdif.ops.open = ice->pro_open = qtet_spdif_in_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ice->spec = spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* Mute Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* SCR Initialize*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* keep codec power down first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) set_scr(ice, SCR_PHP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* codec power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) set_scr(ice, SCR_PHP | SCR_CODEC_PDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* MCR Initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) set_mcr(ice, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* CPLD Initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) set_cpld(ice, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ice->num_total_dacs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ice->num_total_adcs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ice->akm = kcalloc(2, sizeof(struct snd_akm4xxx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ak = ice->akm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (!ak)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* only one codec with two chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ice->akm_codecs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) err = snd_ice1712_akm4xxx_init(ak, &akm_qtet_dac, NULL, ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) err = snd_ak4113_create(ice->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) qtet_ak4113_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) qtet_ak4113_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ak4113_init_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ice, &spec->ak4113);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* callback for codecs rate setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) spec->ak4113->change_callback = qtet_ak4113_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) spec->ak4113->change_callback_private = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /* AK41143 in Quartet can detect external rate correctly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * (i.e. check_flags = 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) spec->ak4113->check_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) proc_init(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) qtet_set_rate(ice, 44100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static const unsigned char qtet_eeprom[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) [ICE_EEP2_SYSCONF] = 0x28, /* clock 256(24MHz), mpu401, 1xADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) 1xDACs, SPDIF in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) [ICE_EEP2_ACLINK] = 0x80, /* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) [ICE_EEP2_I2S] = 0x78, /* 96k, 24bit, 192k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, in, out-ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) [ICE_EEP2_GPIO_DIR] = 0x00, /* 0-7 inputs, switched to output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) only during output operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) [ICE_EEP2_GPIO_DIR1] = 0xff, /* 8-15 outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) [ICE_EEP2_GPIO_DIR2] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) [ICE_EEP2_GPIO_MASK] = 0xff, /* changed only for OUT operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) [ICE_EEP2_GPIO_MASK1] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) [ICE_EEP2_GPIO_MASK2] = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) [ICE_EEP2_GPIO_STATE] = 0x00, /* inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) [ICE_EEP2_GPIO_STATE1] = 0x7d, /* all 1, but GPIO_CPLD_RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) and GPIO15 always zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* entry point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct snd_ice1712_card_info snd_vt1724_qtet_cards[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .subvendor = VT1724_SUBDEVICE_QTET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .name = "Infrasonic Quartet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .model = "quartet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .chip_init = qtet_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .build_controls = qtet_add_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .eeprom_size = sizeof(qtet_eeprom),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .eeprom_data = qtet_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) { } /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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