Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *   ALSA driver for ICEnsemble VT1724 (Envy24HT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *   Lowlevel functions for Philips PSC724 Ultimate Edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "ice1712.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "envy24ht.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "psc724.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "wm8766.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "wm8776.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) struct psc724_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct snd_wm8766 wm8766;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct snd_wm8776 wm8776;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	bool mute_all, jack_detect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	struct snd_ice1712 *ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct delayed_work hp_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	bool hp_connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /*  PHILIPS PSC724 ULTIMATE EDGE                                            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *  VT1722 (Envy24GT) - 6 outputs, 4 inputs (only 2 used), 24-bit/96kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *  system configuration ICE_EEP2_SYSCONF=0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *    XIN1 49.152MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *    no MPU401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *    one stereo ADC, no S/PDIF receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *    three stereo DACs (FRONT, REAR, CENTER+LFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *  AC-Link configuration ICE_EEP2_ACLINK=0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *    use I2S, not AC97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  *  I2S converters feature ICE_EEP2_I2S=0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  *    I2S codec has no volume/mute control feature (bug!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *    I2S codec does not support 96KHz or 192KHz (bug!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  *    I2S codec 24bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  *  S/PDIF configuration ICE_EEP2_SPDIF=0xc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  *    Enable integrated S/PDIF transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  *    internal S/PDIF out implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *    No S/PDIF input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  *    External S/PDIF out implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * ** connected chips **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  *  WM8776
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  *     2-channel DAC used for main output and stereo ADC (with 10-channel MUX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *     AIN1: LINE IN, AIN2: CD/VIDEO, AIN3: AUX, AIN4: Front MIC, AIN5: Rear MIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  *     Controlled by I2C using VT1722 I2C interface:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  *          MODE (pin16) -- GND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  *          CE   (pin17) -- GND  I2C mode (address=0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  *          DI   (pin18) -- SDA  (VT1722 pin70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  *          CL   (pin19) -- SCLK (VT1722 pin71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *  WM8766
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  *      6-channel DAC used for rear & center/LFE outputs (only 4 channels used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *      Controlled by SPI using VT1722 GPIO pins:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  *          MODE   (pin 1) -- GPIO19 (VT1722 pin99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  *          ML/I2S (pin11) -- GPIO18 (VT1722 pin98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  *          MC/IWL (pin12) -- GPIO17 (VT1722 pin97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  *          MD/DM  (pin13) -- GPIO16 (VT1722 pin96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  *          MUTE   (pin14) -- GPIO20 (VT1722 pin101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  *  GPIO14 is used as input for headphone jack detection (1 = connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  *  GPIO22 is used as MUTE ALL output, grounding all 6 channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * ** output pins and device names **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  *   5.1ch name -- output connector color -- device (-D option)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  *      FRONT 2ch                  -- green  -- plughw:0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  *      CENTER(Lch) SUBWOOFER(Rch) -- orange -- plughw:0,2,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  *      REAR 2ch                   -- black  -- plughw:0,2,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* codec access low-level functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define GPIO_HP_JACK	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define GPIO_MUTE_SUR	(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define GPIO_MUTE_ALL	(1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define JACK_INTERVAL	1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define PSC724_SPI_DELAY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define PSC724_SPI_DATA	(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PSC724_SPI_CLK	(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PSC724_SPI_LOAD	(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PSC724_SPI_MASK	(PSC724_SPI_DATA | PSC724_SPI_CLK | PSC724_SPI_LOAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void psc724_wm8766_write(struct snd_wm8766 *wm, u16 addr, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct psc724_spec *spec = container_of(wm, struct psc724_spec, wm8766);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct snd_ice1712 *ice = spec->ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	u32 st, bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	snd_ice1712_save_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	st = ((addr & 0x7f) << 9) | (data & 0x1ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	snd_ice1712_gpio_set_dir(ice, ice->gpio.direction | PSC724_SPI_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask & ~PSC724_SPI_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	bits = snd_ice1712_gpio_read(ice) & ~PSC724_SPI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	snd_ice1712_gpio_write(ice, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		udelay(PSC724_SPI_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		bits &= ~PSC724_SPI_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		/* MSB first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		st <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		if (st & 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			bits |= PSC724_SPI_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			bits &= ~PSC724_SPI_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		snd_ice1712_gpio_write(ice, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		/* CLOCK high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		udelay(PSC724_SPI_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		bits |= PSC724_SPI_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		snd_ice1712_gpio_write(ice, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* LOAD high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	udelay(PSC724_SPI_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	bits |= PSC724_SPI_LOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	snd_ice1712_gpio_write(ice, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* LOAD low, DATA and CLOCK high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	udelay(PSC724_SPI_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	bits |= (PSC724_SPI_DATA | PSC724_SPI_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	snd_ice1712_gpio_write(ice, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	snd_ice1712_restore_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void psc724_wm8776_write(struct snd_wm8776 *wm, u8 addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct psc724_spec *spec = container_of(wm, struct psc724_spec, wm8776);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	snd_vt1724_write_i2c(spec->ice, 0x34, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* mute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void psc724_set_master_switch(struct snd_ice1712 *ice, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	unsigned int bits = snd_ice1712_gpio_read(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct psc724_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	spec->mute_all = !on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		bits &= ~(GPIO_MUTE_ALL | GPIO_MUTE_SUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		bits |= GPIO_MUTE_ALL | GPIO_MUTE_SUR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	snd_ice1712_gpio_write(ice, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static bool psc724_get_master_switch(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct psc724_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	return !spec->mute_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* jack detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void psc724_set_jack_state(struct snd_ice1712 *ice, bool hp_connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct psc724_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct snd_ctl_elem_id elem_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u16 power = spec->wm8776.regs[WM8776_REG_PWRDOWN] & ~WM8776_PWR_HPPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	psc724_set_master_switch(ice, !hp_connected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (!hp_connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		power |= WM8776_PWR_HPPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	snd_wm8776_set_power(&spec->wm8776, power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	spec->hp_connected = hp_connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* notify about master speaker mute change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	memset(&elem_id, 0, sizeof(elem_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	strlcpy(elem_id.name, "Master Speakers Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 						sizeof(elem_id.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	kctl = snd_ctl_find_id(ice->card, &elem_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	snd_ctl_notify(ice->card, SNDRV_CTL_EVENT_MASK_VALUE, &kctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	/* and headphone mute change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	strlcpy(elem_id.name, spec->wm8776.ctl[WM8776_CTL_HP_SW].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 						sizeof(elem_id.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	kctl = snd_ctl_find_id(ice->card, &elem_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	snd_ctl_notify(ice->card, SNDRV_CTL_EVENT_MASK_VALUE, &kctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void psc724_update_hp_jack_state(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct psc724_spec *spec = container_of(work, struct psc724_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 						hp_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct snd_ice1712 *ice = spec->ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	bool hp_connected = snd_ice1712_gpio_read(ice) & GPIO_HP_JACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	schedule_delayed_work(&spec->hp_work, msecs_to_jiffies(JACK_INTERVAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (hp_connected == spec->hp_connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	psc724_set_jack_state(ice, hp_connected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static void psc724_set_jack_detection(struct snd_ice1712 *ice, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct psc724_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (spec->jack_detect == on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	spec->jack_detect = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		bool hp_connected = snd_ice1712_gpio_read(ice) & GPIO_HP_JACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		psc724_set_jack_state(ice, hp_connected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		schedule_delayed_work(&spec->hp_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 					msecs_to_jiffies(JACK_INTERVAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		cancel_delayed_work_sync(&spec->hp_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static bool psc724_get_jack_detection(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct psc724_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	return spec->jack_detect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* mixer controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct psc724_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	void (*set)(struct snd_ice1712 *ice, bool on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	bool (*get)(struct snd_ice1712 *ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct psc724_control psc724_cont[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.name = "Master Speakers Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.set = psc724_set_master_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		.get = psc724_get_master_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		.name = "Headphone Jack Detection Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		.set = psc724_set_jack_detection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		.get = psc724_get_jack_detection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int psc724_ctl_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				  struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	int n = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	ucontrol->value.integer.value[0] = psc724_cont[n].get(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int psc724_ctl_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 				  struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	int n = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	psc724_cont[n].set(ice, ucontrol->value.integer.value[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const char *front_volume	= "Front Playback Volume";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const char *front_switch	= "Front Playback Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const char *front_zc	= "Front Zero Cross Detect Playback Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const char *front_izd	= "Front Infinite Zero Detect Playback Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const char *front_phase	= "Front Phase Invert Playback Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const char *front_deemph	= "Front Deemphasis Playback Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const char *ain1_switch	= "Line Capture Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const char *ain2_switch	= "CD Capture Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const char *ain3_switch	= "AUX Capture Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const char *ain4_switch	= "Front Mic Capture Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const char *ain5_switch	= "Rear Mic Capture Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const char *rear_volume	= "Surround Playback Volume";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const char *clfe_volume	= "CLFE Playback Volume";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const char *rear_switch	= "Surround Playback Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const char *clfe_switch	= "CLFE Playback Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const char *rear_phase	= "Surround Phase Invert Playback Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const char *clfe_phase	= "CLFE Phase Invert Playback Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const char *rear_deemph	= "Surround Deemphasis Playback Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const char *clfe_deemph	= "CLFE Deemphasis Playback Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const char *rear_clfe_izd = "Rear Infinite Zero Detect Playback Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const char *rear_clfe_zc	= "Rear Zero Cross Detect Playback Switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int psc724_add_controls(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct snd_kcontrol_new cont;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct snd_kcontrol *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct psc724_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	spec->wm8776.ctl[WM8776_CTL_DAC_VOL].name = front_volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	spec->wm8776.ctl[WM8776_CTL_DAC_SW].name = front_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	spec->wm8776.ctl[WM8776_CTL_DAC_ZC_SW].name = front_zc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	spec->wm8776.ctl[WM8776_CTL_AUX_SW].name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	spec->wm8776.ctl[WM8776_CTL_DAC_IZD_SW].name = front_izd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	spec->wm8776.ctl[WM8776_CTL_PHASE_SW].name = front_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	spec->wm8776.ctl[WM8776_CTL_DEEMPH_SW].name = front_deemph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	spec->wm8776.ctl[WM8776_CTL_INPUT1_SW].name = ain1_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	spec->wm8776.ctl[WM8776_CTL_INPUT2_SW].name = ain2_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	spec->wm8776.ctl[WM8776_CTL_INPUT3_SW].name = ain3_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	spec->wm8776.ctl[WM8776_CTL_INPUT4_SW].name = ain4_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	spec->wm8776.ctl[WM8776_CTL_INPUT5_SW].name = ain5_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	snd_wm8776_build_controls(&spec->wm8776);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	spec->wm8766.ctl[WM8766_CTL_CH1_VOL].name = rear_volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	spec->wm8766.ctl[WM8766_CTL_CH2_VOL].name = clfe_volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	spec->wm8766.ctl[WM8766_CTL_CH3_VOL].name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	spec->wm8766.ctl[WM8766_CTL_CH1_SW].name = rear_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	spec->wm8766.ctl[WM8766_CTL_CH2_SW].name = clfe_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	spec->wm8766.ctl[WM8766_CTL_CH3_SW].name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	spec->wm8766.ctl[WM8766_CTL_PHASE1_SW].name = rear_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	spec->wm8766.ctl[WM8766_CTL_PHASE2_SW].name = clfe_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	spec->wm8766.ctl[WM8766_CTL_PHASE3_SW].name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	spec->wm8766.ctl[WM8766_CTL_DEEMPH1_SW].name = rear_deemph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	spec->wm8766.ctl[WM8766_CTL_DEEMPH2_SW].name = clfe_deemph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	spec->wm8766.ctl[WM8766_CTL_DEEMPH3_SW].name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	spec->wm8766.ctl[WM8766_CTL_IZD_SW].name = rear_clfe_izd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	spec->wm8766.ctl[WM8766_CTL_ZC_SW].name = rear_clfe_zc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	snd_wm8766_build_controls(&spec->wm8766);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	memset(&cont, 0, sizeof(cont));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	cont.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	for (i = 0; i < ARRAY_SIZE(psc724_cont); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		cont.private_value = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		cont.name = psc724_cont[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		cont.access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		cont.info = snd_ctl_boolean_mono_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		cont.get = psc724_ctl_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		cont.put = psc724_ctl_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		ctl = snd_ctl_new1(&cont, ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		if (!ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		err = snd_ctl_add(ice->card, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void psc724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	struct psc724_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	/* restore codec volume settings after rate change (PMCLK stop) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	snd_wm8776_volume_restore(&spec->wm8776);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	snd_wm8766_volume_restore(&spec->wm8766);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int psc724_resume(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	struct psc724_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	snd_wm8776_resume(&spec->wm8776);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	snd_wm8766_resume(&spec->wm8766);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int psc724_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	struct psc724_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	spec = kzalloc(sizeof(*spec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (!spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	ice->spec = spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	spec->ice = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	ice->num_total_dacs = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	ice->num_total_adcs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	spec->wm8776.ops.write = psc724_wm8776_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	spec->wm8776.card = ice->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	snd_wm8776_init(&spec->wm8776);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	spec->wm8766.ops.write = psc724_wm8766_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	spec->wm8766.card = ice->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	ice->pm_resume = psc724_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	ice->pm_suspend_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	snd_wm8766_init(&spec->wm8766);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	snd_wm8766_set_if(&spec->wm8766,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 			WM8766_IF_FMT_I2S | WM8766_IF_IWL_24BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	ice->gpio.set_pro_rate = psc724_set_pro_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	INIT_DELAYED_WORK(&spec->hp_work, psc724_update_hp_jack_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	psc724_set_jack_detection(ice, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static void psc724_exit(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	struct psc724_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	cancel_delayed_work_sync(&spec->hp_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* PSC724 has buggy EEPROM (no 96&192kHz, all FFh GPIOs), so override it here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const unsigned char psc724_eeprom[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	[ICE_EEP2_SYSCONF]	= 0x42,	/* 49.152MHz, 1 ADC, 3 DACs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	[ICE_EEP2_ACLINK]	= 0x80,	/* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	[ICE_EEP2_I2S]		= 0xf0,	/* I2S volume, 96kHz, 24bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	[ICE_EEP2_SPDIF]	= 0xc1,	/* spdif out-en, out-int, no input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	/* GPIO outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	[ICE_EEP2_GPIO_DIR2]	= 0x5f, /* MUTE_ALL,WM8766 MUTE/MODE/ML/MC/MD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	/* GPIO write enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	[ICE_EEP2_GPIO_MASK]	= 0xff, /* read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	[ICE_EEP2_GPIO_MASK1]	= 0xff, /* read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	[ICE_EEP2_GPIO_MASK2]	= 0xa0, /* MUTE_ALL,WM8766 MUTE/MODE/ML/MC/MD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	/* GPIO initial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	[ICE_EEP2_GPIO_STATE2]	= 0x20,	/* unmuted, all WM8766 pins low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct snd_ice1712_card_info snd_vt1724_psc724_cards[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		.subvendor = VT1724_SUBDEVICE_PSC724,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		.name = "Philips PSC724 Ultimate Edge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		.model = "psc724",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		.chip_init = psc724_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		.chip_exit = psc724_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		.build_controls = psc724_add_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		.eeprom_size = sizeof(psc724_eeprom),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		.eeprom_data = psc724_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	{} /*terminator*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };