^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for ICEnsemble VT1724 (Envy24HT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Lowlevel functions for AudioTrak Prodigy 192 cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Supported IEC958 input from optional MI/ODI/O add-on card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Specifics (SW, HW):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * * 49.5MHz crystal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * * SPDIF-OUT on the card:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - coax (through isolation transformer)/toslink supplied by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 74HC04 gates - 3 in parallel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * - output switched between on-board CD drive dig-out connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * and ice1724 SPDTX pin, using 74HC02 NOR gates, controlled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * by GPIO20 (0 = CD dig-out, 1 = SPDTX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * * SPDTX goes straight to MI/ODI/O card's SPDIF-OUT coax
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * * MI/ODI/O card: AK4114 based, used for iec958 input only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * - toslink input -> RX0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * - coax input -> RX1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * - 4wire protocol:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * AK4114 ICE1724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * ------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * CDTO (pin 32) -- GPIO11 pin 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * CDTI (pin 33) -- GPIO10 pin 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * CCLK (pin 34) -- GPIO9 pin 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * CSN (pin 35) -- GPIO8 pin 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * - output data Mode 7 (24bit, I2S, slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * - both MCKO1 and MCKO2 of ak4114 are fed to FPGA, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * outputs master clock to SPMCLKIN of ice1724.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Experimentally I found out that only a combination of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * OCKS0=1, OCKS1=1 (128fs, 64fs output) and ice1724 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * VT1724_MT_I2S_MCLK_128X=0 (256fs input) yields correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * sampling rate. That means that the FPGA doubles the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * MCK01 rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Copyright (c) 2003 Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Copyright (c) 2003 Dimitromanolakis Apostolos <apostol@cs.utoronto.ca>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Copyright (c) 2004 Kouichi ONO <co2b@ceres.dti.ne.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "ice1712.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "envy24ht.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include "prodigy192.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "stac946x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct prodigy192_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct ak4114 *ak4114;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* rate change needs atomic mute/unmute of all dacs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct mutex mute_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static inline void stac9460_put(struct snd_ice1712 *ice, int reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) snd_vt1724_write_i2c(ice, PRODIGY192_STAC9460_ADDR, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline unsigned char stac9460_get(struct snd_ice1712 *ice, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return snd_vt1724_read_i2c(ice, PRODIGY192_STAC9460_ADDR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * DAC mute control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * idx = STAC9460 volume register number, mute: 0 = mute, 1 = unmute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int stac9460_dac_mute(struct snd_ice1712 *ice, int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned char mute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned char new, old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) old = stac9460_get(ice, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) new = (~mute << 7 & 0x80) | (old & ~0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) change = (new != old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* dev_dbg(ice->card->dev, "Volume register 0x%02x: 0x%02x\n", idx, new);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) stac9460_put(ice, idx, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define stac9460_dac_mute_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int stac9460_dac_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (kcontrol->private_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) idx = STAC946X_MASTER_VOLUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + STAC946X_LF_VOLUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) val = stac9460_get(ice, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ucontrol->value.integer.value[0] = (~val >> 7) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int stac9460_dac_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct prodigy192_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int idx, change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (kcontrol->private_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) idx = STAC946X_MASTER_VOLUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + STAC946X_LF_VOLUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* due to possible conflicts with stac9460_set_rate_val, mutexing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mutex_lock(&spec->mute_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_dbg(ice->card->dev, "Mute put: reg 0x%02x, ctrl value: 0x%02x\n", idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ucontrol->value.integer.value[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) change = stac9460_dac_mute(ice, idx, ucontrol->value.integer.value[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mutex_unlock(&spec->mute_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * DAC volume attenuation mixer control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int stac9460_dac_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) uinfo->value.integer.min = 0; /* mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) uinfo->value.integer.max = 0x7f; /* 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int stac9460_dac_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned char vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (kcontrol->private_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) idx = STAC946X_MASTER_VOLUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + STAC946X_LF_VOLUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) vol = stac9460_get(ice, idx) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ucontrol->value.integer.value[0] = 0x7f - vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int stac9460_dac_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned char tmp, ovol, nvol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (kcontrol->private_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) idx = STAC946X_MASTER_VOLUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + STAC946X_LF_VOLUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) nvol = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) tmp = stac9460_get(ice, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ovol = 0x7f - (tmp & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) change = (ovol != nvol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ovol = (0x7f - nvol) | (tmp & 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_dbg(ice->card->dev, "DAC Volume: reg 0x%02x: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) idx, ovol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) stac9460_put(ice, idx, (0x7f - nvol) | (tmp & 0x80));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * ADC mute control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define stac9460_adc_mute_info snd_ctl_boolean_stereo_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int stac9460_adc_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for (i = 0; i < 2; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) val = stac9460_get(ice, STAC946X_MIC_L_VOLUME + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ucontrol->value.integer.value[i] = ~val>>7 & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int stac9460_adc_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned char new, old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int i, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) for (i = 0; i < 2; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) reg = STAC946X_MIC_L_VOLUME + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) old = stac9460_get(ice, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) new = (~ucontrol->value.integer.value[i]<<7&0x80) | (old&~0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) change = (new != old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) stac9460_put(ice, reg, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * ADC gain mixer control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int stac9460_adc_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) uinfo->value.integer.min = 0; /* 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) uinfo->value.integer.max = 0x0f; /* 22.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int stac9460_adc_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int i, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned char vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) for (i = 0; i < 2; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) reg = STAC946X_MIC_L_VOLUME + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) vol = stac9460_get(ice, reg) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ucontrol->value.integer.value[i] = 0x0f - vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int stac9460_adc_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int i, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned char ovol, nvol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) for (i = 0; i < 2; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) reg = STAC946X_MIC_L_VOLUME + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) nvol = ucontrol->value.integer.value[i] & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ovol = 0x0f - stac9460_get(ice, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) change = ((ovol & 0x0f) != nvol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) stac9460_put(ice, reg, (0x0f - nvol) | (ovol & ~0x0f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int stac9460_mic_sw_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const char * const texts[2] = { "Line In", "Mic" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return snd_ctl_enum_info(uinfo, 1, 2, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int stac9460_mic_sw_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) val = stac9460_get(ice, STAC946X_GENERAL_PURPOSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ucontrol->value.enumerated.item[0] = (val >> 7) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int stac9460_mic_sw_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned char new, old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) old = stac9460_get(ice, STAC946X_GENERAL_PURPOSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) new = (ucontrol->value.enumerated.item[0] << 7 & 0x80) | (old & ~0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) change = (new != old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) stac9460_put(ice, STAC946X_GENERAL_PURPOSE, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Handler for setting correct codec rate - called when rate change is detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void stac9460_set_rate_val(struct snd_ice1712 *ice, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned char old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned char changed[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct prodigy192_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (rate == 0) /* no hint - S/PDIF input is master, simply return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) else if (rate <= 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) new = 0x08; /* 256x, base rate mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) else if (rate <= 96000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) new = 0x11; /* 256x, mid rate mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) new = 0x12; /* 128x, high rate mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) old = stac9460_get(ice, STAC946X_MASTER_CLOCKING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (old == new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* change detected, setting master clock, muting first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* due to possible conflicts with mute controls - mutexing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mutex_lock(&spec->mute_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* we have to remember current mute status for each DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) for (idx = 0; idx < 7 ; ++idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) changed[idx] = stac9460_dac_mute(ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) STAC946X_MASTER_VOLUME + idx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*dev_dbg(ice->card->dev, "Rate change: %d, new MC: 0x%02x\n", rate, new);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) stac9460_put(ice, STAC946X_MASTER_CLOCKING, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* unmuting - only originally unmuted dacs -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * i.e. those changed when muting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) for (idx = 0; idx < 7 ; ++idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (changed[idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) stac9460_dac_mute(ice, STAC946X_MASTER_VOLUME + idx, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mutex_unlock(&spec->mute_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const DECLARE_TLV_DB_SCALE(db_scale_dac, -19125, 75, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const DECLARE_TLV_DB_SCALE(db_scale_adc, 0, 150, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * mixers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct snd_kcontrol_new stac_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .name = "Master Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .info = stac9460_dac_mute_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .get = stac9460_dac_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .put = stac9460_dac_mute_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .private_value = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .tlv = { .p = db_scale_dac }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .name = "Master Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .info = stac9460_dac_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .get = stac9460_dac_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .put = stac9460_dac_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .private_value = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .tlv = { .p = db_scale_dac }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .name = "DAC Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .count = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .info = stac9460_dac_mute_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .get = stac9460_dac_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .put = stac9460_dac_mute_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .name = "DAC Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .count = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .info = stac9460_dac_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .get = stac9460_dac_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .put = stac9460_dac_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .tlv = { .p = db_scale_dac }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .name = "ADC Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .info = stac9460_adc_mute_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .get = stac9460_adc_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .put = stac9460_adc_mute_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .name = "ADC Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .info = stac9460_adc_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .get = stac9460_adc_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .put = stac9460_adc_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .tlv = { .p = db_scale_adc }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .name = "Analog Capture Input",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .info = stac9460_mic_sw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .get = stac9460_mic_sw_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .put = stac9460_mic_sw_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* AK4114 - ICE1724 connections on Prodigy192 + MI/ODI/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* CDTO (pin 32) -- GPIO11 pin 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * CDTI (pin 33) -- GPIO10 pin 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * CCLK (pin 34) -- GPIO9 pin 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * CSN (pin 35) -- GPIO8 pin 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define AK4114_ADDR 0x00 /* C1-C0: Chip Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * (According to datasheet fixed to “00”)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * 4wire ak4114 protocol - writing data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void write_data(struct snd_ice1712 *ice, unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) unsigned int data, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) for (; idx >= 0; idx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* drop clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) gpio &= ~VT1724_PRODIGY192_CCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) snd_ice1712_gpio_write(ice, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* set data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (data & (1 << idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) gpio |= VT1724_PRODIGY192_CDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) gpio &= ~VT1724_PRODIGY192_CDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) snd_ice1712_gpio_write(ice, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* raise clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) gpio |= VT1724_PRODIGY192_CCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) snd_ice1712_gpio_write(ice, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * 4wire ak4114 protocol - reading data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static unsigned char read_data(struct snd_ice1712 *ice, unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned char data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) for (; idx >= 0; idx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* drop clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) gpio &= ~VT1724_PRODIGY192_CCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) snd_ice1712_gpio_write(ice, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* read data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (snd_ice1712_gpio_read(ice) & VT1724_PRODIGY192_CDIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) data |= (1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* raise clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) gpio |= VT1724_PRODIGY192_CCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) snd_ice1712_gpio_write(ice, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * 4wire ak4114 protocol - starting sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static unsigned int prodigy192_4wire_start(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) snd_ice1712_save_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) tmp = snd_ice1712_gpio_read(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) tmp |= VT1724_PRODIGY192_CCLK; /* high at init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) tmp &= ~VT1724_PRODIGY192_CS; /* drop chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) snd_ice1712_gpio_write(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * 4wire ak4114 protocol - final sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void prodigy192_4wire_finish(struct snd_ice1712 *ice, unsigned int tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) tmp |= VT1724_PRODIGY192_CS; /* raise chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) snd_ice1712_gpio_write(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) snd_ice1712_restore_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * Write data to addr register of ak4114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void prodigy192_ak4114_write(void *private_data, unsigned char addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct snd_ice1712 *ice = private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned int tmp, addrdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) tmp = prodigy192_4wire_start(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) addrdata = (AK4114_ADDR << 6) | 0x20 | (addr & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) addrdata = (addrdata << 8) | data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) write_data(ice, tmp, addrdata, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) prodigy192_4wire_finish(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * Read data from addr register of ak4114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static unsigned char prodigy192_ak4114_read(void *private_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned char addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct snd_ice1712 *ice = private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned char data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) tmp = prodigy192_4wire_start(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) write_data(ice, tmp, (AK4114_ADDR << 6) | (addr & 0x1f), 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) data = read_data(ice, tmp, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) prodigy192_4wire_finish(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int ak4114_input_sw_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const char * const texts[2] = { "Toslink", "Coax" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return snd_ctl_enum_info(uinfo, 1, 2, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int ak4114_input_sw_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) val = prodigy192_ak4114_read(ice, AK4114_REG_IO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* AK4114_IPS0 bit = 0 -> RX0 = Toslink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * AK4114_IPS0 bit = 1 -> RX1 = Coax
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ucontrol->value.enumerated.item[0] = (val & AK4114_IPS0) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int ak4114_input_sw_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) unsigned char new, old, itemvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) old = prodigy192_ak4114_read(ice, AK4114_REG_IO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* AK4114_IPS0 could be any bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) itemvalue = (ucontrol->value.enumerated.item[0]) ? 0xff : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) new = (itemvalue & AK4114_IPS0) | (old & ~AK4114_IPS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) change = (new != old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) prodigy192_ak4114_write(ice, AK4114_REG_IO1, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static const struct snd_kcontrol_new ak4114_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .name = "MIODIO IEC958 Capture Input",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .info = ak4114_input_sw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .get = ak4114_input_sw_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .put = ak4114_input_sw_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int prodigy192_ak4114_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const unsigned char ak4114_init_vals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) AK4114_RST | AK4114_PWN | AK4114_OCKS0 | AK4114_OCKS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* ice1724 expects I2S and provides clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * DEM0 disables the deemphasis filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) AK4114_DIF_I24I2S | AK4114_DEM0 ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) AK4114_TX1E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) AK4114_EFH_1024 | AK4114_DIT, /* default input RX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static const unsigned char ak4114_init_txcsb[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 0x41, 0x02, 0x2c, 0x00, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct prodigy192_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) err = snd_ak4114_create(ice->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) prodigy192_ak4114_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) prodigy192_ak4114_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ak4114_init_vals, ak4114_init_txcsb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ice, &spec->ak4114);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* AK4114 in Prodigy192 cannot detect external rate correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * No reason to stop capture stream due to incorrect checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) spec->ak4114->check_flags = AK4114_CHECK_NO_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static void stac9460_proc_regs_read(struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct snd_ice1712 *ice = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* registers 0x0 - 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) for (reg = 0; reg <= 0x15; reg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) val = stac9460_get(ice, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) snd_iprintf(buffer, "0x%02x = 0x%02x\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static void stac9460_proc_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) snd_card_ro_proc_new(ice->card, "stac9460_codec", ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) stac9460_proc_regs_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int prodigy192_add_controls(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct prodigy192_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) for (i = 0; i < ARRAY_SIZE(stac_controls); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) err = snd_ctl_add(ice->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) snd_ctl_new1(&stac_controls[i], ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (spec->ak4114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* ak4114 is connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) for (i = 0; i < ARRAY_SIZE(ak4114_controls); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) err = snd_ctl_add(ice->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) snd_ctl_new1(&ak4114_controls[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) err = snd_ak4114_build(spec->ak4114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) NULL, /* ak4114 in MIO/DI/O handles no IEC958 output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ice->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) stac9460_proc_init(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * check for presence of MI/ODI/O add-on card with digital inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static int prodigy192_miodio_exists(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned char orig_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) const unsigned char test_data = 0xd1; /* random value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned char addr = AK4114_REG_INT0_MASK; /* random SAFE address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int exists = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) orig_value = prodigy192_ak4114_read(ice, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) prodigy192_ak4114_write(ice, addr, test_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (prodigy192_ak4114_read(ice, addr) == test_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* ak4114 seems to communicate, apparently exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* writing back original value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) prodigy192_ak4114_write(ice, addr, orig_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) exists = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return exists;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * initialize the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int prodigy192_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static const unsigned short stac_inits_prodigy[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) STAC946X_RESET, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) STAC946X_MASTER_CLOCKING, 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* STAC946X_MASTER_VOLUME, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) STAC946X_LF_VOLUME, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) STAC946X_RF_VOLUME, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) STAC946X_LR_VOLUME, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) STAC946X_RR_VOLUME, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) STAC946X_CENTER_VOLUME, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) STAC946X_LFE_VOLUME, 0,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) (unsigned short)-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) const unsigned short *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct prodigy192_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* prodigy 192 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ice->num_total_dacs = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ice->num_total_adcs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ice->vt1720 = 0; /* ice1724, e.g. 23 GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) spec = kzalloc(sizeof(*spec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (!spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ice->spec = spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) mutex_init(&spec->mute_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* initialize codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) p = stac_inits_prodigy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) for (; *p != (unsigned short)-1; p += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) stac9460_put(ice, p[0], p[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ice->gpio.set_pro_rate = stac9460_set_rate_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* MI/ODI/O add on card with AK4114 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (prodigy192_miodio_exists(ice)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) err = prodigy192_ak4114_init(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* from this moment if err = 0 then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * spec->ak4114 should not be null
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_dbg(ice->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "AK4114 initialized with status %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_dbg(ice->card->dev, "AK4114 not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * Aureon boards don't provide the EEPROM data except for the vendor IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * hence the driver needs to sets up it properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const unsigned char prodigy71_eeprom[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) [ICE_EEP2_SYSCONF] = 0x6a, /* 49MHz crystal, mpu401,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * spdif-in+ 1 stereo ADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * 3 stereo DACs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) [ICE_EEP2_ACLINK] = 0x80, /* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) [ICE_EEP2_I2S] = 0xf8, /* vol, 96k, 24bit, 192k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) [ICE_EEP2_GPIO_DIR] = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) [ICE_EEP2_GPIO_DIR1] = ~(VT1724_PRODIGY192_CDIN >> 8) ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) [ICE_EEP2_GPIO_DIR2] = 0xbf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) [ICE_EEP2_GPIO_MASK] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) [ICE_EEP2_GPIO_MASK1] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) [ICE_EEP2_GPIO_MASK2] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) [ICE_EEP2_GPIO_STATE] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) [ICE_EEP2_GPIO_STATE1] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) [ICE_EEP2_GPIO_STATE2] = 0x10, /* GPIO20: 0 = CD drive dig. input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * passthrough,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * 1 = SPDIF-OUT from ice1724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* entry point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct snd_ice1712_card_info snd_vt1724_prodigy192_cards[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .subvendor = VT1724_SUBDEVICE_PRODIGY192VE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .name = "Audiotrak Prodigy 192",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .model = "prodigy192",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .chip_init = prodigy192_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .build_controls = prodigy192_add_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .eeprom_size = sizeof(prodigy71_eeprom),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .eeprom_data = prodigy71_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) { } /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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