Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *   ALSA driver for ICEnsemble VT1724 (Envy24HT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *   Lowlevel functions for Pontis MS300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "ice1712.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "envy24ht.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "pontis.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* I2C addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define WM_DEV		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CS_DEV		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* WM8776 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define WM_HP_ATTEN_L		0x00	/* headphone left attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define WM_HP_ATTEN_R		0x01	/* headphone left attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define WM_HP_MASTER		0x02	/* headphone master (both channels) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 					/* override LLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define WM_DAC_ATTEN_L		0x03	/* digital left attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define WM_DAC_ATTEN_R		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define WM_DAC_MASTER		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define WM_PHASE_SWAP		0x06	/* DAC phase swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define WM_DAC_CTRL1		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define WM_DAC_MUTE		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define WM_DAC_CTRL2		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define WM_DAC_INT		0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define WM_ADC_INT		0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define WM_MASTER_CTRL		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define WM_POWERDOWN		0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define WM_ADC_ATTEN_L		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define WM_ADC_ATTEN_R		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define WM_ALC_CTRL1		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define WM_ALC_CTRL2		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define WM_ALC_CTRL3		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define WM_NOISE_GATE		0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define WM_LIMITER		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define WM_ADC_MUX		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define WM_OUT_MUX		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define WM_RESET		0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PONTIS_CS_CS		(1<<4)	/* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PONTIS_CS_CLK		(1<<5)	/* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PONTIS_CS_RDATA		(1<<6)	/* CS8416 -> VT1720 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PONTIS_CS_WDATA		(1<<7)	/* VT1720 -> CS8416 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * get the current register value of WM codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	reg <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	return ((unsigned short)ice->akm[0].images[reg] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		ice->akm[0].images[reg + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * set the register value of WM codec and remember it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	unsigned short cval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	cval = (reg << 9) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	snd_vt1724_write_i2c(ice, WM_DEV, cval >> 8, cval & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	wm_put_nocache(ice, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	reg <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ice->akm[0].images[reg] = val >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ice->akm[0].images[reg + 1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * DAC volume attenuation mixer control (-64dB to 0dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define DAC_0dB	0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define DAC_RES	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define DAC_MIN	(DAC_0dB - DAC_RES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int wm_dac_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	uinfo->value.integer.min = 0;	/* mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	uinfo->value.integer.max = DAC_RES;	/* 0dB, 0.5dB step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int wm_dac_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		val = wm_get(ice, WM_DAC_ATTEN_L + i) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		val = val > DAC_MIN ? (val - DAC_MIN) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		ucontrol->value.integer.value[i] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int wm_dac_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned short oval, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int i, idx, change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		nval = ucontrol->value.integer.value[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		nval = (nval ? (nval + DAC_MIN) : 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		idx = WM_DAC_ATTEN_L + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		oval = wm_get(ice, idx) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		if (oval != nval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			wm_put(ice, idx, nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			wm_put_nocache(ice, idx, nval | 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * ADC gain mixer control (-64dB to 0dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ADC_0dB	0xcf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ADC_RES	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ADC_MIN	(ADC_0dB - ADC_RES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int wm_adc_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	uinfo->value.integer.min = 0;	/* mute (-64dB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	uinfo->value.integer.max = ADC_RES;	/* 0dB, 0.5dB step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int wm_adc_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		val = wm_get(ice, WM_ADC_ATTEN_L + i) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		val = val > ADC_MIN ? (val - ADC_MIN) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		ucontrol->value.integer.value[i] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int wm_adc_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	unsigned short ovol, nvol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	int i, idx, change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		nvol = ucontrol->value.integer.value[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		nvol = nvol ? (nvol + ADC_MIN) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		idx  = WM_ADC_ATTEN_L + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		ovol = wm_get(ice, idx) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		if (ovol != nvol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			wm_put(ice, idx, nvol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * ADC input mux mixer control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define wm_adc_mux_info		snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int wm_adc_mux_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	int bit = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ucontrol->value.integer.value[0] = (wm_get(ice, WM_ADC_MUX) & (1 << bit)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int wm_adc_mux_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	int bit = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	unsigned short oval, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	nval = oval = wm_get(ice, WM_ADC_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (ucontrol->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		nval |= (1 << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		nval &= ~(1 << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	change = nval != oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		wm_put(ice, WM_ADC_MUX, nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * Analog bypass (In -> Out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define wm_bypass_info		snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int wm_bypass_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	ucontrol->value.integer.value[0] = (wm_get(ice, WM_OUT_MUX) & 0x04) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int wm_bypass_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	unsigned short val, oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	val = oval = wm_get(ice, WM_OUT_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (ucontrol->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		val |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		val &= ~0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (val != oval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		wm_put(ice, WM_OUT_MUX, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * Left/Right swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define wm_chswap_info		snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int wm_chswap_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL1) & 0xf0) != 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int wm_chswap_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	unsigned short val, oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	oval = wm_get(ice, WM_DAC_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	val = oval & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (ucontrol->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		val |= 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		val |= 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (val != oval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		wm_put(ice, WM_DAC_CTRL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		wm_put_nocache(ice, WM_DAC_CTRL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)  * write data in the SPI mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void set_gpio_bit(struct snd_ice1712 *ice, unsigned int bit, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	unsigned int tmp = snd_ice1712_gpio_read(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		tmp |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		tmp &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	snd_ice1712_gpio_write(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void spi_send_byte(struct snd_ice1712 *ice, unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		set_gpio_bit(ice, PONTIS_CS_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		set_gpio_bit(ice, PONTIS_CS_WDATA, data & 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		set_gpio_bit(ice, PONTIS_CS_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		data <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static unsigned int spi_read_byte(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		val <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		set_gpio_bit(ice, PONTIS_CS_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		if (snd_ice1712_gpio_read(ice) & PONTIS_CS_RDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			val |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		set_gpio_bit(ice, PONTIS_CS_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void spi_write(struct snd_ice1712 *ice, unsigned int dev, unsigned int reg, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	set_gpio_bit(ice, PONTIS_CS_CS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	spi_send_byte(ice, dev & ~1); /* WRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	spi_send_byte(ice, reg); /* MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	spi_send_byte(ice, data); /* DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	/* trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	set_gpio_bit(ice, PONTIS_CS_CS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	/* restore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static unsigned int spi_read(struct snd_ice1712 *ice, unsigned int dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	set_gpio_bit(ice, PONTIS_CS_CS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	spi_send_byte(ice, dev & ~1); /* WRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	spi_send_byte(ice, reg); /* MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	/* trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	set_gpio_bit(ice, PONTIS_CS_CS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	set_gpio_bit(ice, PONTIS_CS_CS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	spi_send_byte(ice, dev | 1); /* READ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	val = spi_read_byte(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	/* trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	set_gpio_bit(ice, PONTIS_CS_CS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	/* restore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)  * SPDIF input source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int cs_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	static const char * const texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		"Coax",		/* RXP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		"Optical",	/* RXP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		"CD",		/* RXP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	return snd_ctl_enum_info(uinfo, 1, 3, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int cs_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	ucontrol->value.enumerated.item[0] = ice->gpio.saved[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int cs_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	if (ucontrol->value.enumerated.item[0] != ice->gpio.saved[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		ice->gpio.saved[0] = ucontrol->value.enumerated.item[0] & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		val = 0x80 | (ice->gpio.saved[0] << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		spi_write(ice, CS_DEV, 0x04, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)  * GPIO controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int pontis_gpio_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	uinfo->value.integer.max = 0xffff; /* 16bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int pontis_gpio_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	/* 4-7 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	ucontrol->value.integer.value[0] = (~ice->gpio.write_mask & 0xffff) | 0x00f0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int pontis_gpio_mask_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	/* 4-7 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	val = (~ucontrol->value.integer.value[0] & 0xffff) | 0x00f0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	changed = val != ice->gpio.write_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	ice->gpio.write_mask = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int pontis_gpio_dir_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	/* 4-7 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	ucontrol->value.integer.value[0] = ice->gpio.direction & 0xff0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int pontis_gpio_dir_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	/* 4-7 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	val = ucontrol->value.integer.value[0] & 0xff0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	changed = (val != ice->gpio.direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	ice->gpio.direction = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int pontis_gpio_data_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	ucontrol->value.integer.value[0] = snd_ice1712_gpio_read(ice) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int pontis_gpio_data_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	unsigned int val, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	int changed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	val = snd_ice1712_gpio_read(ice) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	nval = ucontrol->value.integer.value[0] & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	if (val != nval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		snd_ice1712_gpio_write(ice, nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 		changed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const DECLARE_TLV_DB_SCALE(db_scale_volume, -6400, 50, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)  * mixers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const struct snd_kcontrol_new pontis_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 			   SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 		.name = "PCM Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		.info = wm_dac_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 		.get = wm_dac_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		.put = wm_dac_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 		.tlv = { .p = db_scale_volume },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 			   SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 		.name = "Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 		.info = wm_adc_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		.get = wm_adc_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 		.put = wm_adc_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 		.tlv = { .p = db_scale_volume },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 		.name = "CD Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 		.info = wm_adc_mux_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 		.get = wm_adc_mux_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 		.put = wm_adc_mux_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 		.private_value = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 		.name = "Line Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 		.info = wm_adc_mux_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 		.get = wm_adc_mux_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 		.put = wm_adc_mux_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 		.private_value = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		.name = "Analog Bypass Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 		.info = wm_bypass_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 		.get = wm_bypass_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 		.put = wm_bypass_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 		.name = "Swap Output Channels",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 		.info = wm_chswap_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 		.get = wm_chswap_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 		.put = wm_chswap_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 		.name = "IEC958 Input Source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 		.info = cs_source_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 		.get = cs_source_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 		.put = cs_source_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	/* FIXME: which interface? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 		.iface = SNDRV_CTL_ELEM_IFACE_CARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 		.name = "GPIO Mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 		.info = pontis_gpio_mask_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 		.get = pontis_gpio_mask_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 		.put = pontis_gpio_mask_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 		.iface = SNDRV_CTL_ELEM_IFACE_CARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 		.name = "GPIO Direction",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 		.info = pontis_gpio_mask_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 		.get = pontis_gpio_dir_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 		.put = pontis_gpio_dir_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 		.iface = SNDRV_CTL_ELEM_IFACE_CARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 		.name = "GPIO Data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 		.info = pontis_gpio_mask_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 		.get = pontis_gpio_data_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 		.put = pontis_gpio_data_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)  * WM codec registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static void wm_proc_regs_write(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	struct snd_ice1712 *ice = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	char line[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	unsigned int reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	while (!snd_info_get_line(buffer, line, sizeof(line))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 		if (sscanf(line, "%x %x", &reg, &val) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 		if (reg <= 0x17 && val <= 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 			wm_put(ice, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static void wm_proc_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	struct snd_ice1712 *ice = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 	int reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 	for (reg = 0; reg <= 0x17; reg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 		val = wm_get(ice, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 		snd_iprintf(buffer, "%02x = %04x\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static void wm_proc_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 	snd_card_rw_proc_new(ice->card, "wm_codec", ice, wm_proc_regs_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 			     wm_proc_regs_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static void cs_proc_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 	struct snd_ice1712 *ice = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 	int reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 	mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 	for (reg = 0; reg <= 0x26; reg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 		val = spi_read(ice, CS_DEV, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 		snd_iprintf(buffer, "%02x = %02x\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 	val = spi_read(ice, CS_DEV, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 	snd_iprintf(buffer, "%02x = %02x\n", 0x7f, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 	mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static void cs_proc_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 	snd_card_ro_proc_new(ice->card, "cs_codec", ice, cs_proc_regs_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int pontis_add_controls(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 	for (i = 0; i < ARRAY_SIZE(pontis_controls); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 		err = snd_ctl_add(ice->card, snd_ctl_new1(&pontis_controls[i], ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 	wm_proc_init(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 	cs_proc_init(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)  * initialize the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static int pontis_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 	static const unsigned short wm_inits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 		/* These come first to reduce init pop noise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 		WM_ADC_MUX,	0x00c0,	/* ADC mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 		WM_DAC_MUTE,	0x0001,	/* DAC softmute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 		WM_DAC_CTRL1,	0x0000,	/* DAC mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 		WM_POWERDOWN,	0x0008,	/* All power-up except HP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 		WM_RESET,	0x0000,	/* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 	static const unsigned short wm_inits2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 		WM_MASTER_CTRL,	0x0022,	/* 256fs, slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 		WM_DAC_INT,	0x0022,	/* I2S, normal polarity, 24bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 		WM_ADC_INT,	0x0022,	/* I2S, normal polarity, 24bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 		WM_DAC_CTRL1,	0x0090,	/* DAC L/R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 		WM_OUT_MUX,	0x0001,	/* OUT DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 		WM_HP_ATTEN_L,	0x0179,	/* HP 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 		WM_HP_ATTEN_R,	0x0179,	/* HP 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 		WM_DAC_ATTEN_L,	0x0000,	/* DAC 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 		WM_DAC_ATTEN_L,	0x0100,	/* DAC 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 		WM_DAC_ATTEN_R,	0x0000,	/* DAC 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 		WM_DAC_ATTEN_R,	0x0100,	/* DAC 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 		/* WM_DAC_MASTER,	0x0100, */	/* DAC master muted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 		WM_PHASE_SWAP,	0x0000,	/* phase normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 		WM_DAC_CTRL2,	0x0000,	/* no deemphasis, no ZFLG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 		WM_ADC_ATTEN_L,	0x0000,	/* ADC muted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 		WM_ADC_ATTEN_R,	0x0000,	/* ADC muted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 		WM_ALC_CTRL1,	0x007b,	/* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 		WM_ALC_CTRL2,	0x0000,	/* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 		WM_ALC_CTRL3,	0x0000,	/* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 		WM_NOISE_GATE,	0x0000,	/* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 		WM_DAC_MUTE,	0x0000,	/* DAC unmute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 		WM_ADC_MUX,	0x0003,	/* ADC unmute, both CD/Line On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 	static const unsigned char cs_inits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 		0x04,	0x80,	/* RUN, RXP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 		0x05,	0x05,	/* slave, 24bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 		0x01,	0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 		0x02,	0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 		0x03,	0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 	ice->vt1720 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 	ice->num_total_dacs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 	ice->num_total_adcs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 	/* to remember the register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 	ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 	if (! ice->akm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 	ice->akm_codecs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 	/* HACK - use this as the SPDIF source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 	 * don't call snd_ice1712_gpio_get/put(), otherwise it's overwritten
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 	ice->gpio.saved[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 	/* initialize WM8776 codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) 	for (i = 0; i < ARRAY_SIZE(wm_inits); i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 		wm_put(ice, wm_inits[i], wm_inits[i+1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 	schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 	for (i = 0; i < ARRAY_SIZE(wm_inits2); i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 		wm_put(ice, wm_inits2[i], wm_inits2[i+1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 	/* initialize CS8416 codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 	/* assert PRST#; MT05 bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 	outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 	mdelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 	/* deassert PRST# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 	outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 	for (i = 0; i < ARRAY_SIZE(cs_inits); i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 		spi_write(ice, CS_DEV, cs_inits[i], cs_inits[i+1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)  * Pontis boards don't provide the EEPROM data at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)  * hence the driver needs to sets up it properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const unsigned char pontis_eeprom[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 	[ICE_EEP2_SYSCONF]     = 0x08,	/* clock 256, mpu401, spdif-in/ADC, 1DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 	[ICE_EEP2_ACLINK]      = 0x80,	/* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 	[ICE_EEP2_I2S]         = 0xf8,	/* vol, 96k, 24bit, 192k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 	[ICE_EEP2_SPDIF]       = 0xc3,	/* out-en, out-int, spdif-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 	[ICE_EEP2_GPIO_DIR]    = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 	[ICE_EEP2_GPIO_DIR1]   = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 	[ICE_EEP2_GPIO_DIR2]   = 0x00,	/* ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 	[ICE_EEP2_GPIO_MASK]   = 0x0f,	/* 4-7 reserved for CS8416 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 	[ICE_EEP2_GPIO_MASK1]  = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 	[ICE_EEP2_GPIO_MASK2]  = 0x00,	/* ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 	[ICE_EEP2_GPIO_STATE]  = 0x06,	/* 0-low, 1-high, 2-high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) 	[ICE_EEP2_GPIO_STATE1] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 	[ICE_EEP2_GPIO_STATE2] = 0x00,	/* ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* entry point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct snd_ice1712_card_info snd_vt1720_pontis_cards[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 		.subvendor = VT1720_SUBDEVICE_PONTIS_MS300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) 		.name = "Pontis MS300",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 		.model = "ms300",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 		.chip_init = pontis_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) 		.build_controls = pontis_add_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) 		.eeprom_size = sizeof(pontis_eeprom),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 		.eeprom_data = pontis_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 	{ } /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };