Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __SOUND_PHASE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __SOUND_PHASE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *   ALSA driver for ICEnsemble ICE1712 (Envy24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *   Lowlevel functions for Terratec PHASE 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *	Copyright (c) 2005 Misha Zhilin <misha@epiphan.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PHASE_DEVICE_DESC	"{Terratec,Phase 22},"\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 				"{Terratec,Phase 28},"\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 				"{Terrasoniq,TS22},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define VT1724_SUBDEVICE_PHASE22	0x3b155011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define VT1724_SUBDEVICE_PHASE28	0x3b154911
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define VT1724_SUBDEVICE_TS22		0x3b157b11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* entry point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) extern struct snd_ice1712_card_info snd_vt1724_phase_cards[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* PHASE28 GPIO bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PHASE28_SPI_MISO	(1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PHASE28_WM_RESET	(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PHASE28_SPI_CLK		(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PHASE28_SPI_MOSI	(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PHASE28_WM_RW		(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PHASE28_AC97_RESET	(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PHASE28_DIGITAL_SEL1	(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PHASE28_HP_SEL		(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PHASE28_WM_CS		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PHASE28_AC97_COMMIT	(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PHASE28_AC97_ADDR	(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PHASE28_AC97_DATA_LOW	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PHASE28_AC97_DATA_HIGH	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PHASE28_AC97_DATA_MASK	0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif /* __SOUND_PHASE */