^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for ICEnsemble ICE1724 (Envy24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Lowlevel functions for Terratec PHASE 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2005 Misha Zhilin <misha@epiphan.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* PHASE 22 overview:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Audio controller: VIA Envy24HT-S (slightly trimmed down Envy24HT, 4in/4out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Analog chip: AK4524 (partially via Philip's 74HCT125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Digital receiver: CS8414-CS (supported in this release)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * PHASE 22 revision 2.0 and Terrasoniq/Musonik TS22PCI have CS8416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * (support status unknown, please test and report)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Envy connects to AK4524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * - CS directly from GPIO 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * - CCLK via 74HCT125's gate #4 from GPIO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * - CDTI via 74HCT125's gate #2 from GPIO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * CDTI may be completely blocked by 74HCT125's gate #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * controlled by GPIO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* PHASE 28 overview:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Audio controller: VIA Envy24HT (full untrimmed version, 4in/8out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Analog chip: WM8770 (8 channel 192k DAC, 2 channel 96k ADC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Digital receiver: CS8414-CS (supported in this release)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "ice1712.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "envy24ht.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "phase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* AC97 register cache for Phase28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct phase28_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned short master[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned short vol[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* WM8770 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define WM_DAC_ATTEN 0x00 /* DAC1-8 analog attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define WM_DAC_MASTER_ATTEN 0x08 /* DAC master analog attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WM_DAC_DIG_ATTEN 0x09 /* DAC1-8 digital attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WM_DAC_DIG_MASTER_ATTEN 0x11 /* DAC master digital attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define WM_PHASE_SWAP 0x12 /* DAC phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WM_DAC_CTRL1 0x13 /* DAC control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define WM_MUTE 0x14 /* mute controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define WM_DAC_CTRL2 0x15 /* de-emphasis and zefo-flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define WM_INT_CTRL 0x16 /* interface control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define WM_MASTER 0x17 /* master clock and mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define WM_POWERDOWN 0x18 /* power-down controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define WM_ADC_GAIN 0x19 /* ADC gain L(19)/R(1a) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define WM_ADC_MUX 0x1b /* input MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define WM_OUT_MUX1 0x1c /* output MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define WM_OUT_MUX2 0x1e /* output MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define WM_RESET 0x1f /* software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Logarithmic volume values for WM8770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Computed as 20 * Log10(255 / x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const unsigned char wm_vol[256] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 127, 48, 42, 39, 36, 34, 33, 31, 30, 29, 28, 27, 27, 26, 25, 25, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 24, 23, 23, 22, 22, 21, 21, 21, 20, 20, 20, 19, 19, 19, 18, 18, 18, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 17, 17, 17, 17, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 14, 14, 14, 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 14, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 11, 11, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define WM_VOL_MAX (sizeof(wm_vol) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define WM_VOL_MUTE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct snd_akm4xxx akm_phase22 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .type = SND_AK4524,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .num_dacs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .num_adcs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct snd_ak4xxx_private akm_phase22_priv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .caddr = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .cif = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .data_mask = 1 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .clk_mask = 1 << 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .cs_mask = 1 << 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .cs_addr = 1 << 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .cs_none = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .add_flags = 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int phase22_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct snd_akm4xxx *ak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Configure DAC/ADC description for generic part of ice1724 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) switch (ice->eeprom.subvendor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case VT1724_SUBDEVICE_PHASE22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case VT1724_SUBDEVICE_TS22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ice->num_total_dacs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ice->num_total_adcs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ice->vt1720 = 1; /* Envy24HT-S have 16 bit wide GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Initialize analog chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ak = ice->akm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!ak)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ice->akm_codecs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) switch (ice->eeprom.subvendor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case VT1724_SUBDEVICE_PHASE22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case VT1724_SUBDEVICE_TS22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) err = snd_ice1712_akm4xxx_init(ak, &akm_phase22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) &akm_phase22_priv, ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int phase22_add_controls(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) switch (ice->eeprom.subvendor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case VT1724_SUBDEVICE_PHASE22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case VT1724_SUBDEVICE_TS22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) err = snd_ice1712_akm4xxx_build_controls(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const unsigned char phase22_eeprom[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [ICE_EEP2_SYSCONF] = 0x28, /* clock 512, mpu 401,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) spdif-in/1xADC, 1xDACs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [ICE_EEP2_ACLINK] = 0x80, /* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [ICE_EEP2_I2S] = 0xf0, /* vol, 96k, 24bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [ICE_EEP2_GPIO_DIR] = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [ICE_EEP2_GPIO_DIR1] = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [ICE_EEP2_GPIO_DIR2] = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [ICE_EEP2_GPIO_MASK] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [ICE_EEP2_GPIO_MASK1] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [ICE_EEP2_GPIO_MASK2] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [ICE_EEP2_GPIO_STATE] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [ICE_EEP2_GPIO_STATE1] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [ICE_EEP2_GPIO_STATE2] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const unsigned char phase28_eeprom[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [ICE_EEP2_SYSCONF] = 0x2b, /* clock 512, mpu401,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) spdif-in/1xADC, 4xDACs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [ICE_EEP2_ACLINK] = 0x80, /* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [ICE_EEP2_I2S] = 0xfc, /* vol, 96k, 24bit, 192k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [ICE_EEP2_GPIO_DIR] = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [ICE_EEP2_GPIO_DIR1] = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [ICE_EEP2_GPIO_DIR2] = 0x5f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [ICE_EEP2_GPIO_MASK] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [ICE_EEP2_GPIO_MASK1] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [ICE_EEP2_GPIO_MASK2] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [ICE_EEP2_GPIO_STATE] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [ICE_EEP2_GPIO_STATE1] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [ICE_EEP2_GPIO_STATE2] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * write data in the SPI mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void phase28_spi_write(struct snd_ice1712 *ice, unsigned int cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int data, int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) tmp = snd_ice1712_gpio_read(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RW|PHASE28_SPI_MOSI|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PHASE28_SPI_CLK|PHASE28_WM_CS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) tmp |= PHASE28_WM_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) tmp &= ~cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) snd_ice1712_gpio_write(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) for (i = bits - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) tmp &= ~PHASE28_SPI_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) snd_ice1712_gpio_write(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (data & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tmp |= PHASE28_SPI_MOSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tmp &= ~PHASE28_SPI_MOSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) snd_ice1712_gpio_write(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) tmp |= PHASE28_SPI_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) snd_ice1712_gpio_write(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) tmp &= ~PHASE28_SPI_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) tmp |= cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) snd_ice1712_gpio_write(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) tmp |= PHASE28_SPI_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) snd_ice1712_gpio_write(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * get the current register value of WM codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) reg <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return ((unsigned short)ice->akm[0].images[reg] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ice->akm[0].images[reg + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * set the register value of WM codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) phase28_spi_write(ice, PHASE28_WM_CS, (reg << 9) | (val & 0x1ff), 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * set the register value of WM codec and remember it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) wm_put_nocache(ice, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) reg <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ice->akm[0].images[reg] = val >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ice->akm[0].images[reg + 1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void wm_set_vol(struct snd_ice1712 *ice, unsigned int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned short vol, unsigned short master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned char nvol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) nvol = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) nvol = 127 - wm_vol[(((vol & ~WM_VOL_MUTE) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) (master & ~WM_VOL_MUTE)) / 127) & WM_VOL_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) wm_put(ice, index, nvol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) wm_put_nocache(ice, index, 0x180 | nvol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * DAC mute control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define wm_pcm_mute_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int wm_pcm_mute_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ucontrol->value.integer.value[0] = (wm_get(ice, WM_MUTE) & 0x10) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int wm_pcm_mute_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned short nval, oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) snd_ice1712_save_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) oval = wm_get(ice, WM_MUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) nval = (oval & ~0x10) | (ucontrol->value.integer.value[0] ? 0 : 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) change = (nval != oval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) wm_put(ice, WM_MUTE, nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) snd_ice1712_restore_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Master volume attenuation mixer control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int wm_master_vol_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) uinfo->value.integer.max = WM_VOL_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int wm_master_vol_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct phase28_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) for (i = 0; i < 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ucontrol->value.integer.value[i] = spec->master[i] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ~WM_VOL_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int wm_master_vol_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct phase28_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int ch, change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) snd_ice1712_save_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) for (ch = 0; ch < 2; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned int vol = ucontrol->value.integer.value[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (vol > WM_VOL_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) vol |= spec->master[ch] & WM_VOL_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (vol != spec->master[ch]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int dac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) spec->master[ch] = vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (dac = 0; dac < ice->num_total_dacs; dac += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) wm_set_vol(ice, WM_DAC_ATTEN + dac + ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) spec->vol[dac + ch],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) spec->master[ch]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) snd_ice1712_restore_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int phase28_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const unsigned short wm_inits_phase28[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* These come first to reduce init pop noise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 0x1b, 0x044, /* ADC Mux (AC'97 source) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 0x1c, 0x00B, /* Out Mux1 (VOUT1 = DAC+AUX, VOUT2 = DAC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0x1d, 0x009, /* Out Mux2 (VOUT2 = DAC, VOUT3 = DAC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 0x18, 0x000, /* All power-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 0x16, 0x122, /* I2S, normal polarity, 24bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0x17, 0x022, /* 256fs, slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 0x00, 0, /* DAC1 analog mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 0x01, 0, /* DAC2 analog mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0x02, 0, /* DAC3 analog mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 0x03, 0, /* DAC4 analog mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0x04, 0, /* DAC5 analog mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 0x05, 0, /* DAC6 analog mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0x06, 0, /* DAC7 analog mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 0x07, 0, /* DAC8 analog mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0x08, 0x100, /* master analog mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 0x09, 0xff, /* DAC1 digital full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 0x0a, 0xff, /* DAC2 digital full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 0x0b, 0xff, /* DAC3 digital full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0x0c, 0xff, /* DAC4 digital full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 0x0d, 0xff, /* DAC5 digital full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 0x0e, 0xff, /* DAC6 digital full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 0x0f, 0xff, /* DAC7 digital full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0x10, 0xff, /* DAC8 digital full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 0x11, 0x1ff, /* master digital full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0x12, 0x000, /* phase normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 0x13, 0x090, /* unmute DAC L/R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0x14, 0x000, /* all unmute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 0x15, 0x000, /* no deemphasis, no ZFLG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 0x19, 0x000, /* -12dB ADC/L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 0x1a, 0x000, /* -12dB ADC/R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) (unsigned short)-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct snd_akm4xxx *ak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct phase28_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) const unsigned short *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ice->num_total_dacs = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ice->num_total_adcs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) spec = kzalloc(sizeof(*spec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ice->spec = spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* Initialize analog chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ak = ice->akm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!ak)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ice->akm_codecs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) snd_ice1712_gpio_set_dir(ice, 0x5fffff); /* fix this for time being */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* reset the wm codec as the SPI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) snd_ice1712_save_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RESET|PHASE28_WM_CS|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PHASE28_HP_SEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) tmp = snd_ice1712_gpio_read(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) tmp &= ~PHASE28_WM_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) snd_ice1712_gpio_write(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) tmp |= PHASE28_WM_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) snd_ice1712_gpio_write(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) tmp |= PHASE28_WM_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) snd_ice1712_gpio_write(ice, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) p = wm_inits_phase28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (; *p != (unsigned short)-1; p += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) wm_put(ice, p[0], p[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) snd_ice1712_restore_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) spec->master[0] = WM_VOL_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) spec->master[1] = WM_VOL_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) for (i = 0; i < ice->num_total_dacs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) spec->vol[i] = WM_VOL_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) wm_set_vol(ice, i, spec->vol[i], spec->master[i % 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * DAC volume attenuation mixer control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int wm_vol_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int voices = kcontrol->private_value >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uinfo->count = voices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) uinfo->value.integer.min = 0; /* mute (-101dB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) uinfo->value.integer.max = 0x7F; /* 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int wm_vol_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct phase28_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int i, ofs, voices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) voices = kcontrol->private_value >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ofs = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) for (i = 0; i < voices; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ucontrol->value.integer.value[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) spec->vol[ofs+i] & ~WM_VOL_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int wm_vol_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct phase28_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int i, idx, ofs, voices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) voices = kcontrol->private_value >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ofs = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) snd_ice1712_save_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) for (i = 0; i < voices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned int vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) vol = ucontrol->value.integer.value[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (vol > 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) vol |= spec->vol[ofs+i] & WM_VOL_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (vol != spec->vol[ofs+i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) spec->vol[ofs+i] = vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) idx = WM_DAC_ATTEN + ofs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) wm_set_vol(ice, idx, spec->vol[ofs+i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) spec->master[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) snd_ice1712_restore_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * WM8770 mute control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int wm_mute_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct snd_ctl_elem_info *uinfo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) uinfo->count = kcontrol->private_value >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) uinfo->value.integer.max = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int wm_mute_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct phase28_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int voices, ofs, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) voices = kcontrol->private_value >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ofs = kcontrol->private_value & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) for (i = 0; i < voices; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ucontrol->value.integer.value[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) (spec->vol[ofs+i] & WM_VOL_MUTE) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int wm_mute_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct phase28_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int change = 0, voices, ofs, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) voices = kcontrol->private_value >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ofs = kcontrol->private_value & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) snd_ice1712_save_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) for (i = 0; i < voices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int val = (spec->vol[ofs + i] & WM_VOL_MUTE) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ucontrol->value.integer.value[i] != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) spec->vol[ofs + i] &= ~WM_VOL_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) spec->vol[ofs + i] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ucontrol->value.integer.value[i] ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) WM_VOL_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) wm_set_vol(ice, ofs + i, spec->vol[ofs + i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) spec->master[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) snd_ice1712_restore_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * WM8770 master mute control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define wm_master_mute_info snd_ctl_boolean_stereo_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int wm_master_mute_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct phase28_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ucontrol->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) (spec->master[0] & WM_VOL_MUTE) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ucontrol->value.integer.value[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) (spec->master[1] & WM_VOL_MUTE) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int wm_master_mute_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct phase28_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int change = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) snd_ice1712_save_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) int val = (spec->master[i] & WM_VOL_MUTE) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (ucontrol->value.integer.value[i] != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int dac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) spec->master[i] &= ~WM_VOL_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) spec->master[i] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ucontrol->value.integer.value[i] ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) WM_VOL_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) for (dac = 0; dac < ice->num_total_dacs; dac += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) wm_set_vol(ice, WM_DAC_ATTEN + dac + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) spec->vol[dac + i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) spec->master[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) snd_ice1712_restore_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* digital master volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define PCM_0dB 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define PCM_RES 128 /* -64dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define PCM_MIN (PCM_0dB - PCM_RES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int wm_pcm_vol_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) uinfo->value.integer.min = 0; /* mute (-64dB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) uinfo->value.integer.max = PCM_RES; /* 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int wm_pcm_vol_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) mutex_lock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) val = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) val = val > PCM_MIN ? (val - PCM_MIN) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ucontrol->value.integer.value[0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) mutex_unlock(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static int wm_pcm_vol_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) unsigned short ovol, nvol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) nvol = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (nvol > PCM_RES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) snd_ice1712_save_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) nvol = (nvol ? (nvol + PCM_MIN) : 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ovol = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (ovol != nvol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) wm_put(ice, WM_DAC_DIG_MASTER_ATTEN, nvol); /* prelatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) wm_put_nocache(ice, WM_DAC_DIG_MASTER_ATTEN, nvol | 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) snd_ice1712_restore_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * Deemphasis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define phase28_deemp_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int phase28_deemp_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL2) & 0xf) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static int phase28_deemp_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int temp, temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) temp = wm_get(ice, WM_DAC_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) temp2 = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (ucontrol->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) temp |= 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) temp &= ~0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (temp != temp2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) wm_put(ice, WM_DAC_CTRL2, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * ADC Oversampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int phase28_oversampling_info(struct snd_kcontrol *k,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static const char * const texts[2] = { "128x", "64x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return snd_ctl_enum_info(uinfo, 1, 2, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int phase28_oversampling_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ucontrol->value.enumerated.item[0] = (wm_get(ice, WM_MASTER) & 0x8) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int phase28_oversampling_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int temp, temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) temp = wm_get(ice, WM_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) temp2 = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (ucontrol->value.enumerated.item[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) temp |= 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) temp &= ~0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (temp != temp2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) wm_put(ice, WM_MASTER, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static const DECLARE_TLV_DB_SCALE(db_scale_wm_dac, -12700, 100, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const DECLARE_TLV_DB_SCALE(db_scale_wm_pcm, -6400, 50, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const struct snd_kcontrol_new phase28_dac_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .name = "Master Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .info = wm_master_mute_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .get = wm_master_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .put = wm_master_mute_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .name = "Master Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .info = wm_master_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .get = wm_master_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .put = wm_master_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .tlv = { .p = db_scale_wm_dac }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .name = "Front Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .info = wm_mute_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .get = wm_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .put = wm_mute_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .private_value = (2 << 8) | 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .name = "Front Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .info = wm_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .get = wm_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .put = wm_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .private_value = (2 << 8) | 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .tlv = { .p = db_scale_wm_dac }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .name = "Rear Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .info = wm_mute_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .get = wm_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .put = wm_mute_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .private_value = (2 << 8) | 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .name = "Rear Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .info = wm_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .get = wm_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .put = wm_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .private_value = (2 << 8) | 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .tlv = { .p = db_scale_wm_dac }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .name = "Center Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .info = wm_mute_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .get = wm_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .put = wm_mute_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .private_value = (1 << 8) | 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .name = "Center Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .info = wm_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .get = wm_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .put = wm_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .private_value = (1 << 8) | 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .tlv = { .p = db_scale_wm_dac }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .name = "LFE Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .info = wm_mute_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .get = wm_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .put = wm_mute_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .private_value = (1 << 8) | 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .name = "LFE Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .info = wm_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .get = wm_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .put = wm_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .private_value = (1 << 8) | 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .tlv = { .p = db_scale_wm_dac }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .name = "Side Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .info = wm_mute_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .get = wm_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .put = wm_mute_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .private_value = (2 << 8) | 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .name = "Side Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .info = wm_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .get = wm_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .put = wm_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .private_value = (2 << 8) | 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .tlv = { .p = db_scale_wm_dac }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static const struct snd_kcontrol_new wm_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .name = "PCM Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .info = wm_pcm_mute_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .get = wm_pcm_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .put = wm_pcm_mute_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .name = "PCM Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .info = wm_pcm_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .get = wm_pcm_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .put = wm_pcm_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .tlv = { .p = db_scale_wm_pcm }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .name = "DAC Deemphasis Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .info = phase28_deemp_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .get = phase28_deemp_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .put = phase28_deemp_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .name = "ADC Oversampling",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .info = phase28_oversampling_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .get = phase28_oversampling_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .put = phase28_oversampling_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int phase28_add_controls(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) unsigned int i, counts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) counts = ARRAY_SIZE(phase28_dac_controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) for (i = 0; i < counts; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) err = snd_ctl_add(ice->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) snd_ctl_new1(&phase28_dac_controls[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) for (i = 0; i < ARRAY_SIZE(wm_controls); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) err = snd_ctl_add(ice->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) snd_ctl_new1(&wm_controls[i], ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct snd_ice1712_card_info snd_vt1724_phase_cards[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .subvendor = VT1724_SUBDEVICE_PHASE22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .name = "Terratec PHASE 22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .model = "phase22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .chip_init = phase22_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .build_controls = phase22_add_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .eeprom_size = sizeof(phase22_eeprom),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .eeprom_data = phase22_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .subvendor = VT1724_SUBDEVICE_PHASE28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .name = "Terratec PHASE 28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .model = "phase28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .chip_init = phase28_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .build_controls = phase28_add_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .eeprom_size = sizeof(phase28_eeprom),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .eeprom_data = phase28_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .subvendor = VT1724_SUBDEVICE_TS22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .name = "Terrasoniq TS22 PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .model = "TS22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .chip_init = phase22_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .build_controls = phase22_add_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .eeprom_size = sizeof(phase22_eeprom),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .eeprom_data = phase22_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) { } /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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