^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for ICEnsemble VT1724 (Envy24HT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Lowlevel functions for ESI Juli@ cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2004 Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * 2008 Pavel Hofman <dustin@seznam.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ice1712.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "envy24ht.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "juli.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct juli_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct ak4114 *ak4114;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int analog:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * chip addresses on I2C bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AK4114_ADDR 0x20 /* S/PDIF receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AK4358_ADDR 0x22 /* DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Juli does not use the standard ICE1724 clock scheme. Juli's ice1724 chip is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * supplied by external clock provided by Xilinx array and MK73-1 PLL frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * multiplier. Actual frequency is set by ice1724 GPIOs hooked to the Xilinx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * The clock circuitry is supplied by the two ice1724 crystals. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * arrangement allows to generate independent clock signal for AK4114's input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * rate detection circuit. As a result, Juli, unlike most other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * ice1724+ak4114-based cards, detects spdif input rate correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * This fact is applied in the driver, allowing to modify PCM stream rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * parameter according to the actual input rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Juli uses the remaining three stereo-channels of its DAC to optionally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * monitor analog input, digital input, and digital output. The corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * I2S signals are routed by Xilinx, controlled by GPIOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * The master mute is implemented using output muting transistors (GPIO) in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * combination with smuting the DAC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * The card itself has no HW master volume control, implemented using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * vmaster control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * researching and fixing the input monitors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * GPIO pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPIO_FREQ_MASK (3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GPIO_FREQ_32KHZ (0<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GPIO_FREQ_44KHZ (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GPIO_FREQ_48KHZ (2<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GPIO_MULTI_MASK (3<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GPIO_MULTI_4X (0<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GPIO_MULTI_2X (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GPIO_MULTI_1X (2<<2) /* also external */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GPIO_MULTI_HALF (3<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GPIO_INTERNAL_CLOCK (1<<4) /* 0 = external, 1 = internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GPIO_CLOCK_MASK (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GPIO_ANALOG_PRESENT (1<<5) /* RO only: 0 = present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GPIO_RXMCLK_SEL (1<<7) /* must be 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GPIO_AK5385A_CKS0 (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GPIO_AK5385A_DFS1 (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GPIO_AK5385A_DFS0 (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GPIO_DIGOUT_MONITOR (1<<11) /* 1 = active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GPIO_DIGIN_MONITOR (1<<12) /* 1 = active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GPIO_ANAIN_MONITOR (1<<13) /* 1 = active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GPIO_AK5385A_CKS1 (1<<14) /* must be 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GPIO_MUTE_CONTROL (1<<15) /* output mute, 1 = muted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GPIO_RATE_MASK (GPIO_FREQ_MASK | GPIO_MULTI_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) GPIO_CLOCK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GPIO_AK5385A_MASK (GPIO_AK5385A_CKS0 | GPIO_AK5385A_DFS0 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) GPIO_AK5385A_DFS1 | GPIO_AK5385A_CKS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define JULI_PCM_RATE (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GPIO_RATE_16000 (GPIO_FREQ_32KHZ | GPIO_MULTI_HALF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) GPIO_INTERNAL_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GPIO_RATE_22050 (GPIO_FREQ_44KHZ | GPIO_MULTI_HALF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) GPIO_INTERNAL_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GPIO_RATE_24000 (GPIO_FREQ_48KHZ | GPIO_MULTI_HALF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) GPIO_INTERNAL_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GPIO_RATE_32000 (GPIO_FREQ_32KHZ | GPIO_MULTI_1X | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) GPIO_INTERNAL_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GPIO_RATE_44100 (GPIO_FREQ_44KHZ | GPIO_MULTI_1X | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) GPIO_INTERNAL_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GPIO_RATE_48000 (GPIO_FREQ_48KHZ | GPIO_MULTI_1X | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) GPIO_INTERNAL_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GPIO_RATE_64000 (GPIO_FREQ_32KHZ | GPIO_MULTI_2X | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) GPIO_INTERNAL_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GPIO_RATE_88200 (GPIO_FREQ_44KHZ | GPIO_MULTI_2X | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) GPIO_INTERNAL_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GPIO_RATE_96000 (GPIO_FREQ_48KHZ | GPIO_MULTI_2X | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) GPIO_INTERNAL_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GPIO_RATE_176400 (GPIO_FREQ_44KHZ | GPIO_MULTI_4X | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) GPIO_INTERNAL_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GPIO_RATE_192000 (GPIO_FREQ_48KHZ | GPIO_MULTI_4X | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) GPIO_INTERNAL_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Initial setup of the conversion array GPIO <-> rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const unsigned int juli_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 16000, 22050, 24000, 32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 44100, 48000, 64000, 88200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 96000, 176400, 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const unsigned int gpio_vals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) GPIO_RATE_16000, GPIO_RATE_22050, GPIO_RATE_24000, GPIO_RATE_32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) GPIO_RATE_44100, GPIO_RATE_48000, GPIO_RATE_64000, GPIO_RATE_88200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) GPIO_RATE_96000, GPIO_RATE_176400, GPIO_RATE_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct snd_pcm_hw_constraint_list juli_rates_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .count = ARRAY_SIZE(juli_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .list = juli_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int get_gpio_val(int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for (i = 0; i < ARRAY_SIZE(juli_rates); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (juli_rates[i] == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return gpio_vals[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void juli_ak4114_write(void *private_data, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) snd_vt1724_write_i2c((struct snd_ice1712 *)private_data, AK4114_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static unsigned char juli_ak4114_read(void *private_data, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return snd_vt1724_read_i2c((struct snd_ice1712 *)private_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) AK4114_ADDR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * If SPDIF capture and slaved to SPDIF-IN, setting runtime rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * to the external rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void juli_spdif_in_open(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct juli_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) !ice->is_spdif_master(ice))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rate = snd_ak4114_external_rate(spec->ak4114);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (rate >= runtime->hw.rate_min && rate <= runtime->hw.rate_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) runtime->hw.rate_min = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) runtime->hw.rate_max = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * AK4358 section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void juli_akm_lock(struct snd_akm4xxx *ak, int chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void juli_akm_unlock(struct snd_akm4xxx *ak, int chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void juli_akm_write(struct snd_akm4xxx *ak, int chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned char addr, unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct snd_ice1712 *ice = ak->private_data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (snd_BUG_ON(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) snd_vt1724_write_i2c(ice, AK4358_ADDR, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * change the rate of envy24HT, AK4358, AK5385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void juli_akm_set_rate_val(struct snd_akm4xxx *ak, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned char old, tmp, ak4358_dfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int ak5385_pins, old_gpio, new_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct snd_ice1712 *ice = ak->private_data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct juli_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (rate == 0) /* no hint - S/PDIF input is master or the new spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) input rate undetected, simply return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* adjust DFS on codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (rate > 96000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ak4358_dfs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ak5385_pins = GPIO_AK5385A_DFS1 | GPIO_AK5385A_CKS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) } else if (rate > 48000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ak4358_dfs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ak5385_pins = GPIO_AK5385A_DFS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ak4358_dfs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ak5385_pins = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* AK5385 first, since it requires cold reset affecting both codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) old_gpio = ice->gpio.get_data(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) new_gpio = (old_gpio & ~GPIO_AK5385A_MASK) | ak5385_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* dev_dbg(ice->card->dev, "JULI - ak5385 set_rate_val: new gpio 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) new_gpio); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ice->gpio.set_data(ice, new_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* cold reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) old = inb(ICEMT1724(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) outb(old | VT1724_AC97_COLD, ICEMT1724(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) outb(old & ~VT1724_AC97_COLD, ICEMT1724(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* AK4358 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* set new value, reset DFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) tmp = snd_akm4xxx_get(ak, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) snd_akm4xxx_reset(ak, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tmp = snd_akm4xxx_get(ak, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) tmp &= ~(0x03 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) tmp |= ak4358_dfs << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) snd_akm4xxx_set(ak, 0, 2, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) snd_akm4xxx_reset(ak, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* reinit ak4114 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) snd_ak4114_reinit(spec->ak4114);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define AK_DAC(xname, xch) { .name = xname, .num_channels = xch }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define PCM_VOLUME "PCM Playback Volume"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MONITOR_AN_IN_VOLUME "Monitor Analog In Volume"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MONITOR_DIG_IN_VOLUME "Monitor Digital In Volume"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MONITOR_DIG_OUT_VOLUME "Monitor Digital Out Volume"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct snd_akm4xxx_dac_channel juli_dac[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) AK_DAC(PCM_VOLUME, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) AK_DAC(MONITOR_AN_IN_VOLUME, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) AK_DAC(MONITOR_DIG_OUT_VOLUME, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) AK_DAC(MONITOR_DIG_IN_VOLUME, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const struct snd_akm4xxx akm_juli_dac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .type = SND_AK4358,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .num_dacs = 8, /* DAC1 - analog out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) DAC2 - analog in monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) DAC3 - digital out monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DAC4 - digital in monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .lock = juli_akm_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .unlock = juli_akm_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .write = juli_akm_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .set_rate_val = juli_akm_set_rate_val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .dac_info = juli_dac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define juli_mute_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int juli_mute_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) val = ice->gpio.get_data(ice) & (unsigned int) kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (kcontrol->private_value == GPIO_MUTE_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* val 0 = signal on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ucontrol->value.integer.value[0] = (val) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* val 1 = signal on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ucontrol->value.integer.value[0] = (val) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int juli_mute_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned int old_gpio, new_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) old_gpio = ice->gpio.get_data(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ucontrol->value.integer.value[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* unmute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (kcontrol->private_value == GPIO_MUTE_CONTROL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* 0 = signal on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) new_gpio = old_gpio & ~GPIO_MUTE_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* un-smuting DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) snd_akm4xxx_write(ice->akm, 0, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* 1 = signal on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) new_gpio = old_gpio |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) (unsigned int) kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (kcontrol->private_value == GPIO_MUTE_CONTROL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* 1 = signal off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) new_gpio = old_gpio | GPIO_MUTE_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* smuting DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) snd_akm4xxx_write(ice->akm, 0, 0x01, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* 0 = signal off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) new_gpio = old_gpio &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ~((unsigned int) kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* dev_dbg(ice->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) "JULI - mute/unmute: control_value: 0x%x, old_gpio: 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "new_gpio 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) (unsigned int)ucontrol->value.integer.value[0], old_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) new_gpio); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (old_gpio != new_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ice->gpio.set_data(ice, new_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* no change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct snd_kcontrol_new juli_mute_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .name = "Master Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .info = juli_mute_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .get = juli_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .put = juli_mute_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .private_value = GPIO_MUTE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Although the following functionality respects the succint NDA'd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * documentation from the card manufacturer, and the same way of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * operation is coded in OSS Juli driver, only Digital Out monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * seems to work. Surprisingly, Analog input monitor outputs Digital
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * output data. The two are independent, as enabling both doubles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * volume of the monitor sound.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Checking traces on the board suggests the functionality described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * by the manufacturer is correct - I2S from ADC and AK4114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * go to ICE as well as to Xilinx, I2S inputs of DAC2,3,4 (the monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * inputs) are fed from Xilinx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * I even checked traces on board and coded a support in driver for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * an alternative possibility - the unused I2S ICE output channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * switched to HW-IN/SPDIF-IN and providing the monitoring signal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * the DAC - to no avail. The I2S outputs seem to be unconnected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * The windows driver supports the monitoring correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .name = "Monitor Analog In Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .info = juli_mute_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .get = juli_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .put = juli_mute_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .private_value = GPIO_ANAIN_MONITOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .name = "Monitor Digital Out Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .info = juli_mute_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .get = juli_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .put = juli_mute_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .private_value = GPIO_DIGOUT_MONITOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .name = "Monitor Digital In Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .info = juli_mute_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .get = juli_mute_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .put = juli_mute_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .private_value = GPIO_DIGIN_MONITOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const char * const follower_vols[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PCM_VOLUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MONITOR_AN_IN_VOLUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MONITOR_DIG_IN_VOLUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MONITOR_DIG_OUT_VOLUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DECLARE_TLV_DB_SCALE(juli_master_db_scale, -6350, 50, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct snd_kcontrol *ctl_find(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct snd_ctl_elem_id sid = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) strlcpy(sid.name, name, sizeof(sid.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) sid.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return snd_ctl_find_id(card, &sid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static void add_followers(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct snd_kcontrol *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) const char * const *list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) for (; *list; list++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct snd_kcontrol *follower = ctl_find(card, *list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* dev_dbg(card->dev, "add_followers - %s\n", *list); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (follower) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* dev_dbg(card->dev, "follower %s found\n", *list); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) snd_ctl_add_follower(master, follower);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int juli_add_controls(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct juli_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct snd_kcontrol *vmaster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) err = snd_ice1712_akm4xxx_build_controls(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (i = 0; i < ARRAY_SIZE(juli_mute_controls); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) err = snd_ctl_add(ice->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) snd_ctl_new1(&juli_mute_controls[i], ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Create virtual master control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) vmaster = snd_ctl_make_virtual_master("Master Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) juli_master_db_scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!vmaster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) add_followers(ice->card, vmaster, follower_vols);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) err = snd_ctl_add(ice->card, vmaster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* only capture SPDIF over AK4114 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return snd_ak4114_build(spec->ak4114, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ice->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * suspend/resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int juli_resume(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct snd_akm4xxx *ak = ice->akm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct juli_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* akm4358 un-reset, un-mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) snd_akm4xxx_reset(ak, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* reinit ak4114 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) snd_ak4114_resume(spec->ak4114);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int juli_suspend(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct snd_akm4xxx *ak = ice->akm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct juli_spec *spec = ice->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* akm4358 reset and soft-mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) snd_akm4xxx_reset(ak, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) snd_ak4114_suspend(spec->ak4114);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * initialize the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static inline int juli_is_spdif_master(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return (ice->gpio.get_data(ice) & GPIO_INTERNAL_CLOCK) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static unsigned int juli_get_rate(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned char result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) result = ice->gpio.get_data(ice) & GPIO_RATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) for (i = 0; i < ARRAY_SIZE(gpio_vals); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (gpio_vals[i] == result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return juli_rates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* setting new rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void juli_set_rate(struct snd_ice1712 *ice, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned int old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) old = ice->gpio.get_data(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) new = (old & ~GPIO_RATE_MASK) | get_gpio_val(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* dev_dbg(ice->card->dev, "JULI - set_rate: old %x, new %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) old & GPIO_RATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) new & GPIO_RATE_MASK); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ice->gpio.set_data(ice, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* switching to external clock - supplied by external circuits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) val = inb(ICEMT1724(ice, RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static inline unsigned char juli_set_mclk(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* no change in master clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* setting clock to external - SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int juli_set_spdif_clock(struct snd_ice1712 *ice, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) unsigned int old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) old = ice->gpio.get_data(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* external clock (= 0), multiply 1x, 48kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ice->gpio.set_data(ice, (old & ~GPIO_RATE_MASK) | GPIO_MULTI_1X |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) GPIO_FREQ_48KHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* Called when ak4114 detects change in the input SPDIF stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void juli_ak4114_change(struct ak4114 *ak4114, unsigned char c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned char c1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct snd_ice1712 *ice = ak4114->change_callback_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (ice->is_spdif_master(ice) && c1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* only for SPDIF master mode, rate was changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) rate = snd_ak4114_external_rate(ak4114);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* dev_dbg(ice->card->dev, "ak4114 - input rate changed to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) rate); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) juli_akm_set_rate_val(ice->akm, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int juli_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static const unsigned char ak4114_init_vals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* AK4117_REG_PWRDN */ AK4114_RST | AK4114_PWN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) AK4114_OCKS0 | AK4114_OCKS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* AK4114_REQ_FORMAT */ AK4114_DIF_I24I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* AK4114_REG_IO0 */ AK4114_TX1E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* AK4114_REG_IO1 */ AK4114_EFH_1024 | AK4114_DIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) AK4114_IPS(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* AK4114_REG_INT0_MASK */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* AK4114_REG_INT1_MASK */ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static const unsigned char ak4114_init_txcsb[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 0x41, 0x02, 0x2c, 0x00, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct juli_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct snd_akm4xxx *ak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) spec = kzalloc(sizeof(*spec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (!spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ice->spec = spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) err = snd_ak4114_create(ice->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) juli_ak4114_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) juli_ak4114_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ak4114_init_vals, ak4114_init_txcsb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ice, &spec->ak4114);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* callback for codecs rate setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) spec->ak4114->change_callback = juli_ak4114_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) spec->ak4114->change_callback_private = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* AK4114 in Juli can detect external rate correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) spec->ak4114->check_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * it seems that the analog doughter board detection does not work reliably, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * force the analog flag; it should be very rare (if ever) to come at Juli@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * used without the analog daughter board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) spec->analog = (ice->gpio.get_data(ice) & GPIO_ANALOG_PRESENT) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) spec->analog = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (spec->analog) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dev_info(ice->card->dev, "juli@: analog I/O detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ice->num_total_dacs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ice->num_total_adcs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ak = ice->akm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (!ak)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ice->akm_codecs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) err = snd_ice1712_akm4xxx_init(ak, &akm_juli_dac, NULL, ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* juli is clocked by Xilinx array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ice->hw_rates = &juli_rates_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ice->is_spdif_master = juli_is_spdif_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ice->get_rate = juli_get_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ice->set_rate = juli_set_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ice->set_mclk = juli_set_mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ice->set_spdif_clock = juli_set_spdif_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ice->spdif.ops.open = juli_spdif_in_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ice->pm_resume = juli_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ice->pm_suspend = juli_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ice->pm_suspend_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * Juli@ boards don't provide the EEPROM data except for the vendor IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * hence the driver needs to sets up it properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const unsigned char juli_eeprom[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) [ICE_EEP2_SYSCONF] = 0x2b, /* clock 512, mpu401, 1xADC, 1xDACs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) SPDIF in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) [ICE_EEP2_ACLINK] = 0x80, /* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) [ICE_EEP2_I2S] = 0xf8, /* vol, 96k, 24bit, 192k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) [ICE_EEP2_GPIO_DIR] = 0x9f, /* 5, 6:inputs; 7, 4-0 outputs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) [ICE_EEP2_GPIO_DIR1] = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) [ICE_EEP2_GPIO_DIR2] = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) [ICE_EEP2_GPIO_MASK] = 0x60, /* 5, 6: locked; 7, 4-0 writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) [ICE_EEP2_GPIO_MASK1] = 0x00, /* 0-7 writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) [ICE_EEP2_GPIO_MASK2] = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) [ICE_EEP2_GPIO_STATE] = GPIO_FREQ_48KHZ | GPIO_MULTI_1X |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) GPIO_INTERNAL_CLOCK, /* internal clock, multiple 1x, 48kHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) [ICE_EEP2_GPIO_STATE1] = 0x00, /* unmuted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) [ICE_EEP2_GPIO_STATE2] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* entry point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct snd_ice1712_card_info snd_vt1724_juli_cards[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .subvendor = VT1724_SUBDEVICE_JULI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .name = "ESI Juli@",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .model = "juli",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .chip_init = juli_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .build_controls = juli_add_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .eeprom_size = sizeof(juli_eeprom),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .eeprom_data = juli_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) { } /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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