^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for VT1724 ICEnsemble ICE1724 / VIA VT1724 (Envy24HT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * VIA VT1720 (Envy24PT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 2002 James Stafford <jstafford@ampltd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * 2003 Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/rawmidi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "ice1712.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "envy24ht.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* lowlevel routines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "amp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "revo.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "aureon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "vt1720_mobo.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "pontis.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "prodigy192.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "prodigy_hifi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "juli.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "maya44.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "phase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "wtm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "se.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "quartet.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "psc724.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MODULE_DESCRIPTION("VIA ICEnsemble ICE1724/1720 (Envy24HT/PT)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MODULE_SUPPORTED_DEVICE("{"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) REVO_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) AMP_AUDIO2000_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) AUREON_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) VT1720_MOBO_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PONTIS_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PRODIGY192_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PRODIGY_HIFI_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) JULI_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MAYA44_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PHASE_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) WTM_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SE_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) QTET_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "{VIA,VT1720},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "{VIA,VT1724},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "{ICEnsemble,Generic ICE1724},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "{ICEnsemble,Generic Envy24HT}"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "{ICEnsemble,Generic Envy24PT}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static char *model[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MODULE_PARM_DESC(index, "Index value for ICE1724 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MODULE_PARM_DESC(id, "ID string for ICE1724 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MODULE_PARM_DESC(enable, "Enable ICE1724 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) module_param_array(model, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MODULE_PARM_DESC(model, "Use the given board model.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Both VT1720 and VT1724 have the same PCI IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct pci_device_id snd_vt1724_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { PCI_VDEVICE(ICE, PCI_DEVICE_ID_VT1724), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MODULE_DEVICE_TABLE(pci, snd_vt1724_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int PRO_RATE_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int PRO_RATE_RESET = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static unsigned int PRO_RATE_DEFAULT = 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const char * const ext_clock_names[1] = { "IEC958 In" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Basic I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * default rates, default clock routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* check whether the clock mode is spdif-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline int stdclock_is_spdif_master(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * locking rate makes sense only for internal clock mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return (!ice->is_spdif_master(ice)) && PRO_RATE_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * ac97 section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static unsigned char snd_vt1724_ac97_ready(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned char old_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) for (tm = 0; tm < 0x10000; tm++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) old_cmd = inb(ICEMT1724(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (old_cmd & (VT1724_AC97_WRITE | VT1724_AC97_READ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!(old_cmd & VT1724_AC97_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return old_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_dbg(ice->card->dev, "snd_vt1724_ac97_ready: timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return old_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int snd_vt1724_ac97_wait_bit(struct snd_ice1712 *ice, unsigned char bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) for (tm = 0; tm < 0x10000; tm++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if ((inb(ICEMT1724(ice, AC97_CMD)) & bit) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_dbg(ice->card->dev, "snd_vt1724_ac97_wait_bit: timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void snd_vt1724_ac97_write(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned short reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct snd_ice1712 *ice = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned char old_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) old_cmd = snd_vt1724_ac97_ready(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) old_cmd &= ~VT1724_AC97_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) old_cmd |= ac97->num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) outb(reg, ICEMT1724(ice, AC97_INDEX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) outw(val, ICEMT1724(ice, AC97_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) outb(old_cmd | VT1724_AC97_WRITE, ICEMT1724(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static unsigned short snd_vt1724_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct snd_ice1712 *ice = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned char old_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) old_cmd = snd_vt1724_ac97_ready(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) old_cmd &= ~VT1724_AC97_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) old_cmd |= ac97->num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) outb(reg, ICEMT1724(ice, AC97_INDEX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) outb(old_cmd | VT1724_AC97_READ, ICEMT1724(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_READ) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return inw(ICEMT1724(ice, AC97_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * GPIO operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* set gpio direction 0 = read, 1 = write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void snd_vt1724_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) outl(data, ICEREG1724(ice, GPIO_DIRECTION));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) inw(ICEREG1724(ice, GPIO_DIRECTION)); /* dummy read for pci-posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* get gpio direction 0 = read, 1 = write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static unsigned int snd_vt1724_get_gpio_dir(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return inl(ICEREG1724(ice, GPIO_DIRECTION));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* set the gpio mask (0 = writable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void snd_vt1724_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) outw(data, ICEREG1724(ice, GPIO_WRITE_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (!ice->vt1720) /* VT1720 supports only 16 GPIO bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) outb((data >> 16) & 0xff, ICEREG1724(ice, GPIO_WRITE_MASK_22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) inw(ICEREG1724(ice, GPIO_WRITE_MASK)); /* dummy read for pci-posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static unsigned int snd_vt1724_get_gpio_mask(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!ice->vt1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mask = (unsigned int)inb(ICEREG1724(ice, GPIO_WRITE_MASK_22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mask = (mask << 16) | inw(ICEREG1724(ice, GPIO_WRITE_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void snd_vt1724_set_gpio_data(struct snd_ice1712 *ice, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) outw(data, ICEREG1724(ice, GPIO_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!ice->vt1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) outb(data >> 16, ICEREG1724(ice, GPIO_DATA_22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) inw(ICEREG1724(ice, GPIO_DATA)); /* dummy read for pci-posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static unsigned int snd_vt1724_get_gpio_data(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!ice->vt1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) data = (unsigned int)inb(ICEREG1724(ice, GPIO_DATA_22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) data = (data << 16) | inw(ICEREG1724(ice, GPIO_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * MIDI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void vt1724_midi_clear_rx(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) for (count = inb(ICEREG1724(ice, MPU_RXFIFO)); count > 0; --count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) inb(ICEREG1724(ice, MPU_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static inline struct snd_rawmidi_substream *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) get_rawmidi_substream(struct snd_ice1712 *ice, unsigned int stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return list_first_entry(&ice->rmidi[0]->streams[stream].substreams,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct snd_rawmidi_substream, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void vt1724_midi_write(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct snd_rawmidi_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int count, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u8 buffer[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_OUTPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) count = 31 - inb(ICEREG1724(ice, MPU_TXFIFO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) count = snd_rawmidi_transmit(s, buffer, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) for (i = 0; i < count; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) outb(buffer[i], ICEREG1724(ice, MPU_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* mask irq when all bytes have been transmitted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * enabled again in output_trigger when the new data comes in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) enable_midi_irq(ice, VT1724_IRQ_MPU_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) !snd_rawmidi_transmit_empty(s));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void vt1724_midi_read(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct snd_rawmidi_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int count, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u8 buffer[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) count = inb(ICEREG1724(ice, MPU_RXFIFO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) count = min(count, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) for (i = 0; i < count; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) buffer[i] = inb(ICEREG1724(ice, MPU_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) snd_rawmidi_receive(s, buffer, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* call with ice->reg_lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u8 mask = inb(ICEREG1724(ice, IRQMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) mask &= ~flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mask |= flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) outb(mask, ICEREG1724(ice, IRQMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void vt1724_enable_midi_irq(struct snd_rawmidi_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u8 flag, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct snd_ice1712 *ice = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) enable_midi_irq(ice, flag, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int vt1724_midi_output_open(struct snd_rawmidi_substream *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int vt1724_midi_output_close(struct snd_rawmidi_substream *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void vt1724_midi_output_trigger(struct snd_rawmidi_substream *s, int up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct snd_ice1712 *ice = s->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) spin_lock_irqsave(&ice->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ice->midi_output = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) vt1724_midi_write(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ice->midi_output = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) spin_unlock_irqrestore(&ice->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void vt1724_midi_output_drain(struct snd_rawmidi_substream *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct snd_ice1712 *ice = s->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_TX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* 32 bytes should be transmitted in less than about 12 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) timeout = jiffies + msecs_to_jiffies(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (inb(ICEREG1724(ice, MPU_CTRL)) & VT1724_MPU_TX_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) } while (time_after(timeout, jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const struct snd_rawmidi_ops vt1724_midi_output_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .open = vt1724_midi_output_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .close = vt1724_midi_output_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .trigger = vt1724_midi_output_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .drain = vt1724_midi_output_drain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int vt1724_midi_input_open(struct snd_rawmidi_substream *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) vt1724_midi_clear_rx(s->rmidi->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int vt1724_midi_input_close(struct snd_rawmidi_substream *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static void vt1724_midi_input_trigger(struct snd_rawmidi_substream *s, int up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct snd_ice1712 *ice = s->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) spin_lock_irqsave(&ice->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ice->midi_input = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) vt1724_midi_read(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ice->midi_input = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) spin_unlock_irqrestore(&ice->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const struct snd_rawmidi_ops vt1724_midi_input_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .open = vt1724_midi_input_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .close = vt1724_midi_input_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .trigger = vt1724_midi_input_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static irqreturn_t snd_vt1724_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct snd_ice1712 *ice = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned char status_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX | VT1724_IRQ_MTPCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) status = inb(ICEREG1724(ice, IRQSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) status &= status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) spin_lock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (++timeout > 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) status = inb(ICEREG1724(ice, IRQSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_err(ice->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "Too long irq loop, status = 0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (status & VT1724_IRQ_MPU_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_err(ice->card->dev, "Disabling MPU_TX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) spin_unlock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (status & VT1724_IRQ_MPU_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (ice->midi_output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) vt1724_midi_write(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Due to mysterical reasons, MPU_TX is always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * generated (and can't be cleared) when a PCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * playback is going. So let's ignore at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * next loop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) status_mask &= ~VT1724_IRQ_MPU_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (status & VT1724_IRQ_MPU_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (ice->midi_input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) vt1724_midi_read(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) vt1724_midi_clear_rx(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* ack MPU irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) outb(status, ICEREG1724(ice, IRQSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) spin_unlock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (status & VT1724_IRQ_MTPCM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * Multi-track PCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * PCM assignment are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Playback DMA0 (M/C) = playback_pro_substream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * Playback DMA1 = playback_con_substream_ds[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Playback DMA2 = playback_con_substream_ds[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * Playback DMA3 = playback_con_substream_ds[2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * Playback DMA4 (SPDIF) = playback_con_substream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * Record DMA0 = capture_pro_substream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * Record DMA1 = capture_con_substream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned char mtstat = inb(ICEMT1724(ice, IRQ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (mtstat & VT1724_MULTI_PDMA0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ice->playback_pro_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) snd_pcm_period_elapsed(ice->playback_pro_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (mtstat & VT1724_MULTI_RDMA0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ice->capture_pro_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) snd_pcm_period_elapsed(ice->capture_pro_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (mtstat & VT1724_MULTI_PDMA1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ice->playback_con_substream_ds[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) snd_pcm_period_elapsed(ice->playback_con_substream_ds[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (mtstat & VT1724_MULTI_PDMA2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ice->playback_con_substream_ds[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) snd_pcm_period_elapsed(ice->playback_con_substream_ds[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (mtstat & VT1724_MULTI_PDMA3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (ice->playback_con_substream_ds[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) snd_pcm_period_elapsed(ice->playback_con_substream_ds[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (mtstat & VT1724_MULTI_PDMA4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ice->playback_con_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) snd_pcm_period_elapsed(ice->playback_con_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (mtstat & VT1724_MULTI_RDMA1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ice->capture_con_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) snd_pcm_period_elapsed(ice->capture_con_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* ack anyway to avoid freeze */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) outb(mtstat, ICEMT1724(ice, IRQ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* ought to really handle this properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (mtstat & VT1724_MULTI_FIFO_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned char fstat = inb(ICEMT1724(ice, DMA_FIFO_ERR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) outb(fstat, ICEMT1724(ice, DMA_FIFO_ERR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) outb(VT1724_MULTI_FIFO_ERR | inb(ICEMT1724(ice, DMA_INT_MASK)), ICEMT1724(ice, DMA_INT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* If I don't do this, I get machine lockup due to continual interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * PCM code - professional part (multitrack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static const unsigned int rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 8000, 9600, 11025, 12000, 16000, 22050, 24000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 32000, 44100, 48000, 64000, 88200, 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 176400, 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct snd_pcm_hw_constraint_list hw_constraints_rates_96 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .count = ARRAY_SIZE(rates) - 2, /* up to 96000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .list = rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static const struct snd_pcm_hw_constraint_list hw_constraints_rates_48 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .count = ARRAY_SIZE(rates) - 5, /* up to 48000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .list = rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const struct snd_pcm_hw_constraint_list hw_constraints_rates_192 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .count = ARRAY_SIZE(rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .list = rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct vt1724_pcm_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned int addr; /* ADDR register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned int size; /* SIZE register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned int count; /* COUNT register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned int start; /* start & pause bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int snd_vt1724_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned char what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned char old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct snd_pcm_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) what = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (snd_pcm_substream_chip(s) == ice) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) const struct vt1724_pcm_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) reg = s->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) what |= reg->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) spin_lock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) old = inb(ICEMT1724(ice, DMA_PAUSE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) old |= what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) old &= ~what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) outb(old, ICEMT1724(ice, DMA_PAUSE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) spin_unlock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) spin_lock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) old = inb(ICEMT1724(ice, DMA_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (cmd == SNDRV_PCM_TRIGGER_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) old |= what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) old &= ~what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) outb(old, ICEMT1724(ice, DMA_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) spin_unlock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* apps will have to restart stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define DMA_STARTS (VT1724_RDMA0_START|VT1724_PDMA0_START|VT1724_RDMA1_START|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) VT1724_PDMA1_START|VT1724_PDMA2_START|VT1724_PDMA3_START|VT1724_PDMA4_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define DMA_PAUSES (VT1724_RDMA0_PAUSE|VT1724_PDMA0_PAUSE|VT1724_RDMA1_PAUSE|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) VT1724_PDMA1_PAUSE|VT1724_PDMA2_PAUSE|VT1724_PDMA3_PAUSE|VT1724_PDMA4_PAUSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const unsigned int stdclock_rate_list[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 48000, 24000, 12000, 9600, 32000, 16000, 8000, 96000, 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 22050, 11025, 88200, 176400, 0, 192000, 64000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static unsigned int stdclock_get_rate(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return stdclock_rate_list[inb(ICEMT1724(ice, RATE)) & 15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static void stdclock_set_rate(struct snd_ice1712 *ice, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) for (i = 0; i < ARRAY_SIZE(stdclock_rate_list); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (stdclock_rate_list[i] == rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) outb(i, ICEMT1724(ice, RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static unsigned char stdclock_set_mclk(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) unsigned char val, old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* check MT02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) val = old = inb(ICEMT1724(ice, I2S_FORMAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (rate > 96000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) val |= VT1724_MT_I2S_MCLK_128X; /* 128x MCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) val &= ~VT1724_MT_I2S_MCLK_128X; /* 256x MCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (val != old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) outb(val, ICEMT1724(ice, I2S_FORMAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* master clock changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* no change in master clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) unsigned char mclk_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) unsigned int i, old_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) bool call_set_rate = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (rate > ice->hw_rates->list[ice->hw_rates->count - 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) spin_lock_irqsave(&ice->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) (inb(ICEMT1724(ice, DMA_PAUSE)) & DMA_PAUSES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* running? we cannot change the rate now... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) spin_unlock_irqrestore(&ice->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ((rate == ice->cur_rate) && !force) ? 0 : -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (!force && is_pro_rate_locked(ice)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* comparing required and current rate - makes sense for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * internal clock only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) spin_unlock_irqrestore(&ice->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return (rate == ice->cur_rate) ? 0 : -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (force || !ice->is_spdif_master(ice)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* force means the rate was switched by ucontrol, otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * setting clock rate for internal clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) old_rate = ice->get_rate(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (force || (old_rate != rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) call_set_rate = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) else if (rate == ice->cur_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) spin_unlock_irqrestore(&ice->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ice->cur_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) spin_unlock_irqrestore(&ice->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (call_set_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ice->set_rate(ice, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* setting master clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) mclk_change = ice->set_mclk(ice, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (mclk_change && ice->gpio.i2s_mclk_changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ice->gpio.i2s_mclk_changed(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (ice->gpio.set_pro_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ice->gpio.set_pro_rate(ice, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* set up codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) for (i = 0; i < ice->akm_codecs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (ice->akm[i].ops.set_rate_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (ice->spdif.ops.setup_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ice->spdif.ops.setup_rate(ice, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int snd_vt1724_pcm_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int i, chs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) chs = params_channels(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) mutex_lock(&ice->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* mark surround channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (substream == ice->playback_pro_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* PDMA0 can be multi-channel up to 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) chs = chs / 2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) for (i = 0; i < chs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ice->pcm_reserved[i] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ice->pcm_reserved[i] != substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) mutex_unlock(&ice->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ice->pcm_reserved[i] = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) for (; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (ice->pcm_reserved[i] == substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ice->pcm_reserved[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* check individual playback stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (ice->playback_con_substream_ds[i] == substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (ice->pcm_reserved[i] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ice->pcm_reserved[i] != substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) mutex_unlock(&ice->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ice->pcm_reserved[i] = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) mutex_unlock(&ice->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return snd_vt1724_set_pro_rate(ice, params_rate(hw_params), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static int snd_vt1724_pcm_hw_free(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) mutex_lock(&ice->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* unmark surround channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (ice->pcm_reserved[i] == substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ice->pcm_reserved[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) mutex_unlock(&ice->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static int snd_vt1724_playback_pro_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) val = (8 - substream->runtime->channels) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) outb(val, ICEMT1724(ice, BURST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) outl(substream->runtime->dma_addr, ICEMT1724(ice, PLAYBACK_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) size = (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* outl(size, ICEMT1724(ice, PLAYBACK_SIZE)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) outw(size, ICEMT1724(ice, PLAYBACK_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) outb(size >> 16, ICEMT1724(ice, PLAYBACK_SIZE) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* outl(size, ICEMT1724(ice, PLAYBACK_COUNT)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) outw(size, ICEMT1724(ice, PLAYBACK_COUNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) outb(size >> 16, ICEMT1724(ice, PLAYBACK_COUNT) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev_dbg(ice->card->dev, "pro prepare: ch = %d, addr = 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "buffer = 0x%x, period = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) substream->runtime->channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) (unsigned int)substream->runtime->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) snd_pcm_lib_buffer_bytes(substream),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) snd_pcm_lib_period_bytes(substream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static snd_pcm_uframes_t snd_vt1724_playback_pro_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & VT1724_PDMA0_START))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #if 0 /* read PLAYBACK_ADDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ptr = inl(ICEMT1724(ice, PLAYBACK_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (ptr < substream->runtime->dma_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_dbg(ice->card->dev, "invalid negative ptr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ptr -= substream->runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ptr = bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (ptr >= substream->runtime->buffer_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) (int)ptr, (int)substream->runtime->period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #else /* read PLAYBACK_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ptr = inl(ICEMT1724(ice, PLAYBACK_SIZE)) & 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ptr = (ptr + 1) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ptr = bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) else if (ptr <= substream->runtime->buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ptr = substream->runtime->buffer_size - ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) (int)ptr, (int)substream->runtime->buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static int snd_vt1724_pcm_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) outl(substream->runtime->dma_addr, ice->profi_port + reg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) outw((snd_pcm_lib_buffer_bytes(substream) >> 2) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ice->profi_port + reg->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ice->profi_port + reg->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static snd_pcm_uframes_t snd_vt1724_pcm_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & reg->start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #if 0 /* use ADDR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ptr = inl(ice->profi_port + reg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ptr -= substream->runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #else /* use SIZE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ptr = inw(ice->profi_port + reg->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ptr = (ptr + 1) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ptr = bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (!ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) else if (ptr <= substream->runtime->buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ptr = substream->runtime->buffer_size - ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) (int)ptr, (int)substream->runtime->buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static const struct vt1724_pcm_reg vt1724_pdma0_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .addr = VT1724_MT_PLAYBACK_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .size = VT1724_MT_PLAYBACK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .count = VT1724_MT_PLAYBACK_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .start = VT1724_PDMA0_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static const struct vt1724_pcm_reg vt1724_pdma4_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .addr = VT1724_MT_PDMA4_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .size = VT1724_MT_PDMA4_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .count = VT1724_MT_PDMA4_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .start = VT1724_PDMA4_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static const struct vt1724_pcm_reg vt1724_rdma0_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .addr = VT1724_MT_CAPTURE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .size = VT1724_MT_CAPTURE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .count = VT1724_MT_CAPTURE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .start = VT1724_RDMA0_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const struct vt1724_pcm_reg vt1724_rdma1_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .addr = VT1724_MT_RDMA1_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .size = VT1724_MT_RDMA1_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .count = VT1724_MT_RDMA1_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .start = VT1724_RDMA1_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define vt1724_playback_pro_reg vt1724_pdma0_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define vt1724_playback_spdif_reg vt1724_pdma4_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define vt1724_capture_pro_reg vt1724_rdma0_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define vt1724_capture_spdif_reg vt1724_rdma1_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static const struct snd_pcm_hardware snd_vt1724_playback_pro = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .formats = SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .rate_max = 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .buffer_bytes_max = (1UL << 21), /* 19bits dword */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .period_bytes_min = 8 * 4 * 2, /* FIXME: constraints needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .period_bytes_max = (1UL << 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static const struct snd_pcm_hardware snd_vt1724_spdif = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .formats = SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .rates = (SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_44100|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) SNDRV_PCM_RATE_48000|SNDRV_PCM_RATE_88200|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) SNDRV_PCM_RATE_96000|SNDRV_PCM_RATE_176400|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) SNDRV_PCM_RATE_192000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .rate_min = 32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .rate_max = 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .buffer_bytes_max = (1UL << 18), /* 16bits dword */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .period_bytes_min = 2 * 4 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .period_bytes_max = (1UL << 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static const struct snd_pcm_hardware snd_vt1724_2ch_stereo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .formats = SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .rate_max = 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .buffer_bytes_max = (1UL << 18), /* 16bits dword */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .period_bytes_min = 2 * 4 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .period_bytes_max = (1UL << 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * set rate constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static void set_std_hw_rates(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* VT1720 doesn't support more than 96kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if ((ice->eeprom.data[ICE_EEP2_I2S] & 0x08) && !ice->vt1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ice->hw_rates = &hw_constraints_rates_192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ice->hw_rates = &hw_constraints_rates_96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* ACLINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ice->hw_rates = &hw_constraints_rates_48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int set_rate_constraints(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) runtime->hw.rate_min = ice->hw_rates->list[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) runtime->hw.rate_max = ice->hw_rates->list[ice->hw_rates->count - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return snd_pcm_hw_constraint_list(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ice->hw_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* if the card has the internal rate locked (is_pro_locked), limit runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) hw rates to the current internal rate only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static void constrain_rate_if_locked(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (is_pro_rate_locked(ice)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) rate = ice->get_rate(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (rate >= runtime->hw.rate_min
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) && rate <= runtime->hw.rate_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) runtime->hw.rate_min = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) runtime->hw.rate_max = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* multi-channel playback needs alignment 8x32bit regardless of the channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * actually used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define VT1724_BUFFER_ALIGN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int snd_vt1724_playback_pro_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) int chs, num_indeps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) runtime->private_data = (void *)&vt1724_playback_pro_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ice->playback_pro_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) runtime->hw = snd_vt1724_playback_pro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) set_rate_constraints(ice, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) mutex_lock(&ice->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* calculate the currently available channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) num_indeps = ice->num_total_dacs / 2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) for (chs = 0; chs < num_indeps; chs++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (ice->pcm_reserved[chs])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) chs = (chs + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) runtime->hw.channels_max = chs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (chs > 2) /* channels must be even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) mutex_unlock(&ice->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) VT1724_BUFFER_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) VT1724_BUFFER_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) constrain_rate_if_locked(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (ice->pro_open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ice->pro_open(ice, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static int snd_vt1724_capture_pro_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) runtime->private_data = (void *)&vt1724_capture_pro_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ice->capture_pro_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) runtime->hw = snd_vt1724_2ch_stereo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) set_rate_constraints(ice, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) VT1724_BUFFER_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) VT1724_BUFFER_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) constrain_rate_if_locked(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (ice->pro_open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ice->pro_open(ice, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static int snd_vt1724_playback_pro_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (PRO_RATE_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ice->playback_pro_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static int snd_vt1724_capture_pro_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (PRO_RATE_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ice->capture_pro_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static const struct snd_pcm_ops snd_vt1724_playback_pro_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .open = snd_vt1724_playback_pro_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .close = snd_vt1724_playback_pro_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .hw_params = snd_vt1724_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .hw_free = snd_vt1724_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .prepare = snd_vt1724_playback_pro_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .trigger = snd_vt1724_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .pointer = snd_vt1724_playback_pro_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static const struct snd_pcm_ops snd_vt1724_capture_pro_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .open = snd_vt1724_capture_pro_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .close = snd_vt1724_capture_pro_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .hw_params = snd_vt1724_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .hw_free = snd_vt1724_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .prepare = snd_vt1724_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .trigger = snd_vt1724_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .pointer = snd_vt1724_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static int snd_vt1724_pcm_profi(struct snd_ice1712 *ice, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) int capt, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if ((ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_ADC_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) VT1724_CFG_ADC_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) capt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) capt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) err = snd_pcm_new(ice->card, "ICE1724", device, 1, capt, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_vt1724_playback_pro_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (capt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) &snd_vt1724_capture_pro_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) pcm->private_data = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) strcpy(pcm->name, "ICE1724");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) &ice->pci->dev, 256*1024, 256*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ice->pcm_pro = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * SPDIF PCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* update spdif control bits; call with reg_lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static void update_spdif_bits(struct snd_ice1712 *ice, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) unsigned char cbit, disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) cbit = inb(ICEREG1724(ice, SPDIF_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) disabled = cbit & ~VT1724_CFG_SPDIF_OUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (cbit != disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) outb(disabled, ICEREG1724(ice, SPDIF_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) outw(val, ICEMT1724(ice, SPDIF_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (cbit != disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) outb(cbit, ICEREG1724(ice, SPDIF_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) outw(val, ICEMT1724(ice, SPDIF_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /* update SPDIF control bits according to the given rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static void update_spdif_rate(struct snd_ice1712 *ice, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) unsigned int val, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) spin_lock_irqsave(&ice->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) nval = val = inw(ICEMT1724(ice, SPDIF_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) nval &= ~(7 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) case 44100: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) case 48000: nval |= 2 << 12; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) case 32000: nval |= 3 << 12; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) case 88200: nval |= 4 << 12; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) case 96000: nval |= 5 << 12; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) case 192000: nval |= 6 << 12; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) case 176400: nval |= 7 << 12; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (val != nval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) update_spdif_bits(ice, nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) spin_unlock_irqrestore(&ice->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static int snd_vt1724_playback_spdif_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (!ice->force_pdma4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) update_spdif_rate(ice, substream->runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return snd_vt1724_pcm_prepare(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static int snd_vt1724_playback_spdif_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) runtime->private_data = (void *)&vt1724_playback_spdif_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ice->playback_con_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (ice->force_pdma4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) runtime->hw = snd_vt1724_2ch_stereo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) set_rate_constraints(ice, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) runtime->hw = snd_vt1724_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) VT1724_BUFFER_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) VT1724_BUFFER_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) constrain_rate_if_locked(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (ice->spdif.ops.open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ice->spdif.ops.open(ice, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static int snd_vt1724_playback_spdif_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (PRO_RATE_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ice->playback_con_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (ice->spdif.ops.close)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) ice->spdif.ops.close(ice, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static int snd_vt1724_capture_spdif_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) runtime->private_data = (void *)&vt1724_capture_spdif_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ice->capture_con_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (ice->force_rdma1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) runtime->hw = snd_vt1724_2ch_stereo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) set_rate_constraints(ice, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) runtime->hw = snd_vt1724_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) VT1724_BUFFER_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) VT1724_BUFFER_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) constrain_rate_if_locked(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (ice->spdif.ops.open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) ice->spdif.ops.open(ice, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static int snd_vt1724_capture_spdif_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (PRO_RATE_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ice->capture_con_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (ice->spdif.ops.close)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ice->spdif.ops.close(ice, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static const struct snd_pcm_ops snd_vt1724_playback_spdif_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .open = snd_vt1724_playback_spdif_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .close = snd_vt1724_playback_spdif_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .hw_params = snd_vt1724_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .hw_free = snd_vt1724_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .prepare = snd_vt1724_playback_spdif_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .trigger = snd_vt1724_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .pointer = snd_vt1724_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static const struct snd_pcm_ops snd_vt1724_capture_spdif_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .open = snd_vt1724_capture_spdif_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .close = snd_vt1724_capture_spdif_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .hw_params = snd_vt1724_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .hw_free = snd_vt1724_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .prepare = snd_vt1724_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .trigger = snd_vt1724_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .pointer = snd_vt1724_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static int snd_vt1724_pcm_spdif(struct snd_ice1712 *ice, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) int play, capt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (ice->force_pdma4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_OUT_INT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) play = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ice->has_spdif = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) play = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (ice->force_rdma1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) capt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ice->has_spdif = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) capt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (!play && !capt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) return 0; /* no spdif device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (ice->force_pdma4 || ice->force_rdma1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) name = "ICE1724 Secondary";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) name = "ICE1724 IEC958";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) err = snd_pcm_new(ice->card, name, device, play, capt, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (play)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) &snd_vt1724_playback_spdif_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (capt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) &snd_vt1724_capture_spdif_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) pcm->private_data = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) strcpy(pcm->name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) &ice->pci->dev, 256*1024, 256*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ice->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * independent surround PCMs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static const struct vt1724_pcm_reg vt1724_playback_dma_regs[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .addr = VT1724_MT_PDMA1_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .size = VT1724_MT_PDMA1_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .count = VT1724_MT_PDMA1_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .start = VT1724_PDMA1_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .addr = VT1724_MT_PDMA2_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .size = VT1724_MT_PDMA2_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .count = VT1724_MT_PDMA2_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .start = VT1724_PDMA2_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .addr = VT1724_MT_PDMA3_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .size = VT1724_MT_PDMA3_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .count = VT1724_MT_PDMA3_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .start = VT1724_PDMA3_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static int snd_vt1724_playback_indep_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) val = 3 - substream->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (inb(ICEMT1724(ice, BURST)) < val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) outb(val, ICEMT1724(ice, BURST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return snd_vt1724_pcm_prepare(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static int snd_vt1724_playback_indep_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) mutex_lock(&ice->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /* already used by PDMA0? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (ice->pcm_reserved[substream->number]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) mutex_unlock(&ice->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return -EBUSY; /* FIXME: should handle blocking mode properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) mutex_unlock(&ice->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) runtime->private_data = (void *)&vt1724_playback_dma_regs[substream->number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ice->playback_con_substream_ds[substream->number] = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) runtime->hw = snd_vt1724_2ch_stereo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) set_rate_constraints(ice, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static int snd_vt1724_playback_indep_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (PRO_RATE_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) ice->playback_con_substream_ds[substream->number] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) ice->pcm_reserved[substream->number] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) static const struct snd_pcm_ops snd_vt1724_playback_indep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .open = snd_vt1724_playback_indep_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .close = snd_vt1724_playback_indep_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .hw_params = snd_vt1724_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .hw_free = snd_vt1724_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .prepare = snd_vt1724_playback_indep_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .trigger = snd_vt1724_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .pointer = snd_vt1724_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) static int snd_vt1724_pcm_indep(struct snd_ice1712 *ice, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) int play;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) play = ice->num_total_dacs / 2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (play <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) err = snd_pcm_new(ice->card, "ICE1724 Surrounds", device, play, 0, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) &snd_vt1724_playback_indep_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) pcm->private_data = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) strcpy(pcm->name, "ICE1724 Surround PCM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) &ice->pci->dev, 256*1024, 256*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ice->pcm_ds = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * Mixer section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static int snd_vt1724_ac97_mixer(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (!(ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) struct snd_ac97_bus *pbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) struct snd_ac97_template ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static const struct snd_ac97_bus_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .write = snd_vt1724_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .read = snd_vt1724_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /* cold reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) mdelay(5); /* FIXME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) err = snd_ac97_bus(ice->card, 0, &ops, NULL, &pbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ac97.private_data = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) dev_warn(ice->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) "cannot initialize pro ac97, skipped\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* I2S mixer only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) strcat(ice->card->mixername, "ICE1724 - multitrack");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static inline unsigned int eeprom_triple(struct snd_ice1712 *ice, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) return (unsigned int)ice->eeprom.data[idx] | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) ((unsigned int)ice->eeprom.data[idx + 1] << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) ((unsigned int)ice->eeprom.data[idx + 2] << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static void snd_vt1724_proc_read(struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) struct snd_ice1712 *ice = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) snd_iprintf(buffer, "%s\n\n", ice->card->longname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) snd_iprintf(buffer, "EEPROM:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) snd_iprintf(buffer, " System Config : 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) ice->eeprom.data[ICE_EEP2_SYSCONF]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) snd_iprintf(buffer, " ACLink : 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) ice->eeprom.data[ICE_EEP2_ACLINK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) snd_iprintf(buffer, " I2S : 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) ice->eeprom.data[ICE_EEP2_I2S]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) snd_iprintf(buffer, " S/PDIF : 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) ice->eeprom.data[ICE_EEP2_SPDIF]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) snd_iprintf(buffer, " GPIO direction : 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) ice->eeprom.gpiodir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) snd_iprintf(buffer, " GPIO mask : 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) ice->eeprom.gpiomask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) snd_iprintf(buffer, " GPIO state : 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) ice->eeprom.gpiostate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) for (idx = 0x12; idx < ice->eeprom.size; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) snd_iprintf(buffer, " Extra #%02i : 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) idx, ice->eeprom.data[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) snd_iprintf(buffer, "\nRegisters:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) snd_iprintf(buffer, " PSDOUT03 : 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) (unsigned)inl(ICEMT1724(ice, ROUTE_PLAYBACK)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) for (idx = 0x0; idx < 0x20 ; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) snd_iprintf(buffer, " CCS%02x : 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) idx, inb(ice->port+idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) for (idx = 0x0; idx < 0x30 ; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) snd_iprintf(buffer, " MT%02x : 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) idx, inb(ice->profi_port+idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static void snd_vt1724_proc_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) snd_card_ro_proc_new(ice->card, "ice1724", ice, snd_vt1724_proc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static int snd_vt1724_eeprom_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) uinfo->count = sizeof(struct snd_ice1712_eeprom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) static int snd_vt1724_eeprom_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static const struct snd_kcontrol_new snd_vt1724_eeprom = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .iface = SNDRV_CTL_ELEM_IFACE_CARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .name = "ICE1724 EEPROM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .info = snd_vt1724_eeprom_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .get = snd_vt1724_eeprom_get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static int snd_vt1724_spdif_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static unsigned int encode_spdif_bits(struct snd_aes_iec958 *diga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) unsigned int val, rbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) val = diga->status[0] & 0x03; /* professional, non-audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (val & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) /* professional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if ((diga->status[0] & IEC958_AES0_PRO_EMPHASIS) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) IEC958_AES0_PRO_EMPHASIS_5015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) val |= 1U << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) rbits = (diga->status[4] >> 3) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (rbits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) switch (rbits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) case 2: val |= 5 << 12; break; /* 96k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) case 3: val |= 6 << 12; break; /* 192k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) case 10: val |= 4 << 12; break; /* 88.2k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) case 11: val |= 7 << 12; break; /* 176.4k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) switch (diga->status[0] & IEC958_AES0_PRO_FS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) case IEC958_AES0_PRO_FS_44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) case IEC958_AES0_PRO_FS_32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) val |= 3U << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) val |= 2U << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /* consumer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) val |= diga->status[1] & 0x04; /* copyright */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if ((diga->status[0] & IEC958_AES0_CON_EMPHASIS) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) IEC958_AES0_CON_EMPHASIS_5015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) val |= 1U << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) val |= (unsigned int)(diga->status[1] & 0x3f) << 4; /* category */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) val |= (unsigned int)(diga->status[3] & IEC958_AES3_CON_FS) << 12; /* fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static void decode_spdif_bits(struct snd_aes_iec958 *diga, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) memset(diga->status, 0, sizeof(diga->status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) diga->status[0] = val & 0x03; /* professional, non-audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (val & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) /* professional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (val & (1U << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) switch ((val >> 12) & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) diga->status[0] |= IEC958_AES0_PRO_FS_32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) diga->status[0] |= IEC958_AES0_PRO_FS_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) /* consumer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) diga->status[0] |= val & (1U << 2); /* copyright */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (val & (1U << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) diga->status[1] |= (val >> 4) & 0x3f; /* category */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) diga->status[3] |= (val >> 12) & 0x07; /* fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static int snd_vt1724_spdif_default_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) val = inw(ICEMT1724(ice, SPDIF_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) decode_spdif_bits(&ucontrol->value.iec958, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static int snd_vt1724_spdif_default_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) unsigned int val, old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) val = encode_spdif_bits(&ucontrol->value.iec958);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) old = inw(ICEMT1724(ice, SPDIF_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (val != old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) update_spdif_bits(ice, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return val != old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) static const struct snd_kcontrol_new snd_vt1724_spdif_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .info = snd_vt1724_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .get = snd_vt1724_spdif_default_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .put = snd_vt1724_spdif_default_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) static int snd_vt1724_spdif_maskc_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) IEC958_AES0_PROFESSIONAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) IEC958_AES0_CON_NOT_COPYRIGHT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) IEC958_AES0_CON_EMPHASIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) IEC958_AES1_CON_CATEGORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) static int snd_vt1724_spdif_maskp_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) IEC958_AES0_PROFESSIONAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) IEC958_AES0_PRO_FS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) IEC958_AES0_PRO_EMPHASIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static const struct snd_kcontrol_new snd_vt1724_spdif_maskc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .info = snd_vt1724_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .get = snd_vt1724_spdif_maskc_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) static const struct snd_kcontrol_new snd_vt1724_spdif_maskp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .info = snd_vt1724_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .get = snd_vt1724_spdif_maskp_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) #define snd_vt1724_spdif_sw_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) static int snd_vt1724_spdif_sw_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) ucontrol->value.integer.value[0] = inb(ICEREG1724(ice, SPDIF_CFG)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) VT1724_CFG_SPDIF_OUT_EN ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) static int snd_vt1724_spdif_sw_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) unsigned char old, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) old = val = inb(ICEREG1724(ice, SPDIF_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) val &= ~VT1724_CFG_SPDIF_OUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (ucontrol->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) val |= VT1724_CFG_SPDIF_OUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (old != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) outb(val, ICEREG1724(ice, SPDIF_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) return old != val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) static const struct snd_kcontrol_new snd_vt1724_spdif_switch =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) /* FIXME: the following conflict with IEC958 Playback Route */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) /* .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, SWITCH), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .name = SNDRV_CTL_NAME_IEC958("Output ", NONE, SWITCH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .info = snd_vt1724_spdif_sw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .get = snd_vt1724_spdif_sw_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .put = snd_vt1724_spdif_sw_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #if 0 /* NOT USED YET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) * GPIO access from extern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) #define snd_vt1724_gpio_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) int snd_vt1724_gpio_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) int shift = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) snd_ice1712_save_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) ucontrol->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) (snd_ice1712_gpio_read(ice) & (1 << shift) ? 1 : 0) ^ invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) snd_ice1712_restore_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) int shift = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) unsigned int val, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (kcontrol->private_value & (1 << 31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) nval = (ucontrol->value.integer.value[0] ? (1 << shift) : 0) ^ invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) snd_ice1712_save_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) val = snd_ice1712_gpio_read(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) nval |= val & ~(1 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (val != nval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) snd_ice1712_gpio_write(ice, nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) snd_ice1712_restore_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) return val != nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) #endif /* NOT USED YET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) * rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static int snd_vt1724_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) int hw_rates_count = ice->hw_rates->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /* internal clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) uinfo->value.enumerated.items = hw_rates_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) /* external clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (ice->force_rdma1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) uinfo->value.enumerated.items += ice->ext_clock_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) /* upper limit - keep at top */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) if (uinfo->value.enumerated.item >= hw_rates_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* ext_clock items */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) strcpy(uinfo->value.enumerated.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) ice->ext_clock_names[
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) uinfo->value.enumerated.item - hw_rates_count]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) /* int clock items */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) sprintf(uinfo->value.enumerated.name, "%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) ice->hw_rates->list[uinfo->value.enumerated.item]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static int snd_vt1724_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) unsigned int i, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) if (ice->is_spdif_master(ice)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ucontrol->value.enumerated.item[0] = ice->hw_rates->count +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) ice->get_spdif_master_type(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) rate = ice->get_rate(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) ucontrol->value.enumerated.item[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) for (i = 0; i < ice->hw_rates->count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (ice->hw_rates->list[i] == rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) ucontrol->value.enumerated.item[0] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) static int stdclock_get_spdif_master_type(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) /* standard external clock - only single type - SPDIF IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) /* setting clock to external - SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) static int stdclock_set_spdif_clock(struct snd_ice1712 *ice, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) unsigned char oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) unsigned char i2s_oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) oval = inb(ICEMT1724(ice, RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) /* setting 256fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X, ICEMT1724(ice, I2S_FORMAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) unsigned int old_rate, new_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) unsigned int item = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) unsigned int first_ext_clock = ice->hw_rates->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (item > first_ext_clock + ice->ext_clock_count - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) /* if rate = 0 => external clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) if (ice->is_spdif_master(ice))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) old_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) old_rate = ice->get_rate(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (item >= first_ext_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) /* switching to external clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) ice->set_spdif_clock(ice, item - first_ext_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) new_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) /* internal on-card clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) new_rate = ice->hw_rates->list[item];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) ice->pro_rate_default = new_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) /* the first switch to the ext. clock mode? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (old_rate != new_rate && !new_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /* notify akm chips as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) if (ice->gpio.set_pro_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) ice->gpio.set_pro_rate(ice, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) for (i = 0; i < ice->akm_codecs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) if (ice->akm[i].ops.set_rate_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) return old_rate != new_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) static const struct snd_kcontrol_new snd_vt1724_pro_internal_clock = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .name = "Multi Track Internal Clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .info = snd_vt1724_pro_internal_clock_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .get = snd_vt1724_pro_internal_clock_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .put = snd_vt1724_pro_internal_clock_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define snd_vt1724_pro_rate_locking_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) static int snd_vt1724_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) static int snd_vt1724_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) int change = 0, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) nval = ucontrol->value.integer.value[0] ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) change = PRO_RATE_LOCKED != nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) PRO_RATE_LOCKED = nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) static const struct snd_kcontrol_new snd_vt1724_pro_rate_locking = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .name = "Multi Track Rate Locking",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .info = snd_vt1724_pro_rate_locking_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .get = snd_vt1724_pro_rate_locking_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .put = snd_vt1724_pro_rate_locking_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) #define snd_vt1724_pro_rate_reset_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) static int snd_vt1724_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) ucontrol->value.integer.value[0] = PRO_RATE_RESET ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) static int snd_vt1724_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) int change = 0, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) nval = ucontrol->value.integer.value[0] ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) change = PRO_RATE_RESET != nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) PRO_RATE_RESET = nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) static const struct snd_kcontrol_new snd_vt1724_pro_rate_reset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .name = "Multi Track Rate Reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .info = snd_vt1724_pro_rate_reset_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .get = snd_vt1724_pro_rate_reset_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .put = snd_vt1724_pro_rate_reset_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) * routing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) static int snd_vt1724_pro_route_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) static const char * const texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) "PCM Out", /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) "H/W In 0", "H/W In 1", /* 1-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) "IEC958 In L", "IEC958 In R", /* 3-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) return snd_ctl_enum_info(uinfo, 1, 5, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) static inline int analog_route_shift(int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) return (idx % 2) * 12 + ((idx / 2) * 3) + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) static inline int digital_route_shift(int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) return idx * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) unsigned char eitem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) static const unsigned char xlate[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) 0, 255, 1, 2, 255, 255, 3, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) val >>= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) val &= 7; /* we now have 3 bits per output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) eitem = xlate[val];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if (eitem == 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) return eitem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) int shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) unsigned int old_val, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) static const unsigned char xroute[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) 0, /* PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) 2, /* PSDIN0 Left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) 3, /* PSDIN0 Right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) 6, /* SPDIN Left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) 7, /* SPDIN Right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) nval = xroute[val % 5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) val = old_val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) val &= ~(0x07 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) val |= nval << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) change = val != old_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) outl(val, ICEMT1724(ice, ROUTE_PLAYBACK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) static int snd_vt1724_pro_route_analog_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) ucontrol->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) snd_ice1724_get_route_val(ice, analog_route_shift(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static int snd_vt1724_pro_route_analog_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) return snd_ice1724_put_route_val(ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) ucontrol->value.enumerated.item[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) analog_route_shift(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) static int snd_vt1724_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) ucontrol->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) snd_ice1724_get_route_val(ice, digital_route_shift(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) static int snd_vt1724_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) return snd_ice1724_put_route_val(ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) ucontrol->value.enumerated.item[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) digital_route_shift(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) static const struct snd_kcontrol_new snd_vt1724_mixer_pro_analog_route =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .name = "H/W Playback Route",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .info = snd_vt1724_pro_route_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .get = snd_vt1724_pro_route_analog_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .put = snd_vt1724_pro_route_analog_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) static const struct snd_kcontrol_new snd_vt1724_mixer_pro_spdif_route = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .info = snd_vt1724_pro_route_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .get = snd_vt1724_pro_route_spdif_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .put = snd_vt1724_pro_route_spdif_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) static int snd_vt1724_pro_peak_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) uinfo->count = 22; /* FIXME: for compatibility with ice1712... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) uinfo->value.integer.max = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) static int snd_vt1724_pro_peak_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) for (idx = 0; idx < 22; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) outb(idx, ICEMT1724(ice, MONITOR_PEAKINDEX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) ucontrol->value.integer.value[idx] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) inb(ICEMT1724(ice, MONITOR_PEAKDATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) static const struct snd_kcontrol_new snd_vt1724_mixer_pro_peak = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .name = "Multi Track Peak",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .info = snd_vt1724_pro_peak_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .get = snd_vt1724_pro_peak_get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) static const struct snd_ice1712_card_info no_matched;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) ooAoo cards with no controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) static const unsigned char ooaoo_sq210_eeprom[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) [ICE_EEP2_SYSCONF] = 0x4c, /* 49MHz crystal, no mpu401, no ADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) 1xDACs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) [ICE_EEP2_ACLINK] = 0x80, /* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) [ICE_EEP2_I2S] = 0x78, /* no volume, 96k, 24bit, 192k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) [ICE_EEP2_SPDIF] = 0xc1, /* out-en, out-int, out-ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) [ICE_EEP2_GPIO_DIR] = 0x00, /* no GPIOs are used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) [ICE_EEP2_GPIO_DIR1] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) [ICE_EEP2_GPIO_DIR2] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) [ICE_EEP2_GPIO_MASK] = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) [ICE_EEP2_GPIO_MASK1] = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) [ICE_EEP2_GPIO_MASK2] = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) [ICE_EEP2_GPIO_STATE] = 0x00, /* inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) [ICE_EEP2_GPIO_STATE1] = 0x00, /* all 1, but GPIO_CPLD_RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) and GPIO15 always zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) static const struct snd_ice1712_card_info snd_vt1724_ooaoo_cards[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .name = "ooAoo SQ210a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .model = "sq210a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .eeprom_size = sizeof(ooaoo_sq210_eeprom),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .eeprom_data = ooaoo_sq210_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) { } /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) static const struct snd_ice1712_card_info *card_tables[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) snd_vt1724_revo_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) snd_vt1724_amp_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) snd_vt1724_aureon_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) snd_vt1720_mobo_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) snd_vt1720_pontis_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) snd_vt1724_prodigy_hifi_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) snd_vt1724_prodigy192_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) snd_vt1724_juli_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) snd_vt1724_maya44_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) snd_vt1724_phase_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) snd_vt1724_wtm_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) snd_vt1724_se_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) snd_vt1724_qtet_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) snd_vt1724_ooaoo_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) snd_vt1724_psc724_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) static void wait_i2c_busy(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) int t = 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) while ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_BUSY) && t--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) if (t == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) dev_err(ice->card->dev, "i2c busy timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) unsigned char snd_vt1724_read_i2c(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) unsigned char dev, unsigned char addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) mutex_lock(&ice->i2c_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) wait_i2c_busy(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) outb(dev & ~VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) wait_i2c_busy(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) val = inb(ICEREG1724(ice, I2C_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) mutex_unlock(&ice->i2c_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) dev_dbg(ice->card->dev, "i2c_read: [0x%x,0x%x] = 0x%x\n", dev, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) void snd_vt1724_write_i2c(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) unsigned char dev, unsigned char addr, unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) mutex_lock(&ice->i2c_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) wait_i2c_busy(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) dev_dbg(ice->card->dev, "i2c_write: [0x%x,0x%x] = 0x%x\n", dev, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) outb(data, ICEREG1724(ice, I2C_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) outb(dev | VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) wait_i2c_busy(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) mutex_unlock(&ice->i2c_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) static int snd_vt1724_read_eeprom(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) const char *modelname)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) const int dev = 0xa0; /* EEPROM device address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) unsigned int i, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) const struct snd_ice1712_card_info * const *tbl, *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) if (!modelname || !*modelname) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) ice->eeprom.subvendor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) if ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_EEPROM) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) ice->eeprom.subvendor =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) (snd_vt1724_read_i2c(ice, dev, 0x00) << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) (snd_vt1724_read_i2c(ice, dev, 0x01) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) (snd_vt1724_read_i2c(ice, dev, 0x02) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) (snd_vt1724_read_i2c(ice, dev, 0x03) << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) if (ice->eeprom.subvendor == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) ice->eeprom.subvendor == (unsigned int)-1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) /* invalid subvendor from EEPROM, try the PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) * subststem ID instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) u16 vendor, device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) &vendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) ice->eeprom.subvendor =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) ((unsigned int)swab16(vendor) << 16) | swab16(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) if (ice->eeprom.subvendor == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) ice->eeprom.subvendor == (unsigned int)-1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) dev_err(ice->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) "No valid ID is found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) for (tbl = card_tables; *tbl; tbl++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) for (c = *tbl; c->name; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) if (modelname && c->model &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) !strcmp(modelname, c->model)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) dev_info(ice->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) "Using board model %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) c->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) ice->eeprom.subvendor = c->subvendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) } else if (c->subvendor != ice->eeprom.subvendor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) ice->card_info = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) if (!c->eeprom_size || !c->eeprom_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) /* if the EEPROM is given by the driver, use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) dev_dbg(ice->card->dev, "using the defined eeprom..\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) ice->eeprom.version = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) ice->eeprom.size = c->eeprom_size + 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) goto read_skipped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) ice->eeprom.subvendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) /* assume AC97-only card which can suspend without additional code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) ice->pm_suspend_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) ice->eeprom.size = snd_vt1724_read_i2c(ice, dev, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) if (ice->eeprom.size < 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) ice->eeprom.size = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) else if (ice->eeprom.size > 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) dev_err(ice->card->dev, "Invalid EEPROM (size = %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) ice->eeprom.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) ice->eeprom.version = snd_vt1724_read_i2c(ice, dev, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) if (ice->eeprom.version != 1 && ice->eeprom.version != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) dev_warn(ice->card->dev, "Invalid EEPROM version %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) ice->eeprom.version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) size = ice->eeprom.size - 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) for (i = 0; i < size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) ice->eeprom.data[i] = snd_vt1724_read_i2c(ice, dev, i + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) read_skipped:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) ice->eeprom.gpiomask = eeprom_triple(ice, ICE_EEP2_GPIO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) ice->eeprom.gpiostate = eeprom_triple(ice, ICE_EEP2_GPIO_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) ice->eeprom.gpiodir = eeprom_triple(ice, ICE_EEP2_GPIO_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) static void snd_vt1724_chip_reset(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) outb(VT1724_RESET , ICEREG1724(ice, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) outb(0, ICEREG1724(ice, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) static int snd_vt1724_chip_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) outb(ice->eeprom.data[ICE_EEP2_SYSCONF], ICEREG1724(ice, SYS_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) outb(ice->eeprom.data[ICE_EEP2_ACLINK], ICEREG1724(ice, AC97_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) outb(ice->eeprom.data[ICE_EEP2_I2S], ICEREG1724(ice, I2S_FEATURES));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) outb(ice->eeprom.data[ICE_EEP2_SPDIF], ICEREG1724(ice, SPDIF_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) ice->gpio.write_mask = ice->eeprom.gpiomask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) ice->gpio.direction = ice->eeprom.gpiodir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) snd_vt1724_set_gpio_mask(ice, ice->eeprom.gpiomask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) snd_vt1724_set_gpio_dir(ice, ice->eeprom.gpiodir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) snd_vt1724_set_gpio_data(ice, ice->eeprom.gpiostate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) outb(0, ICEREG1724(ice, POWERDOWN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) /* MPU_RX and TX irq masks are cleared later dynamically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) outb(VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX , ICEREG1724(ice, IRQMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) /* don't handle FIFO overrun/underruns (just yet),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) * since they cause machine lockups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) outb(VT1724_MULTI_FIFO_ERR, ICEMT1724(ice, DMA_INT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) static int snd_vt1724_spdif_build_controls(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) if (snd_BUG_ON(!ice->pcm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) if (!ice->own_routing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) err = snd_ctl_add(ice->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) snd_ctl_new1(&snd_vt1724_mixer_pro_spdif_route, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_spdif_switch, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_default, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) kctl->id.device = ice->pcm->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskc, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) kctl->id.device = ice->pcm->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskp, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) kctl->id.device = ice->pcm->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) #if 0 /* use default only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_stream, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) kctl->id.device = ice->pcm->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) ice->spdif.stream_ctl = kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) static int snd_vt1724_build_controls(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_eeprom, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_internal_clock, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_locking, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_reset, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) if (!ice->own_routing && ice->num_total_dacs > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) struct snd_kcontrol_new tmp = snd_vt1724_mixer_pro_analog_route;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) tmp.count = ice->num_total_dacs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) if (ice->vt1720 && tmp.count > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) tmp.count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) return snd_ctl_add(ice->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) snd_ctl_new1(&snd_vt1724_mixer_pro_peak, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) static int snd_vt1724_free(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) if (!ice->port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) goto __hw_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) /* mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) outb(0xff, ICEMT1724(ice, DMA_INT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) outb(0xff, ICEREG1724(ice, IRQMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) /* --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) __hw_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) if (ice->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) free_irq(ice->irq, ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) pci_release_regions(ice->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) snd_ice1712_akm4xxx_free(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) pci_disable_device(ice->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) kfree(ice->spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) kfree(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) static int snd_vt1724_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) struct snd_ice1712 *ice = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) return snd_vt1724_free(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) static int snd_vt1724_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) const char *modelname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) struct snd_ice1712 **r_ice1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) struct snd_ice1712 *ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .dev_free = snd_vt1724_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) *r_ice1712 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) /* enable PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) err = pci_enable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) ice = kzalloc(sizeof(*ice), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) if (ice == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) ice->vt1724 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) spin_lock_init(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) mutex_init(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) mutex_init(&ice->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) mutex_init(&ice->i2c_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) ice->gpio.set_mask = snd_vt1724_set_gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) ice->gpio.get_mask = snd_vt1724_get_gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) ice->gpio.set_dir = snd_vt1724_set_gpio_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) ice->gpio.get_dir = snd_vt1724_get_gpio_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) ice->gpio.set_data = snd_vt1724_set_gpio_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) ice->gpio.get_data = snd_vt1724_get_gpio_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) ice->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) ice->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) ice->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) snd_vt1724_proc_init(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) card->private_data = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) err = pci_request_regions(pci, "ICE1724");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) kfree(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) ice->port = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) ice->profi_port = pci_resource_start(pci, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) if (request_irq(pci->irq, snd_vt1724_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) IRQF_SHARED, KBUILD_MODNAME, ice)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) snd_vt1724_free(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) ice->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) card->sync_irq = ice->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) snd_vt1724_chip_reset(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) if (snd_vt1724_read_eeprom(ice, modelname) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) snd_vt1724_free(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) if (snd_vt1724_chip_init(ice) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) snd_vt1724_free(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) snd_vt1724_free(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) *r_ice1712 = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) * Registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static int snd_vt1724_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) struct snd_ice1712 *ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) int pcm_dev = 0, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) const struct snd_ice1712_card_info * const *tbl, *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) strcpy(card->driver, "ICE1724");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) strcpy(card->shortname, "ICEnsemble ICE1724");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) err = snd_vt1724_create(card, pci, model[dev], &ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) /* field init before calling chip_init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) ice->ext_clock_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) for (tbl = card_tables; *tbl; tbl++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) for (c = *tbl; c->name; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) if ((model[dev] && c->model &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) !strcmp(model[dev], c->model)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) (c->subvendor == ice->eeprom.subvendor)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) strcpy(card->shortname, c->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) if (c->driver) /* specific driver? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) strcpy(card->driver, c->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) if (c->chip_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) err = c->chip_init(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) goto __found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) c = &no_matched;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) __found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) * VT1724 has separate DMAs for the analog and the SPDIF streams while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) * ICE1712 has only one for both (mixed up).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) * Confusingly the analog PCM is named "professional" here because it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) * was called so in ice1712 driver, and vt1724 driver is derived from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) * ice1712 driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) ice->pro_rate_default = PRO_RATE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) if (!ice->is_spdif_master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) ice->is_spdif_master = stdclock_is_spdif_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) if (!ice->get_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) ice->get_rate = stdclock_get_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) if (!ice->set_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) ice->set_rate = stdclock_set_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) if (!ice->set_mclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) ice->set_mclk = stdclock_set_mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) if (!ice->set_spdif_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) ice->set_spdif_clock = stdclock_set_spdif_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) if (!ice->get_spdif_master_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) ice->get_spdif_master_type = stdclock_get_spdif_master_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if (!ice->ext_clock_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) ice->ext_clock_names = ext_clock_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) if (!ice->ext_clock_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) if (!ice->hw_rates)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) set_std_hw_rates(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) err = snd_vt1724_pcm_profi(ice, pcm_dev++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) err = snd_vt1724_pcm_spdif(ice, pcm_dev++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) err = snd_vt1724_pcm_indep(ice, pcm_dev++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) err = snd_vt1724_ac97_mixer(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) err = snd_vt1724_build_controls(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) if (ice->pcm && ice->has_spdif) { /* has SPDIF I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) err = snd_vt1724_spdif_build_controls(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) if (c->build_controls) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) err = c->build_controls(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) if (!c->no_mpu401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) if (ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_MPU401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) err = snd_rawmidi_new(card, "MIDI", 0, 1, 1, &rmidi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) ice->rmidi[0] = rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) rmidi->private_data = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) strcpy(rmidi->name, "ICE1724 MIDI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) rmidi->info_flags = SNDRV_RAWMIDI_INFO_OUTPUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) SNDRV_RAWMIDI_INFO_INPUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) SNDRV_RAWMIDI_INFO_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) &vt1724_midi_output_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) &vt1724_midi_input_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) /* set watermarks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) outb(VT1724_MPU_RX_FIFO | 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) ICEREG1724(ice, MPU_FIFO_WM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) outb(0x1, ICEREG1724(ice, MPU_FIFO_WM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) /* set UART mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) outb(VT1724_MPU_UART, ICEREG1724(ice, MPU_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) sprintf(card->longname, "%s at 0x%lx, irq %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) card->shortname, ice->port, ice->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) static void snd_vt1724_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) struct snd_card *card = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) struct snd_ice1712 *ice = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) if (ice->card_info && ice->card_info->chip_exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) ice->card_info->chip_exit(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) static int snd_vt1724_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) struct snd_ice1712 *ice = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) if (!ice->pm_suspend_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) snd_ac97_suspend(ice->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) ice->pm_saved_is_spdif_master = ice->is_spdif_master(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) ice->pm_saved_spdif_ctrl = inw(ICEMT1724(ice, SPDIF_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) ice->pm_saved_spdif_cfg = inb(ICEREG1724(ice, SPDIF_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) ice->pm_saved_route = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) if (ice->pm_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) ice->pm_suspend(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) static int snd_vt1724_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) struct snd_ice1712 *ice = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) if (!ice->pm_suspend_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) snd_vt1724_chip_reset(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) if (snd_vt1724_chip_init(ice) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) snd_card_disconnect(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) if (ice->pm_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) ice->pm_resume(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) if (ice->pm_saved_is_spdif_master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) /* switching to external clock via SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) ice->set_spdif_clock(ice, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) /* internal on-card clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) if (ice->cur_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) rate = ice->cur_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) rate = ice->pro_rate_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) snd_vt1724_set_pro_rate(ice, rate, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) update_spdif_bits(ice, ice->pm_saved_spdif_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) outb(ice->pm_saved_spdif_cfg, ICEREG1724(ice, SPDIF_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) outl(ice->pm_saved_route, ICEMT1724(ice, ROUTE_PLAYBACK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) snd_ac97_resume(ice->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) static SIMPLE_DEV_PM_OPS(snd_vt1724_pm, snd_vt1724_suspend, snd_vt1724_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) #define SND_VT1724_PM_OPS &snd_vt1724_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) #define SND_VT1724_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) static struct pci_driver vt1724_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) .id_table = snd_vt1724_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) .probe = snd_vt1724_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .remove = snd_vt1724_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) .pm = SND_VT1724_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) module_pci_driver(vt1724_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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