^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for ICEnsemble ICE1712 (Envy24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) NOTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - spdif nonaudio consumer mode does not work (at least with my
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Sony STR-DB830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Changes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 2002.09.09 Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * split the code to several files. each low-level routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * is stored in the local file and called from registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * function from card_info struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 2002.11.26 James Stafford <jstafford@ampltd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Added support for VT1724 (Envy24HT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * I have left out support for 176.4 and 192 KHz for the moment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * I also haven't done anything with the internal S/PDIF transmitter or the MPU-401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 2003.02.20 Taksahi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Split vt1724 part to an independent driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The GPIO is accessed through the callback functions now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 2004.03.31 Doug McLain <nostar@comcast.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Added support for Event Electronics EZ8 card to hoontech.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <sound/cs8427.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include "ice1712.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* lowlevel routines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include "delta.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include "ews.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include "hoontech.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_DESCRIPTION("ICEnsemble ICE1712 (Envy24)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MODULE_SUPPORTED_DEVICE("{"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) HOONTECH_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DELTA_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) EWS_DEVICE_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "{ICEnsemble,Generic ICE1712},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "{ICEnsemble,Generic Envy24}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static char *model[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static bool omni[SNDRV_CARDS]; /* Delta44 & 66 Omni I/O support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transceiver reset timeout value in msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int dxr_enable[SNDRV_CARDS]; /* DXR enable for DMX6FIRE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MODULE_PARM_DESC(index, "Index value for ICE1712 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_PARM_DESC(id, "ID string for ICE1712 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MODULE_PARM_DESC(enable, "Enable ICE1712 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) module_param_array(omni, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MODULE_PARM_DESC(omni, "Enable Midiman M-Audio Delta Omni I/O support.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) module_param_array(cs8427_timeout, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MODULE_PARM_DESC(cs8427_timeout, "Define reset timeout for cs8427 chip in msec resolution.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) module_param_array(model, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MODULE_PARM_DESC(model, "Use the given board model.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) module_param_array(dxr_enable, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MODULE_PARM_DESC(dxr_enable, "Enable DXR support for Terratec DMX6FIRE.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct pci_device_id snd_ice1712_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { PCI_VDEVICE(ICE, PCI_DEVICE_ID_ICE_1712), 0 }, /* ICE1712 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MODULE_DEVICE_TABLE(pci, snd_ice1712_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int snd_ice1712_build_controls(struct snd_ice1712 *ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int PRO_RATE_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int PRO_RATE_RESET = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static unsigned int PRO_RATE_DEFAULT = 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Basic I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* check whether the clock mode is spdif-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline int is_spdif_master(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return is_spdif_master(ice) || PRO_RATE_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline void snd_ice1712_ds_write(struct snd_ice1712 *ice, u8 channel, u8 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) outb((channel << 4) | addr, ICEDS(ice, INDEX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) outl(data, ICEDS(ice, DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline u32 snd_ice1712_ds_read(struct snd_ice1712 *ice, u8 channel, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) outb((channel << 4) | addr, ICEDS(ice, INDEX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return inl(ICEDS(ice, DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void snd_ice1712_ac97_write(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned short reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct snd_ice1712 *ice = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned char old_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for (tm = 0; tm < 0x10000; tm++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) old_cmd = inb(ICEREG(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!(old_cmd & ICE1712_AC97_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) outb(reg, ICEREG(ice, AC97_INDEX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) outw(val, ICEREG(ice, AC97_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) outb(old_cmd | ICE1712_AC97_WRITE, ICEREG(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) for (tm = 0; tm < 0x10000; tm++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static unsigned short snd_ice1712_ac97_read(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct snd_ice1712 *ice = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned char old_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) for (tm = 0; tm < 0x10000; tm++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) old_cmd = inb(ICEREG(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (!(old_cmd & ICE1712_AC97_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) outb(reg, ICEREG(ice, AC97_INDEX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) outb(old_cmd | ICE1712_AC97_READ, ICEREG(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) for (tm = 0; tm < 0x10000; tm++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (tm >= 0x10000) /* timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return inw(ICEREG(ice, AC97_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * pro ac97 section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void snd_ice1712_pro_ac97_write(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned short reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct snd_ice1712 *ice = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned char old_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) for (tm = 0; tm < 0x10000; tm++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) old_cmd = inb(ICEMT(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (!(old_cmd & ICE1712_AC97_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) outb(reg, ICEMT(ice, AC97_INDEX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) outw(val, ICEMT(ice, AC97_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) outb(old_cmd | ICE1712_AC97_WRITE, ICEMT(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) for (tm = 0; tm < 0x10000; tm++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static unsigned short snd_ice1712_pro_ac97_read(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct snd_ice1712 *ice = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned char old_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) for (tm = 0; tm < 0x10000; tm++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) old_cmd = inb(ICEMT(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!(old_cmd & ICE1712_AC97_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) outb(reg, ICEMT(ice, AC97_INDEX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) outb(old_cmd | ICE1712_AC97_READ, ICEMT(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) for (tm = 0; tm < 0x10000; tm++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (tm >= 0x10000) /* timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return inw(ICEMT(ice, AC97_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * consumer ac97 digital mix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define snd_ice1712_digmix_route_ac97_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int snd_ice1712_digmix_route_ac97_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_ROUTECTRL)) & ICE1712_ROUTE_AC97 ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int snd_ice1712_digmix_route_ac97_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned char val, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val = inb(ICEMT(ice, MONITOR_ROUTECTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) nval = val & ~ICE1712_ROUTE_AC97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ucontrol->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) nval |= ICE1712_ROUTE_AC97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) outb(nval, ICEMT(ice, MONITOR_ROUTECTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return val != nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct snd_kcontrol_new snd_ice1712_mixer_digmix_route_ac97 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .name = "Digital Mixer To AC97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .info = snd_ice1712_digmix_route_ac97_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .get = snd_ice1712_digmix_route_ac97_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .put = snd_ice1712_digmix_route_ac97_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * gpio operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void snd_ice1712_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static unsigned int snd_ice1712_get_gpio_dir(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static unsigned int snd_ice1712_get_gpio_mask(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void snd_ice1712_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static unsigned int snd_ice1712_get_gpio_data(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void snd_ice1712_set_gpio_data(struct snd_ice1712 *ice, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * CS8427 interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * change the input clock selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * spdif_clock = 1 - IEC958 input, 0 - Envy24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int snd_ice1712_cs8427_set_input_clock(struct snd_ice1712 *ice, int spdif_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned char reg[2] = { 0x80 | 4, 0 }; /* CS8427 auto increment | register number 4 + data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned char val, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) snd_i2c_lock(ice->i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (snd_i2c_sendbytes(ice->cs8427, reg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) snd_i2c_unlock(ice->i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (snd_i2c_readbytes(ice->cs8427, &val, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) snd_i2c_unlock(ice->i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) nval = val & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (spdif_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) nval |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) nval |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (val != nval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) reg[1] = nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (snd_i2c_sendbytes(ice->cs8427, reg, 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) res = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) res++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) snd_i2c_unlock(ice->i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * spdif callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void open_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) snd_cs8427_iec958_active(ice->cs8427, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static void close_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) snd_cs8427_iec958_active(ice->cs8427, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void setup_cs8427(struct snd_ice1712 *ice, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) snd_cs8427_iec958_pcm(ice->cs8427, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * create and initialize callbacks for cs8427 interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) err = snd_cs8427_create(ice->i2c, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) (ice->cs8427_timeout * HZ) / 1000, &ice->cs8427);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_err(ice->card->dev, "CS8427 initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ice->spdif.ops.open = open_cs8427;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ice->spdif.ops.close = close_cs8427;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ice->spdif.ops.setup_rate = setup_cs8427;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void snd_ice1712_set_input_clock_source(struct snd_ice1712 *ice, int spdif_is_master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* change CS8427 clock source too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ice->cs8427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) snd_ice1712_cs8427_set_input_clock(ice, spdif_is_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* notify ak4524 chip as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (spdif_is_master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) for (i = 0; i < ice->akm_codecs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ice->akm[i].ops.set_rate_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static irqreturn_t snd_ice1712_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct snd_ice1712 *ice = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) status = inb(ICEREG(ice, IRQSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (status & ICE1712_IRQ_MPU1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (ice->rmidi[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) snd_mpu401_uart_interrupt(irq, ice->rmidi[0]->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) outb(ICE1712_IRQ_MPU1, ICEREG(ice, IRQSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) status &= ~ICE1712_IRQ_MPU1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (status & ICE1712_IRQ_TIMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) outb(ICE1712_IRQ_TIMER, ICEREG(ice, IRQSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (status & ICE1712_IRQ_MPU2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (ice->rmidi[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) snd_mpu401_uart_interrupt(irq, ice->rmidi[1]->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) outb(ICE1712_IRQ_MPU2, ICEREG(ice, IRQSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) status &= ~ICE1712_IRQ_MPU2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (status & ICE1712_IRQ_PROPCM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned char mtstat = inb(ICEMT(ice, IRQ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (mtstat & ICE1712_MULTI_PBKSTATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (ice->playback_pro_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) snd_pcm_period_elapsed(ice->playback_pro_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) outb(ICE1712_MULTI_PBKSTATUS, ICEMT(ice, IRQ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (mtstat & ICE1712_MULTI_CAPSTATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ice->capture_pro_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) snd_pcm_period_elapsed(ice->capture_pro_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) outb(ICE1712_MULTI_CAPSTATUS, ICEMT(ice, IRQ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (status & ICE1712_IRQ_FM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) outb(ICE1712_IRQ_FM, ICEREG(ice, IRQSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (status & ICE1712_IRQ_PBKDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u32 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u16 pbkstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pbkstatus = inw(ICEDS(ice, INTSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* dev_dbg(ice->card->dev, "pbkstatus = 0x%x\n", pbkstatus); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) for (idx = 0; idx < 6; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if ((pbkstatus & (3 << (idx * 2))) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) substream = ice->playback_con_substream_ds[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (substream != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) snd_pcm_period_elapsed(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) outw(3 << (idx * 2), ICEDS(ice, INTSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) outb(ICE1712_IRQ_PBKDS, ICEREG(ice, IRQSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (status & ICE1712_IRQ_CONCAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ice->capture_con_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) snd_pcm_period_elapsed(ice->capture_con_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) outb(ICE1712_IRQ_CONCAP, ICEREG(ice, IRQSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (status & ICE1712_IRQ_CONPBK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ice->playback_con_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) snd_pcm_period_elapsed(ice->playback_con_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) outb(ICE1712_IRQ_CONPBK, ICEREG(ice, IRQSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * PCM part - consumer I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int snd_ice1712_playback_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) spin_lock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) tmp = snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (cmd == SNDRV_PCM_TRIGGER_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) tmp |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) tmp &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) tmp |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) tmp &= ~2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) spin_unlock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int snd_ice1712_playback_ds_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) spin_lock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) tmp = snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (cmd == SNDRV_PCM_TRIGGER_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) tmp |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) tmp &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) tmp |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) tmp &= ~2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) snd_ice1712_ds_write(ice, substream->number * 2, ICE1712_DSC_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) spin_unlock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static int snd_ice1712_capture_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) spin_lock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) tmp = snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (cmd == SNDRV_PCM_TRIGGER_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) tmp |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) tmp &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) spin_unlock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int snd_ice1712_playback_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 period_size, buf_size, rate, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) tmp = 0x0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (snd_pcm_format_width(runtime->format) == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) tmp |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (runtime->channels == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) tmp |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) rate = (runtime->rate * 8192) / 375;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (rate > 0x000fffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) rate = 0x000fffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) outb(0, ice->ddma_port + 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) outb(ICE1712_DMA_MODE_WRITE | ICE1712_DMA_AUTOINIT, ice->ddma_port + 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) outl(runtime->dma_addr, ice->ddma_port + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) outw(buf_size, ice->ddma_port + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_LO, rate & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_MID, (rate >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_HI, (rate >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_LO, period_size & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_HI, period_size >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) snd_ice1712_write(ice, ICE1712_IREG_PBK_LEFT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) snd_ice1712_write(ice, ICE1712_IREG_PBK_RIGHT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int snd_ice1712_playback_ds_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 period_size, rate, tmp, chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) period_size = snd_pcm_lib_period_bytes(substream) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) tmp = 0x0064;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (snd_pcm_format_width(runtime->format) == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) tmp &= ~0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (runtime->channels == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) tmp |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) rate = (runtime->rate * 8192) / 375;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (rate > 0x000fffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) rate = 0x000fffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ice->playback_con_active_buf[substream->number] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ice->playback_con_virt_addr[substream->number] = runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) chn = substream->number * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR0, runtime->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT0, period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR1, runtime->dma_addr + (runtime->periods > 1 ? period_size + 1 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT1, period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) snd_ice1712_ds_write(ice, chn, ICE1712_DSC_RATE, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) snd_ice1712_ds_write(ice, chn, ICE1712_DSC_VOLUME, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) snd_ice1712_ds_write(ice, chn, ICE1712_DSC_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (runtime->channels == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_RATE, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_VOLUME, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int snd_ice1712_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u32 period_size, buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) tmp = 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (snd_pcm_format_width(runtime->format) == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) tmp &= ~0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (runtime->channels == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) tmp &= ~0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) outl(ice->capture_con_virt_addr = runtime->dma_addr, ICEREG(ice, CONCAP_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) outw(buf_size, ICEREG(ice, CONCAP_COUNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_HI, period_size >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_LO, period_size & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) snd_ac97_set_rate(ice->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static snd_pcm_uframes_t snd_ice1712_playback_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (!(snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ptr = runtime->buffer_size - inw(ice->ddma_port + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ptr = bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ptr == runtime->buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static snd_pcm_uframes_t snd_ice1712_playback_ds_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (!(snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (ice->playback_con_active_buf[substream->number])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) addr = ICE1712_DSC_ADDR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) addr = ICE1712_DSC_ADDR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ptr = snd_ice1712_ds_read(ice, substream->number * 2, addr) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ice->playback_con_virt_addr[substream->number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ptr = bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (ptr == substream->runtime->buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static snd_pcm_uframes_t snd_ice1712_capture_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (!(snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ptr = inl(ICEREG(ice, CONCAP_ADDR)) - ice->capture_con_virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ptr = bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (ptr == substream->runtime->buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const struct snd_pcm_hardware snd_ice1712_playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) SNDRV_PCM_INFO_PAUSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .rate_min = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .buffer_bytes_max = (64*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .period_bytes_max = (64*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static const struct snd_pcm_hardware snd_ice1712_playback_ds = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) SNDRV_PCM_INFO_PAUSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .rate_min = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .buffer_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .period_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .periods_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const struct snd_pcm_hardware snd_ice1712_capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .rate_min = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .buffer_bytes_max = (64*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .period_bytes_max = (64*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static int snd_ice1712_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ice->playback_con_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) runtime->hw = snd_ice1712_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static int snd_ice1712_playback_ds_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ice->playback_con_substream_ds[substream->number] = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) runtime->hw = snd_ice1712_playback_ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) tmp = inw(ICEDS(ice, INTMASK)) & ~(1 << (substream->number * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) outw(tmp, ICEDS(ice, INTMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static int snd_ice1712_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ice->capture_con_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) runtime->hw = snd_ice1712_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) runtime->hw.rates = ice->ac97->rates[AC97_RATES_ADC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (!(runtime->hw.rates & SNDRV_PCM_RATE_8000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) runtime->hw.rate_min = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int snd_ice1712_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ice->playback_con_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int snd_ice1712_playback_ds_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) tmp = inw(ICEDS(ice, INTMASK)) | (3 << (substream->number * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) outw(tmp, ICEDS(ice, INTMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ice->playback_con_substream_ds[substream->number] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int snd_ice1712_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ice->capture_con_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static const struct snd_pcm_ops snd_ice1712_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .open = snd_ice1712_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .close = snd_ice1712_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .prepare = snd_ice1712_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .trigger = snd_ice1712_playback_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .pointer = snd_ice1712_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static const struct snd_pcm_ops snd_ice1712_playback_ds_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .open = snd_ice1712_playback_ds_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .close = snd_ice1712_playback_ds_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .prepare = snd_ice1712_playback_ds_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .trigger = snd_ice1712_playback_ds_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .pointer = snd_ice1712_playback_ds_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static const struct snd_pcm_ops snd_ice1712_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .open = snd_ice1712_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .close = snd_ice1712_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .prepare = snd_ice1712_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .trigger = snd_ice1712_capture_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .pointer = snd_ice1712_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static int snd_ice1712_pcm(struct snd_ice1712 *ice, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) err = snd_pcm_new(ice->card, "ICE1712 consumer", device, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) pcm->private_data = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) strcpy(pcm->name, "ICE1712 consumer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ice->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) &ice->pci->dev, 64*1024, 64*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dev_warn(ice->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) "Consumer PCM code does not work well at the moment --jk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int snd_ice1712_pcm_ds(struct snd_ice1712 *ice, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) err = snd_pcm_new(ice->card, "ICE1712 consumer (DS)", device, 6, 0, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ds_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) pcm->private_data = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) strcpy(pcm->name, "ICE1712 consumer (DS)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ice->pcm_ds = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) &ice->pci->dev, 64*1024, 128*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * PCM code - professional part (multitrack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static const unsigned int rates[] = { 8000, 9600, 11025, 12000, 16000, 22050, 24000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) 32000, 44100, 48000, 64000, 88200, 96000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .count = ARRAY_SIZE(rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .list = rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static int snd_ice1712_pro_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) unsigned int what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) unsigned int old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) what = ICE1712_PLAYBACK_PAUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) snd_pcm_trigger_done(substream, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) spin_lock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) old = inl(ICEMT(ice, PLAYBACK_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) old |= what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) old &= ~what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) outl(old, ICEMT(ice, PLAYBACK_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) spin_unlock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) unsigned int what = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) unsigned int old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct snd_pcm_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (s == ice->playback_pro_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) what |= ICE1712_PLAYBACK_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) } else if (s == ice->capture_pro_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) what |= ICE1712_CAPTURE_START_SHADOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) spin_lock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) old = inl(ICEMT(ice, PLAYBACK_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (cmd == SNDRV_PCM_TRIGGER_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) old |= what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) old &= ~what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) outl(old, ICEMT(ice, PLAYBACK_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) spin_unlock(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static void snd_ice1712_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate, int force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) unsigned char val, old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) case 8000: val = 6; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) case 9600: val = 3; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) case 11025: val = 10; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) case 12000: val = 2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) case 16000: val = 5; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) case 22050: val = 9; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) case 24000: val = 1; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) case 32000: val = 4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) case 44100: val = 8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) case 48000: val = 0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) case 64000: val = 15; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) case 88200: val = 11; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) case 96000: val = 7; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) rate = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) spin_lock_irqsave(&ice->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (inb(ICEMT(ice, PLAYBACK_CONTROL)) & (ICE1712_CAPTURE_START_SHADOW|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ICE1712_PLAYBACK_PAUSE|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ICE1712_PLAYBACK_START)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) __out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) spin_unlock_irqrestore(&ice->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (!force && is_pro_rate_locked(ice))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) goto __out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) old = inb(ICEMT(ice, RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (!force && old == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) goto __out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ice->cur_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) outb(val, ICEMT(ice, RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) spin_unlock_irqrestore(&ice->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (ice->gpio.set_pro_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ice->gpio.set_pro_rate(ice, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) for (i = 0; i < ice->akm_codecs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (ice->akm[i].ops.set_rate_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (ice->spdif.ops.setup_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ice->spdif.ops.setup_rate(ice, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static int snd_ice1712_playback_pro_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ice->playback_pro_size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) outl(substream->runtime->dma_addr, ICEMT(ice, PLAYBACK_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) outw((ice->playback_pro_size >> 2) - 1, ICEMT(ice, PLAYBACK_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, PLAYBACK_COUNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static int snd_ice1712_playback_pro_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static int snd_ice1712_capture_pro_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ice->capture_pro_size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) outl(substream->runtime->dma_addr, ICEMT(ice, CAPTURE_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) outw((ice->capture_pro_size >> 2) - 1, ICEMT(ice, CAPTURE_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, CAPTURE_COUNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static int snd_ice1712_capture_pro_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static snd_pcm_uframes_t snd_ice1712_playback_pro_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_PLAYBACK_START))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ptr = ice->playback_pro_size - (inw(ICEMT(ice, PLAYBACK_SIZE)) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ptr = bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (ptr == substream->runtime->buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static snd_pcm_uframes_t snd_ice1712_capture_pro_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_CAPTURE_START_SHADOW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ptr = ice->capture_pro_size - (inw(ICEMT(ice, CAPTURE_SIZE)) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ptr = bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (ptr == substream->runtime->buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static const struct snd_pcm_hardware snd_ice1712_playback_pro = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .formats = SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .rate_min = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .channels_min = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .channels_max = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .buffer_bytes_max = (256*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .period_bytes_min = 10 * 4 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .period_bytes_max = 131040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static const struct snd_pcm_hardware snd_ice1712_capture_pro = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .formats = SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .rate_min = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .channels_min = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .channels_max = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .buffer_bytes_max = (256*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .period_bytes_min = 12 * 4 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .period_bytes_max = 131040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static int snd_ice1712_playback_pro_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ice->playback_pro_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) runtime->hw = snd_ice1712_playback_pro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (is_pro_rate_locked(ice)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) runtime->hw.rate_min = PRO_RATE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) runtime->hw.rate_max = PRO_RATE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (ice->spdif.ops.open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ice->spdif.ops.open(ice, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static int snd_ice1712_capture_pro_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ice->capture_pro_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) runtime->hw = snd_ice1712_capture_pro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (is_pro_rate_locked(ice)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) runtime->hw.rate_min = PRO_RATE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) runtime->hw.rate_max = PRO_RATE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static int snd_ice1712_playback_pro_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (PRO_RATE_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ice->playback_pro_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (ice->spdif.ops.close)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ice->spdif.ops.close(ice, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static int snd_ice1712_capture_pro_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (PRO_RATE_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ice->capture_pro_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static const struct snd_pcm_ops snd_ice1712_playback_pro_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .open = snd_ice1712_playback_pro_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .close = snd_ice1712_playback_pro_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .hw_params = snd_ice1712_playback_pro_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .prepare = snd_ice1712_playback_pro_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .trigger = snd_ice1712_pro_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .pointer = snd_ice1712_playback_pro_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static const struct snd_pcm_ops snd_ice1712_capture_pro_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .open = snd_ice1712_capture_pro_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .close = snd_ice1712_capture_pro_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .hw_params = snd_ice1712_capture_pro_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .prepare = snd_ice1712_capture_pro_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .trigger = snd_ice1712_pro_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .pointer = snd_ice1712_capture_pro_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static int snd_ice1712_pcm_profi(struct snd_ice1712 *ice, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) err = snd_pcm_new(ice->card, "ICE1712 multi", device, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_pro_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_pro_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) pcm->private_data = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) strcpy(pcm->name, "ICE1712 multi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) &ice->pci->dev, 256*1024, 256*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ice->pcm_pro = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (ice->cs8427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /* assign channels to iec958 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) err = snd_cs8427_iec958_build(ice->cs8427,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) pcm->streams[0].substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) pcm->streams[1].substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return snd_ice1712_build_pro_mixer(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * Mixer section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static void snd_ice1712_update_volume(struct snd_ice1712 *ice, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) unsigned int vol = ice->pro_volumes[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) unsigned short val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) val |= (vol & 0x8000) == 0 ? (96 - (vol & 0x7f)) : 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) val |= ((vol & 0x80000000) == 0 ? (96 - ((vol >> 16) & 0x7f)) : 0x7f) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) outb(index, ICEMT(ice, MONITOR_INDEX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) outw(val, ICEMT(ice, MONITOR_VOLUME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define snd_ice1712_pro_mixer_switch_info snd_ctl_boolean_stereo_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static int snd_ice1712_pro_mixer_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ucontrol->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) !((ice->pro_volumes[priv_idx] >> 15) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ucontrol->value.integer.value[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) !((ice->pro_volumes[priv_idx] >> 31) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static int snd_ice1712_pro_mixer_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) unsigned int nval, change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) nval = (ucontrol->value.integer.value[0] ? 0 : 0x00008000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) (ucontrol->value.integer.value[1] ? 0 : 0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) nval |= ice->pro_volumes[priv_idx] & ~0x80008000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) change = nval != ice->pro_volumes[priv_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) ice->pro_volumes[priv_idx] = nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) snd_ice1712_update_volume(ice, priv_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static int snd_ice1712_pro_mixer_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) uinfo->value.integer.max = 96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static int snd_ice1712_pro_mixer_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) ucontrol->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) (ice->pro_volumes[priv_idx] >> 0) & 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ucontrol->value.integer.value[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) (ice->pro_volumes[priv_idx] >> 16) & 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static int snd_ice1712_pro_mixer_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) unsigned int nval, change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) nval = (ucontrol->value.integer.value[0] & 127) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) ((ucontrol->value.integer.value[1] & 127) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) nval |= ice->pro_volumes[priv_idx] & ~0x007f007f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) change = nval != ice->pro_volumes[priv_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) ice->pro_volumes[priv_idx] = nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) snd_ice1712_update_volume(ice, priv_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static const DECLARE_TLV_DB_SCALE(db_scale_playback, -14400, 150, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static const struct snd_kcontrol_new snd_ice1712_multi_playback_ctrls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .name = "Multi Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .info = snd_ice1712_pro_mixer_switch_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .get = snd_ice1712_pro_mixer_switch_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .put = snd_ice1712_pro_mixer_switch_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .private_value = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .count = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .name = "Multi Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .info = snd_ice1712_pro_mixer_volume_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .get = snd_ice1712_pro_mixer_volume_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .put = snd_ice1712_pro_mixer_volume_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .private_value = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .count = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .tlv = { .p = db_scale_playback }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static const struct snd_kcontrol_new snd_ice1712_multi_capture_analog_switch = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .name = "H/W Multi Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .info = snd_ice1712_pro_mixer_switch_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .get = snd_ice1712_pro_mixer_switch_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .put = snd_ice1712_pro_mixer_switch_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .private_value = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static const struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_switch = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, SWITCH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .info = snd_ice1712_pro_mixer_switch_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .get = snd_ice1712_pro_mixer_switch_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .put = snd_ice1712_pro_mixer_switch_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .private_value = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static const struct snd_kcontrol_new snd_ice1712_multi_capture_analog_volume = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) SNDRV_CTL_ELEM_ACCESS_TLV_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .name = "H/W Multi Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .info = snd_ice1712_pro_mixer_volume_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .get = snd_ice1712_pro_mixer_volume_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .put = snd_ice1712_pro_mixer_volume_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .private_value = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .tlv = { .p = db_scale_playback }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) static const struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_volume = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, VOLUME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .info = snd_ice1712_pro_mixer_volume_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .get = snd_ice1712_pro_mixer_volume_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .put = snd_ice1712_pro_mixer_volume_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .private_value = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) struct snd_card *card = ice->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /* multi-channel mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) for (idx = 0; idx < ARRAY_SIZE(snd_ice1712_multi_playback_ctrls); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_playback_ctrls[idx], ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (ice->num_total_adcs > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) tmp.count = ice->num_total_adcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_switch, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (ice->num_total_adcs > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) tmp.count = ice->num_total_adcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_volume, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /* initialize volumes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) for (idx = 0; idx < 10; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) ice->pro_volumes[idx] = 0x80008000; /* mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) snd_ice1712_update_volume(ice, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) for (idx = 10; idx < 10 + ice->num_total_adcs; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) ice->pro_volumes[idx] = 0x80008000; /* mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) snd_ice1712_update_volume(ice, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) for (idx = 18; idx < 20; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) ice->pro_volumes[idx] = 0x80008000; /* mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) snd_ice1712_update_volume(ice, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static void snd_ice1712_mixer_free_ac97(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) struct snd_ice1712 *ice = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) ice->ac97 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static int snd_ice1712_ac97_mixer(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) int err, bus_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct snd_ac97_template ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) struct snd_ac97_bus *pbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static const struct snd_ac97_bus_ops con_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .write = snd_ice1712_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .read = snd_ice1712_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) static const struct snd_ac97_bus_ops pro_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .write = snd_ice1712_pro_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .read = snd_ice1712_pro_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (ice_has_con_ac97(ice)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) err = snd_ac97_bus(ice->card, bus_num++, &con_ops, NULL, &pbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) ac97.private_data = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) ac97.private_free = snd_ice1712_mixer_free_ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) dev_warn(ice->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) "cannot initialize ac97 for consumer, skipped\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return snd_ctl_add(ice->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) snd_ctl_new1(&snd_ice1712_mixer_digmix_route_ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (!(ice->eeprom.data[ICE_EEP1_ACLINK] & ICE1712_CFG_PRO_I2S)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) err = snd_ac97_bus(ice->card, bus_num, &pro_ops, NULL, &pbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) ac97.private_data = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ac97.private_free = snd_ice1712_mixer_free_ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) dev_warn(ice->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) "cannot initialize pro ac97, skipped\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* I2S mixer only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) strcat(ice->card->mixername, "ICE1712 - multitrack");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static inline unsigned int eeprom_double(struct snd_ice1712 *ice, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return (unsigned int)ice->eeprom.data[idx] | ((unsigned int)ice->eeprom.data[idx + 1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static void snd_ice1712_proc_read(struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct snd_ice1712 *ice = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) snd_iprintf(buffer, "%s\n\n", ice->card->longname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) snd_iprintf(buffer, "EEPROM:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) snd_iprintf(buffer, " Codec : 0x%x\n", ice->eeprom.data[ICE_EEP1_CODEC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) snd_iprintf(buffer, " ACLink : 0x%x\n", ice->eeprom.data[ICE_EEP1_ACLINK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) snd_iprintf(buffer, " I2S ID : 0x%x\n", ice->eeprom.data[ICE_EEP1_I2SID]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) snd_iprintf(buffer, " S/PDIF : 0x%x\n", ice->eeprom.data[ICE_EEP1_SPDIF]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) snd_iprintf(buffer, " GPIO mask : 0x%x\n", ice->eeprom.gpiomask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) snd_iprintf(buffer, " GPIO state : 0x%x\n", ice->eeprom.gpiostate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) snd_iprintf(buffer, " GPIO direction : 0x%x\n", ice->eeprom.gpiodir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) snd_iprintf(buffer, " AC'97 main : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_MAIN_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) snd_iprintf(buffer, " AC'97 pcm : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_PCM_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) snd_iprintf(buffer, " AC'97 record : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_REC_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) snd_iprintf(buffer, " AC'97 record src : 0x%x\n", ice->eeprom.data[ICE_EEP1_AC97_RECSRC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) for (idx = 0; idx < 4; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) snd_iprintf(buffer, " DAC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_DAC_ID + idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) for (idx = 0; idx < 4; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) snd_iprintf(buffer, " ADC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_ADC_ID + idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) for (idx = 0x1c; idx < ice->eeprom.size; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) snd_iprintf(buffer, " Extra #%02i : 0x%x\n", idx, ice->eeprom.data[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) snd_iprintf(buffer, "\nRegisters:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) snd_iprintf(buffer, " PSDOUT03 : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_PSDOUT03)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) snd_iprintf(buffer, " CAPTURE : 0x%08x\n", inl(ICEMT(ice, ROUTE_CAPTURE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) snd_iprintf(buffer, " SPDOUT : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_SPDOUT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) snd_iprintf(buffer, " RATE : 0x%02x\n", (unsigned)inb(ICEMT(ice, RATE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) snd_iprintf(buffer, " GPIO_DATA : 0x%02x\n", (unsigned)snd_ice1712_get_gpio_data(ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) snd_iprintf(buffer, " GPIO_WRITE_MASK : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) snd_iprintf(buffer, " GPIO_DIRECTION : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) static void snd_ice1712_proc_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) snd_card_ro_proc_new(ice->card, "ice1712", ice, snd_ice1712_proc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) static int snd_ice1712_eeprom_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) uinfo->count = sizeof(struct snd_ice1712_eeprom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static int snd_ice1712_eeprom_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) static const struct snd_kcontrol_new snd_ice1712_eeprom = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .iface = SNDRV_CTL_ELEM_IFACE_CARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .name = "ICE1712 EEPROM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .info = snd_ice1712_eeprom_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .get = snd_ice1712_eeprom_get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) static int snd_ice1712_spdif_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static int snd_ice1712_spdif_default_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (ice->spdif.ops.default_get)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) ice->spdif.ops.default_get(ice, ucontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) static int snd_ice1712_spdif_default_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (ice->spdif.ops.default_put)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) return ice->spdif.ops.default_put(ice, ucontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) static const struct snd_kcontrol_new snd_ice1712_spdif_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .info = snd_ice1712_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .get = snd_ice1712_spdif_default_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .put = snd_ice1712_spdif_default_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static int snd_ice1712_spdif_maskc_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (ice->spdif.ops.default_get) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) IEC958_AES0_PROFESSIONAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) IEC958_AES0_CON_NOT_COPYRIGHT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) IEC958_AES0_CON_EMPHASIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) IEC958_AES1_CON_CATEGORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) ucontrol->value.iec958.status[0] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) ucontrol->value.iec958.status[1] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ucontrol->value.iec958.status[2] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) ucontrol->value.iec958.status[3] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) ucontrol->value.iec958.status[4] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) static int snd_ice1712_spdif_maskp_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (ice->spdif.ops.default_get) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) IEC958_AES0_PROFESSIONAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) IEC958_AES0_PRO_FS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) IEC958_AES0_PRO_EMPHASIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) ucontrol->value.iec958.status[1] = IEC958_AES1_PRO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) ucontrol->value.iec958.status[0] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) ucontrol->value.iec958.status[1] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ucontrol->value.iec958.status[2] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) ucontrol->value.iec958.status[3] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) ucontrol->value.iec958.status[4] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static const struct snd_kcontrol_new snd_ice1712_spdif_maskc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .info = snd_ice1712_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .get = snd_ice1712_spdif_maskc_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) static const struct snd_kcontrol_new snd_ice1712_spdif_maskp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .info = snd_ice1712_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .get = snd_ice1712_spdif_maskp_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static int snd_ice1712_spdif_stream_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (ice->spdif.ops.stream_get)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) ice->spdif.ops.stream_get(ice, ucontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) static int snd_ice1712_spdif_stream_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) if (ice->spdif.ops.stream_put)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) return ice->spdif.ops.stream_put(ice, ucontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static const struct snd_kcontrol_new snd_ice1712_spdif_stream =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) SNDRV_CTL_ELEM_ACCESS_INACTIVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .info = snd_ice1712_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .get = snd_ice1712_spdif_stream_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .put = snd_ice1712_spdif_stream_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) unsigned char mask = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) snd_ice1712_save_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) ucontrol->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) (snd_ice1712_gpio_read(ice) & mask ? 1 : 0) ^ invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) snd_ice1712_restore_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) unsigned char mask = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) unsigned int val, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (kcontrol->private_value & (1 << 31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) nval = (ucontrol->value.integer.value[0] ? mask : 0) ^ invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) snd_ice1712_save_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) val = snd_ice1712_gpio_read(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) nval |= val & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (val != nval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) snd_ice1712_gpio_write(ice, nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) snd_ice1712_restore_gpio_status(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) return val != nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) static int snd_ice1712_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static const char * const texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) "8000", /* 0: 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) "9600", /* 1: 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) "11025", /* 2: 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) "12000", /* 3: 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) "16000", /* 4: 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) "22050", /* 5: 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) "24000", /* 6: 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) "32000", /* 7: 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) "44100", /* 8: 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) "48000", /* 9: 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) "64000", /* 10: 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) "88200", /* 11: 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) "96000", /* 12: 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) "IEC958 Input", /* 13: -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return snd_ctl_enum_info(uinfo, 1, 14, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static int snd_ice1712_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static const unsigned char xlate[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) 9, 6, 3, 1, 7, 4, 0, 12, 8, 5, 2, 11, 255, 255, 255, 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if (is_spdif_master(ice)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) ucontrol->value.enumerated.item[0] = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) val = xlate[inb(ICEMT(ice, RATE)) & 15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) if (val == 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ucontrol->value.enumerated.item[0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) static int snd_ice1712_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static const unsigned int xrate[13] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) 8000, 9600, 11025, 12000, 16000, 22050, 24000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) 32000, 44100, 48000, 64000, 88200, 96000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) unsigned char oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) oval = inb(ICEMT(ice, RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (ucontrol->value.enumerated.item[0] == 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) outb(oval | ICE1712_SPDIF_MASTER, ICEMT(ice, RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) change = inb(ICEMT(ice, RATE)) != oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) if ((oval & ICE1712_SPDIF_MASTER) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) snd_ice1712_set_input_clock_source(ice, is_spdif_master(ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) static const struct snd_kcontrol_new snd_ice1712_pro_internal_clock = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .name = "Multi Track Internal Clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .info = snd_ice1712_pro_internal_clock_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .get = snd_ice1712_pro_internal_clock_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .put = snd_ice1712_pro_internal_clock_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) static int snd_ice1712_pro_internal_clock_default_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) static const char * const texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) "8000", /* 0: 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) "9600", /* 1: 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) "11025", /* 2: 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) "12000", /* 3: 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) "16000", /* 4: 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) "22050", /* 5: 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) "24000", /* 6: 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) "32000", /* 7: 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) "44100", /* 8: 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) "48000", /* 9: 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) "64000", /* 10: 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) "88200", /* 11: 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) "96000", /* 12: 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) /* "IEC958 Input", 13: -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) return snd_ctl_enum_info(uinfo, 1, 13, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static int snd_ice1712_pro_internal_clock_default_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) static const unsigned int xrate[13] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) 8000, 9600, 11025, 12000, 16000, 22050, 24000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) 32000, 44100, 48000, 64000, 88200, 96000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) for (val = 0; val < 13; val++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (xrate[val] == PRO_RATE_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) ucontrol->value.enumerated.item[0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) static int snd_ice1712_pro_internal_clock_default_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static const unsigned int xrate[13] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) 8000, 9600, 11025, 12000, 16000, 22050, 24000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) 32000, 44100, 48000, 64000, 88200, 96000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) unsigned char oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) oval = PRO_RATE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) change = PRO_RATE_DEFAULT != oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static const struct snd_kcontrol_new snd_ice1712_pro_internal_clock_default = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .name = "Multi Track Internal Clock Default",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .info = snd_ice1712_pro_internal_clock_default_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .get = snd_ice1712_pro_internal_clock_default_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .put = snd_ice1712_pro_internal_clock_default_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) #define snd_ice1712_pro_rate_locking_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static int snd_ice1712_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static int snd_ice1712_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) int change = 0, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) nval = ucontrol->value.integer.value[0] ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) change = PRO_RATE_LOCKED != nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) PRO_RATE_LOCKED = nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static const struct snd_kcontrol_new snd_ice1712_pro_rate_locking = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .name = "Multi Track Rate Locking",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .info = snd_ice1712_pro_rate_locking_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .get = snd_ice1712_pro_rate_locking_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .put = snd_ice1712_pro_rate_locking_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) #define snd_ice1712_pro_rate_reset_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) static int snd_ice1712_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) ucontrol->value.integer.value[0] = PRO_RATE_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) static int snd_ice1712_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) int change = 0, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) nval = ucontrol->value.integer.value[0] ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) change = PRO_RATE_RESET != nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) PRO_RATE_RESET = nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) static const struct snd_kcontrol_new snd_ice1712_pro_rate_reset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .name = "Multi Track Rate Reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .info = snd_ice1712_pro_rate_reset_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .get = snd_ice1712_pro_rate_reset_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .put = snd_ice1712_pro_rate_reset_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) * routing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) static int snd_ice1712_pro_route_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) static const char * const texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) "PCM Out", /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) "H/W In 0", "H/W In 1", "H/W In 2", "H/W In 3", /* 1-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) "H/W In 4", "H/W In 5", "H/W In 6", "H/W In 7", /* 5-8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) "IEC958 In L", "IEC958 In R", /* 9-10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) "Digital Mixer", /* 11 - optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) int num_items = snd_ctl_get_ioffidx(kcontrol, &uinfo->id) < 2 ? 12 : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) return snd_ctl_enum_info(uinfo, 1, num_items, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) static int snd_ice1712_pro_route_analog_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) unsigned int val, cval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) val = inw(ICEMT(ice, ROUTE_PSDOUT03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) cval = inl(ICEMT(ice, ROUTE_CAPTURE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) val >>= ((idx % 2) * 8) + ((idx / 2) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) val &= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) cval >>= ((idx / 2) * 8) + ((idx % 2) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) if (val == 1 && idx < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) ucontrol->value.enumerated.item[0] = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) else if (val == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) else if (val == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) ucontrol->value.enumerated.item[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static int snd_ice1712_pro_route_analog_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) int change, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) unsigned int val, old_val, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) /* update PSDOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) if (ucontrol->value.enumerated.item[0] >= 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) nval = idx < 2 ? 1 : 0; /* dig mixer (or pcm) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) else if (ucontrol->value.enumerated.item[0] >= 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) nval = 3; /* spdif in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) else if (ucontrol->value.enumerated.item[0] >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) nval = 2; /* analog in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) nval = 0; /* pcm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) shift = ((idx % 2) * 8) + ((idx / 2) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) val = old_val = inw(ICEMT(ice, ROUTE_PSDOUT03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) val &= ~(0x03 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) val |= nval << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) change = val != old_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) outw(val, ICEMT(ice, ROUTE_PSDOUT03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) if (nval < 2) /* dig mixer of pcm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) /* update CAPTURE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) val = old_val = inl(ICEMT(ice, ROUTE_CAPTURE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) shift = ((idx / 2) * 8) + ((idx % 2) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if (nval == 2) { /* analog in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) nval = ucontrol->value.enumerated.item[0] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) val &= ~(0x07 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) val |= nval << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) } else { /* spdif in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) val &= ~(0x08 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) val |= nval << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) if (val != old_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) outl(val, ICEMT(ice, ROUTE_CAPTURE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) static int snd_ice1712_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) unsigned int val, cval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) val = inw(ICEMT(ice, ROUTE_SPDOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) cval = (val >> (idx * 4 + 8)) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) val = (val >> (idx * 2)) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (val == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) ucontrol->value.enumerated.item[0] = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) else if (val == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) else if (val == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) ucontrol->value.enumerated.item[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) static int snd_ice1712_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) int change, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) unsigned int val, old_val, nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) /* update SPDOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) val = old_val = inw(ICEMT(ice, ROUTE_SPDOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (ucontrol->value.enumerated.item[0] >= 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) nval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) else if (ucontrol->value.enumerated.item[0] >= 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) nval = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) else if (ucontrol->value.enumerated.item[0] >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) nval = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) nval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) shift = idx * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) val &= ~(0x03 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) val |= nval << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) shift = idx * 4 + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (nval == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) nval = ucontrol->value.enumerated.item[0] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) val &= ~(0x07 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) val |= nval << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) } else if (nval == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) val &= ~(0x08 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) val |= nval << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) change = val != old_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) outw(val, ICEMT(ice, ROUTE_SPDOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) static const struct snd_kcontrol_new snd_ice1712_mixer_pro_analog_route = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .name = "H/W Playback Route",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .info = snd_ice1712_pro_route_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .get = snd_ice1712_pro_route_analog_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .put = snd_ice1712_pro_route_analog_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) static const struct snd_kcontrol_new snd_ice1712_mixer_pro_spdif_route = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .info = snd_ice1712_pro_route_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .get = snd_ice1712_pro_route_spdif_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .put = snd_ice1712_pro_route_spdif_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) static int snd_ice1712_pro_volume_rate_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) uinfo->value.integer.max = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) static int snd_ice1712_pro_volume_rate_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) static int snd_ice1712_pro_volume_rate_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) change = inb(ICEMT(ice, MONITOR_RATE)) != ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) outb(ucontrol->value.integer.value[0], ICEMT(ice, MONITOR_RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) static const struct snd_kcontrol_new snd_ice1712_mixer_pro_volume_rate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .name = "Multi Track Volume Rate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .info = snd_ice1712_pro_volume_rate_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .get = snd_ice1712_pro_volume_rate_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .put = snd_ice1712_pro_volume_rate_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) static int snd_ice1712_pro_peak_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) uinfo->count = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) uinfo->value.integer.max = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) static int snd_ice1712_pro_peak_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) for (idx = 0; idx < 22; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) outb(idx, ICEMT(ice, MONITOR_PEAKINDEX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) ucontrol->value.integer.value[idx] = inb(ICEMT(ice, MONITOR_PEAKDATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) static const struct snd_kcontrol_new snd_ice1712_mixer_pro_peak = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .name = "Multi Track Peak",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .info = snd_ice1712_pro_peak_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .get = snd_ice1712_pro_peak_get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) * list of available boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) static const struct snd_ice1712_card_info *card_tables[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) snd_ice1712_hoontech_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) snd_ice1712_delta_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) snd_ice1712_ews_cards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) static unsigned char snd_ice1712_read_i2c(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) unsigned char dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) unsigned char addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) long t = 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) outb(addr, ICEREG(ice, I2C_BYTE_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) outb(dev & ~ICE1712_I2C_WRITE, ICEREG(ice, I2C_DEV_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) while (t-- > 0 && (inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_BUSY)) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) return inb(ICEREG(ice, I2C_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) static int snd_ice1712_read_eeprom(struct snd_ice1712 *ice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) const char *modelname)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) int dev = ICE_I2C_EEPROM_ADDR; /* I2C EEPROM device address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) unsigned int i, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) const struct snd_ice1712_card_info * const *tbl, *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) if (!modelname || !*modelname) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) ice->eeprom.subvendor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) if ((inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_EEPROM) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) ice->eeprom.subvendor = (snd_ice1712_read_i2c(ice, dev, 0x00) << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) (snd_ice1712_read_i2c(ice, dev, 0x01) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) (snd_ice1712_read_i2c(ice, dev, 0x02) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) (snd_ice1712_read_i2c(ice, dev, 0x03) << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) if (ice->eeprom.subvendor == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) ice->eeprom.subvendor == (unsigned int)-1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) /* invalid subvendor from EEPROM, try the PCI subststem ID instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) u16 vendor, device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) ice->eeprom.subvendor = ((unsigned int)swab16(vendor) << 16) | swab16(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) if (ice->eeprom.subvendor == 0 || ice->eeprom.subvendor == (unsigned int)-1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) dev_err(ice->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) "No valid ID is found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) for (tbl = card_tables; *tbl; tbl++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) for (c = *tbl; c->subvendor; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) if (modelname && c->model && !strcmp(modelname, c->model)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) dev_info(ice->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) "Using board model %s\n", c->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) ice->eeprom.subvendor = c->subvendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) } else if (c->subvendor != ice->eeprom.subvendor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) if (!c->eeprom_size || !c->eeprom_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) /* if the EEPROM is given by the driver, use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) dev_dbg(ice->card->dev, "using the defined eeprom..\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) ice->eeprom.version = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) ice->eeprom.size = c->eeprom_size + 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) goto read_skipped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) ice->eeprom.subvendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) ice->eeprom.size = snd_ice1712_read_i2c(ice, dev, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) if (ice->eeprom.size < 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) ice->eeprom.size = 32; /* FIXME: any cards without the correct size? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) else if (ice->eeprom.size > 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) dev_err(ice->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) "invalid EEPROM (size = %i)\n", ice->eeprom.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) ice->eeprom.version = snd_ice1712_read_i2c(ice, dev, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) if (ice->eeprom.version != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) dev_err(ice->card->dev, "invalid EEPROM version %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) ice->eeprom.version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) /* return -EIO; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) size = ice->eeprom.size - 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) for (i = 0; i < size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) ice->eeprom.data[i] = snd_ice1712_read_i2c(ice, dev, i + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) read_skipped:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) ice->eeprom.gpiomask = ice->eeprom.data[ICE_EEP1_GPIO_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) ice->eeprom.gpiostate = ice->eeprom.data[ICE_EEP1_GPIO_STATE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) ice->eeprom.gpiodir = ice->eeprom.data[ICE_EEP1_GPIO_DIR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) static int snd_ice1712_chip_init(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) outb(ICE1712_RESET | ICE1712_NATIVE, ICEREG(ice, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) outb(ICE1712_NATIVE, ICEREG(ice, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_DMX6FIRE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) !ice->dxr_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) /* Set eeprom value to limit active ADCs and DACs to 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) * Also disable AC97 as no hardware in standard 6fire card/box
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) * Note: DXR extensions are not currently supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) ice->eeprom.data[ICE_EEP1_CODEC] = 0x3a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) pci_write_config_byte(ice->pci, 0x60, ice->eeprom.data[ICE_EEP1_CODEC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) pci_write_config_byte(ice->pci, 0x61, ice->eeprom.data[ICE_EEP1_ACLINK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) pci_write_config_byte(ice->pci, 0x62, ice->eeprom.data[ICE_EEP1_I2SID]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) pci_write_config_byte(ice->pci, 0x63, ice->eeprom.data[ICE_EEP1_SPDIF]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) if (ice->eeprom.subvendor != ICE1712_SUBDEVICE_STDSP24 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) ice->eeprom.subvendor != ICE1712_SUBDEVICE_STAUDIO_ADCIII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) ice->gpio.write_mask = ice->eeprom.gpiomask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) ice->gpio.direction = ice->eeprom.gpiodir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) ice->eeprom.gpiomask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) ice->eeprom.gpiodir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) ice->eeprom.gpiostate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) ice->gpio.write_mask = 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) ice->gpio.direction = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) ICE1712_STDSP24_CLOCK_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) snd_ice1712_write(ice, ICE1712_IREG_PRO_POWERDOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) if (!(ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) outb(ICE1712_AC97_WARM, ICEREG(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) outb(0, ICEREG(ice, AC97_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) snd_ice1712_write(ice, ICE1712_IREG_CONSUMER_POWERDOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) snd_ice1712_set_pro_rate(ice, 48000, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) /* unmask used interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) outb(((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) == 0 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) ICE1712_IRQ_MPU2 : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) ((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) ICE1712_IRQ_PBKDS | ICE1712_IRQ_CONCAP | ICE1712_IRQ_CONPBK : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) ICEREG(ice, IRQMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) outb(0x00, ICEMT(ice, IRQ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) if (snd_BUG_ON(!ice->pcm_pro))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_default, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) kctl->id.device = ice->pcm_pro->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskc, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) kctl->id.device = ice->pcm_pro->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskp, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) kctl->id.device = ice->pcm_pro->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_stream, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) kctl->id.device = ice->pcm_pro->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) ice->spdif.stream_ctl = kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) static int snd_ice1712_build_controls(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_eeprom, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock_default, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_locking, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_reset, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) if (ice->num_total_dacs > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) struct snd_kcontrol_new tmp = snd_ice1712_mixer_pro_analog_route;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) tmp.count = ice->num_total_dacs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_volume_rate, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) return snd_ctl_add(ice->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) snd_ctl_new1(&snd_ice1712_mixer_pro_peak, ice));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) static int snd_ice1712_free(struct snd_ice1712 *ice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) if (!ice->port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) goto __hw_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) /* mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) outb(ICE1712_MULTI_CAPTURE | ICE1712_MULTI_PLAYBACK, ICEMT(ice, IRQ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) outb(0xff, ICEREG(ice, IRQMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) /* --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) __hw_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) if (ice->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) free_irq(ice->irq, ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) if (ice->port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) pci_release_regions(ice->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) snd_ice1712_akm4xxx_free(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) pci_disable_device(ice->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) kfree(ice->spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) kfree(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) static int snd_ice1712_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) struct snd_ice1712 *ice = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) return snd_ice1712_free(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) static int snd_ice1712_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) const char *modelname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) int omni,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) int cs8427_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) int dxr_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) struct snd_ice1712 **r_ice1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) struct snd_ice1712 *ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .dev_free = snd_ice1712_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) *r_ice1712 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) /* enable PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) err = pci_enable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) /* check, if we can restrict PCI DMA transfers to 28 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) if (dma_set_mask(&pci->dev, DMA_BIT_MASK(28)) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(28)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) dev_err(card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) "architecture does not support 28bit PCI busmaster DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) ice = kzalloc(sizeof(*ice), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) if (ice == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) ice->omni = omni ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) if (cs8427_timeout < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) cs8427_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) else if (cs8427_timeout > 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) cs8427_timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) ice->cs8427_timeout = cs8427_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) ice->dxr_enable = dxr_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) spin_lock_init(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) mutex_init(&ice->gpio_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) mutex_init(&ice->i2c_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) mutex_init(&ice->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) ice->gpio.set_mask = snd_ice1712_set_gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) ice->gpio.get_mask = snd_ice1712_get_gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) ice->gpio.set_dir = snd_ice1712_set_gpio_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) ice->gpio.get_dir = snd_ice1712_get_gpio_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) ice->gpio.set_data = snd_ice1712_set_gpio_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) ice->gpio.get_data = snd_ice1712_get_gpio_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) ice->spdif.cs8403_bits =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) ice->spdif.cs8403_stream_bits = (0x01 | /* consumer format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) 0x10 | /* no emphasis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) 0x20); /* PCM encoder/decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) ice->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) ice->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) ice->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) /* disable legacy emulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) pci_write_config_word(ice->pci, 0x40, 0x807f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) pci_write_config_word(ice->pci, 0x42, 0x0006);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) snd_ice1712_proc_init(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) card->private_data = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) err = pci_request_regions(pci, "ICE1712");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) kfree(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) ice->port = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) ice->ddma_port = pci_resource_start(pci, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) ice->dmapath_port = pci_resource_start(pci, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) ice->profi_port = pci_resource_start(pci, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) if (request_irq(pci->irq, snd_ice1712_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) KBUILD_MODNAME, ice)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) snd_ice1712_free(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) ice->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) card->sync_irq = ice->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) if (snd_ice1712_read_eeprom(ice, modelname) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) snd_ice1712_free(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) if (snd_ice1712_chip_init(ice) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) snd_ice1712_free(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) snd_ice1712_free(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) *r_ice1712 = ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) * Registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) static struct snd_ice1712_card_info no_matched;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) static int snd_ice1712_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) struct snd_ice1712 *ice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) int pcm_dev = 0, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) const struct snd_ice1712_card_info * const *tbl, *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) strcpy(card->driver, "ICE1712");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) strcpy(card->shortname, "ICEnsemble ICE1712");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) err = snd_ice1712_create(card, pci, model[dev], omni[dev],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) cs8427_timeout[dev], dxr_enable[dev], &ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) for (tbl = card_tables; *tbl; tbl++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) for (c = *tbl; c->subvendor; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) if (c->subvendor == ice->eeprom.subvendor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) ice->card_info = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) strcpy(card->shortname, c->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) if (c->driver) /* specific driver? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) strcpy(card->driver, c->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) if (c->chip_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) err = c->chip_init(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) goto __found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) c = &no_matched;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) __found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) err = snd_ice1712_pcm_profi(ice, pcm_dev++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) if (ice_has_con_ac97(ice)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) err = snd_ice1712_pcm(ice, pcm_dev++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) err = snd_ice1712_ac97_mixer(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) err = snd_ice1712_build_controls(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) if (c->build_controls) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) err = c->build_controls(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) if (ice_has_con_ac97(ice)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) err = snd_ice1712_pcm_ds(ice, pcm_dev++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) if (!c->no_mpu401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) ICEREG(ice, MPU1_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) c->mpu401_1_info_flags |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) -1, &ice->rmidi[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) if (c->mpu401_1_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) /* Preferred name available in card_info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) snprintf(ice->rmidi[0]->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) sizeof(ice->rmidi[0]->name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) "%s %d", c->mpu401_1_name, card->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) if (ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) /* 2nd port used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) err = snd_mpu401_uart_new(card, 1, MPU401_HW_ICE1712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) ICEREG(ice, MPU2_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) c->mpu401_2_info_flags |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) -1, &ice->rmidi[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) if (c->mpu401_2_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) /* Preferred name available in card_info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) snprintf(ice->rmidi[1]->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) sizeof(ice->rmidi[1]->name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) "%s %d", c->mpu401_2_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) card->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) snd_ice1712_set_input_clock_source(ice, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) sprintf(card->longname, "%s at 0x%lx, irq %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) card->shortname, ice->port, ice->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) static void snd_ice1712_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) struct snd_card *card = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) struct snd_ice1712 *ice = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) if (ice->card_info && ice->card_info->chip_exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) ice->card_info->chip_exit(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) static int snd_ice1712_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) struct snd_ice1712 *ice = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) if (!ice->pm_suspend_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) snd_ac97_suspend(ice->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) ice->pm_saved_is_spdif_master = is_spdif_master(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) ice->pm_saved_spdif_ctrl = inw(ICEMT(ice, ROUTE_SPDOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) ice->pm_saved_route = inw(ICEMT(ice, ROUTE_PSDOUT03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) if (ice->pm_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) ice->pm_suspend(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) static int snd_ice1712_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) struct snd_ice1712 *ice = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) if (!ice->pm_suspend_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) if (ice->cur_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) rate = ice->cur_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) rate = PRO_RATE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) if (snd_ice1712_chip_init(ice) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) snd_card_disconnect(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) ice->cur_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) if (ice->pm_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) ice->pm_resume(ice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) if (ice->pm_saved_is_spdif_master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) /* switching to external clock via SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) spin_lock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) outb(inb(ICEMT(ice, RATE)) | ICE1712_SPDIF_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) ICEMT(ice, RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) spin_unlock_irq(&ice->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) snd_ice1712_set_input_clock_source(ice, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) /* internal on-card clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) snd_ice1712_set_pro_rate(ice, rate, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) snd_ice1712_set_input_clock_source(ice, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) outw(ice->pm_saved_spdif_ctrl, ICEMT(ice, ROUTE_SPDOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) outw(ice->pm_saved_route, ICEMT(ice, ROUTE_PSDOUT03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) snd_ac97_resume(ice->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) static SIMPLE_DEV_PM_OPS(snd_ice1712_pm, snd_ice1712_suspend, snd_ice1712_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) #define SND_VT1712_PM_OPS &snd_ice1712_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) #define SND_VT1712_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) static struct pci_driver ice1712_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) .id_table = snd_ice1712_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) .probe = snd_ice1712_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) .remove = snd_ice1712_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) .pm = SND_VT1712_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) module_pci_driver(ice1712_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags