Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Universal Interface for Intel High Definition Audio Codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * HD audio interface patch for Silicon Labs 3054/5 modem codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (c) 2005 Sasha Khapyorsky <sashak@alsa-project.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *                    Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <sound/hda_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "hda_local.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* si3054 verbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SI3054_VERB_READ_NODE  0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SI3054_VERB_WRITE_NODE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* si3054 nodes (registers) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SI3054_EXTENDED_MID    2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SI3054_LINE_RATE       3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SI3054_LINE_LEVEL      4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SI3054_GPIO_CFG        5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SI3054_GPIO_POLARITY   6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SI3054_GPIO_STICKY     7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SI3054_GPIO_WAKEUP     8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SI3054_GPIO_STATUS     9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SI3054_GPIO_CONTROL   10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SI3054_MISC_AFE       11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SI3054_CHIPID         12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SI3054_LINE_CFG1      13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SI3054_LINE_STATUS    14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SI3054_DC_TERMINATION 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SI3054_LINE_CONFIG    16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SI3054_CALLPROG_ATT   17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SI3054_SQ_CONTROL     18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SI3054_MISC_CONTROL   19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SI3054_RING_CTRL1     20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SI3054_RING_CTRL2     21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* extended MID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SI3054_MEI_READY 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* line level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SI3054_ATAG_MASK 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SI3054_DTAG_MASK 0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* GPIO bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SI3054_GPIO_OH    0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SI3054_GPIO_CID   0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* chipid and revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SI3054_CHIPID_CODEC_REV_MASK 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SI3054_CHIPID_DAA_REV_MASK   0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SI3054_CHIPID_INTERNATIONAL  0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SI3054_CHIPID_DAA_ID         0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SI3054_CHIPID_CODEC_ID      (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* si3054 codec registers (nodes) access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define GET_REG(codec,reg) (snd_hda_codec_read(codec,reg,0,SI3054_VERB_READ_NODE,0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SET_REG(codec,reg,val) (snd_hda_codec_write(codec,reg,0,SI3054_VERB_WRITE_NODE,val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SET_REG_CACHE(codec,reg,val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	snd_hda_codec_write_cache(codec,reg,0,SI3054_VERB_WRITE_NODE,val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) struct si3054_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned international;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * Modem mixer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PRIVATE_VALUE(reg,mask) ((reg<<16)|(mask&0xffff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PRIVATE_REG(val) ((val>>16)&0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PRIVATE_MASK(val) (val&0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define si3054_switch_info	snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static int si3054_switch_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		               struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u16 reg  = PRIVATE_REG(kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u16 mask = PRIVATE_MASK(kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	uvalue->value.integer.value[0] = (GET_REG(codec, reg)) & mask ? 1 : 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static int si3054_switch_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		               struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u16 reg  = PRIVATE_REG(kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u16 mask = PRIVATE_MASK(kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (uvalue->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) | mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) & ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SI3054_KCONTROL(kname,reg,mask) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.name = kname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.subdevice = HDA_SUBDEV_NID_FLAG | reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.info = si3054_switch_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.get  = si3054_switch_get, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.put  = si3054_switch_put, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.private_value = PRIVATE_VALUE(reg,mask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct snd_kcontrol_new si3054_modem_mixer[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	SI3054_KCONTROL("Off-hook Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_OH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	SI3054_KCONTROL("Caller ID Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_CID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int si3054_build_controls(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return snd_hda_add_new_ctls(codec, si3054_modem_mixer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * PCM callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int si3054_pcm_prepare(struct hda_pcm_stream *hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			      struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			      unsigned int stream_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			      unsigned int format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			      struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	SET_REG(codec, SI3054_LINE_RATE, substream->runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	val = GET_REG(codec, SI3054_LINE_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	val &= 0xff << (8 * (substream->stream != SNDRV_PCM_STREAM_PLAYBACK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	val |= ((stream_tag & 0xf) << 4) << (8 * (substream->stream == SNDRV_PCM_STREAM_PLAYBACK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	SET_REG(codec, SI3054_LINE_LEVEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	snd_hda_codec_setup_stream(codec, hinfo->nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				   stream_tag, 0, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int si3054_pcm_open(struct hda_pcm_stream *hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			   struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			    struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	static const unsigned int rates[] = { 8000, 9600, 16000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		.count = ARRAY_SIZE(rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.list = rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	substream->runtime->hw.period_bytes_min = 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return snd_pcm_hw_constraint_list(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct hda_pcm_stream si3054_pcm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.substreams = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.nid = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_KNOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.maxbps = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.open = si3054_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		.prepare = si3054_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int si3054_build_pcms(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct hda_pcm *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	info = snd_hda_codec_pcm_new(codec, "Si3054 Modem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	info->stream[SNDRV_PCM_STREAM_PLAYBACK] = si3054_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	info->stream[SNDRV_PCM_STREAM_CAPTURE]  = si3054_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = codec->core.mfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = codec->core.mfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	info->pcm_type = HDA_PCM_TYPE_MODEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * Init part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int si3054_init(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct si3054_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	unsigned wait_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (snd_hdac_regmap_add_vendor_verb(&codec->core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 					    SI3054_VERB_WRITE_NODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	snd_hda_codec_write(codec, AC_NODE_ROOT, 0, AC_VERB_SET_CODEC_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	snd_hda_codec_write(codec, codec->core.mfg, 0, AC_VERB_SET_STREAM_FORMAT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	SET_REG(codec, SI3054_LINE_RATE, 9600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	SET_REG(codec, SI3054_LINE_LEVEL, SI3054_DTAG_MASK|SI3054_ATAG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	SET_REG(codec, SI3054_EXTENDED_MID, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	wait_count = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		msleep(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		val = GET_REG(codec, SI3054_EXTENDED_MID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	} while ((val & SI3054_MEI_READY) != SI3054_MEI_READY && wait_count--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if((val&SI3054_MEI_READY) != SI3054_MEI_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		codec_err(codec, "si3054: cannot initialize. EXT MID = %04x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		/* let's pray that this is no fatal error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		/* return -EACCES; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	SET_REG(codec, SI3054_GPIO_POLARITY, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	SET_REG(codec, SI3054_GPIO_CFG, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	SET_REG(codec, SI3054_MISC_AFE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	SET_REG(codec, SI3054_LINE_CFG1,0x200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if((GET_REG(codec,SI3054_LINE_STATUS) & (1<<6)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		codec_dbg(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			  "Link Frame Detect(FDT) is not ready (line status: %04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 				GET_REG(codec,SI3054_LINE_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	spec->international = GET_REG(codec, SI3054_CHIPID) & SI3054_CHIPID_INTERNATIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void si3054_free(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	kfree(codec->spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const struct hda_codec_ops si3054_patch_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.build_controls = si3054_build_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.build_pcms = si3054_build_pcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.init = si3054_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.free = si3054_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int patch_si3054(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct si3054_spec *spec = kzalloc(sizeof(*spec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (spec == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	codec->spec = spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	codec->patch_ops = si3054_patch_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  * patch entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const struct hda_device_id snd_hda_id_si3054[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	HDA_CODEC_ENTRY(0x163c3055, "Si3054", patch_si3054),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	HDA_CODEC_ENTRY(0x163c3155, "Si3054", patch_si3054),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	HDA_CODEC_ENTRY(0x11c13026, "Si3054", patch_si3054),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	HDA_CODEC_ENTRY(0x11c13055, "Si3054", patch_si3054),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	HDA_CODEC_ENTRY(0x11c13155, "Si3054", patch_si3054),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	HDA_CODEC_ENTRY(0x10573055, "Si3054", patch_si3054),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	HDA_CODEC_ENTRY(0x10573057, "Si3054", patch_si3054),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	HDA_CODEC_ENTRY(0x10573155, "Si3054", patch_si3054),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/* VIA HDA on Clevo m540 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	HDA_CODEC_ENTRY(0x11063288, "Si3054", patch_si3054),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	/* Asus A8J Modem (SM56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	HDA_CODEC_ENTRY(0x15433155, "Si3054", patch_si3054),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	/* LG LW20 modem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	HDA_CODEC_ENTRY(0x18540018, "Si3054", patch_si3054),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_si3054);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MODULE_DESCRIPTION("Si3054 HD-audio modem codec");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct hda_codec_driver si3054_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.id = snd_hda_id_si3054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) module_hda_codec_driver(si3054_driver);