^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * patch_hdmi.c - routines for HDMI/DisplayPort codecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2006 ATI Technologies Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Wu Fengguang <wfg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Maintained by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Wu Fengguang <wfg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/jack.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <sound/hdaudio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <sound/hda_i915.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <sound/hda_chmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <sound/hda_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "hda_local.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "hda_jack.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "hda_controller.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static bool static_hdmi_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) module_param(static_hdmi_pcm, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static bool enable_acomp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) module_param(enable_acomp, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static bool enable_silent_stream =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) module_param(enable_silent_stream, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct hdmi_spec_per_cvt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) hda_nid_t cvt_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int assigned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int channels_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int channels_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u64 formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int maxbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* max. connections to a widget */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HDA_MAX_CONNECTIONS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct hdmi_spec_per_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) hda_nid_t pin_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* pin idx, different device entries on the same pin use the same idx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int pin_nid_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int num_mux_nids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int mux_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) hda_nid_t cvt_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct hda_codec *codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct hdmi_eld sink_eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct delayed_work work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int repoll_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) bool setup; /* the stream has been set up by prepare callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bool silent_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int channels; /* current number of channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bool non_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bool chmap_set; /* channel-map override by ALSA API? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned char chmap[8]; /* ALSA API channel-map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #ifdef CONFIG_SND_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct snd_info_entry *proc_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* operations used by generic code that can be overridden by patches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct hdmi_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int dev_id, unsigned char *buf, int *eld_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int ca, int active_channels, int conn_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* enable/disable HBR (HD passthrough) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int dev_id, bool hbr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) hda_nid_t pin_nid, int dev_id, u32 stream_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void (*pin_cvt_fixup)(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct hdmi_spec_per_pin *per_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) hda_nid_t cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct hdmi_pcm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct hda_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct snd_jack *jack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct snd_kcontrol *eld_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct hdmi_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct hda_codec *codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int num_cvts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct snd_array cvts; /* struct hdmi_spec_per_cvt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) hda_nid_t cvt_nids[4]; /* only for haswell fix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * num_pins is the number of virtual pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * for example, there are 3 pins, and each pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * has 4 device entries, then the num_pins is 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * num_nids is the number of real pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * In the above example, num_nids is 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int num_nids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * dev_num is the number of device entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * on each pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * In the above example, dev_num is 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct snd_array pins; /* struct hdmi_spec_per_pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct hdmi_pcm pcm_rec[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct mutex pcm_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct mutex bind_lock; /* for audio component binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* pcm_bitmap means which pcms have been assigned to pins*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned long pcm_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int pcm_used; /* counter of pcm_rec[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* bitmap shows whether the pcm is opened in user space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * bit 0 means the first playback PCM (PCM3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * bit 1 means the second playback PCM, and so on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long pcm_in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct hdmi_eld temp_eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct hdmi_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bool dyn_pin_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) bool dyn_pcm_assign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Non-generic VIA/NVIDIA specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct hda_multi_out multiout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct hda_pcm_stream pcm_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bool use_acomp_notifier; /* use eld_notify callback for hotplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) bool acomp_registered; /* audio component registered in this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bool force_connect; /* force connectivity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct drm_audio_component_audio_ops drm_audio_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct hdac_chmap chmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) hda_nid_t vendor_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const int *port_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) bool send_silent_stream; /* Flag to enable silent stream feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #ifdef CONFIG_SND_HDA_COMPONENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline bool codec_has_acomp(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return spec->use_acomp_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define codec_has_acomp(codec) false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct hdmi_audio_infoframe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u8 type; /* 0x84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u8 ver; /* 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 len; /* 0x0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u8 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 SS01_SF24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 CXT04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 CA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 LFEPBL01_LSV36_DM_INH7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct dp_audio_infoframe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 type; /* 0x84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 len; /* 0x1b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 ver; /* 0x11 << 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 CC02_CT47; /* match with HDMI infoframe from this on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 SS01_SF24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 CXT04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 CA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 LFEPBL01_LSV36_DM_INH7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) union audio_infoframe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct hdmi_audio_infoframe hdmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct dp_audio_infoframe dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u8 bytes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * HDMI routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define get_pin(spec, idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define get_cvt(spec, idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* obtain hdmi_pcm object assigned to idx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* obtain hda_pcm object assigned to idx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int pin_id_to_pin_index(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) hda_nid_t pin_nid, int dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int pin_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct hdmi_spec_per_pin *per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * (dev_id == -1) means it is NON-MST pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * return the first virtual pin on this port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (dev_id == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if ((per_pin->pin_nid == pin_nid) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (per_pin->dev_id == dev_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return pin_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int hinfo_to_pcm_index(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct hda_pcm_stream *hinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int pcm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return pcm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int hinfo_to_pin_index(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct hda_pcm_stream *hinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct hdmi_spec_per_pin *per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int pin_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (per_pin->pcm &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) per_pin->pcm->pcm->stream == hinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return pin_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) hinfo_to_pcm_index(codec, hinfo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int pcm_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct hdmi_spec_per_pin *per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) for (i = 0; i < spec->num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) per_pin = get_pin(spec, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (per_pin->pcm_idx == pcm_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int cvt_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return cvt_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct hdmi_spec_per_pin *per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct hdmi_eld *eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int pcm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pcm_idx = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mutex_lock(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) per_pin = pcm_idx_to_pin(spec, pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!per_pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* no pin is bound to the pcm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) uinfo->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) eld = &per_pin->sink_eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) uinfo->count = eld->eld_valid ? eld->eld_size : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mutex_unlock(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct hdmi_spec_per_pin *per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct hdmi_eld *eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int pcm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pcm_idx = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mutex_lock(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) per_pin = pcm_idx_to_pin(spec, pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (!per_pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* no pin is bound to the pcm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) memset(ucontrol->value.bytes.data, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ARRAY_SIZE(ucontrol->value.bytes.data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) eld = &per_pin->sink_eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) eld->eld_size > ELD_MAX_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) memset(ucontrol->value.bytes.data, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ARRAY_SIZE(ucontrol->value.bytes.data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (eld->eld_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) eld->eld_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mutex_unlock(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const struct snd_kcontrol_new eld_bytes_ctl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .name = "ELD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .info = hdmi_eld_ctl_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .get = hdmi_eld_ctl_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (!kctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) kctl->private_value = pcm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) kctl->id.device = device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* no pin nid is associated with the kctl now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * tbd: associate pin nid to eld ctl later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) err = snd_hda_ctl_add(codec, 0, kctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #ifdef BE_PARANOID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int *packet_index, int *byte_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) val = snd_hda_codec_read(codec, pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) AC_VERB_GET_HDMI_DIP_INDEX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *packet_index = val >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) *byte_index = val & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int packet_index, int byte_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) val = (packet_index << 5) | (byte_index & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int pin_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Unmute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) snd_hda_codec_write(codec, pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (spec->dyn_pin_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Disable pin out until stream is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pin_out = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Enable pin out: some machines with GM965 gets broken output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * when the pin is disabled or changed while using with HDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pin_out = PIN_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) snd_hda_codec_write(codec, pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * ELD proc files
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #ifdef CONFIG_SND_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static void print_eld_info(struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct hdmi_spec_per_pin *per_pin = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mutex_lock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) mutex_unlock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static void write_eld_info(struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct hdmi_spec_per_pin *per_pin = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mutex_lock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) mutex_unlock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct hda_codec *codec = per_pin->codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct snd_info_entry *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) err = snd_card_proc_new(codec->card, name, &entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) snd_info_set_text_ops(entry, per_pin, print_eld_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) entry->c.text.write = write_eld_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) entry->mode |= 0200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) per_pin->proc_entry = entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!per_pin->codec->bus->shutdown) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) snd_info_free_entry(per_pin->proc_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) per_pin->proc_entry = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * Audio InfoFrame routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * Enable Audio InfoFrame Transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static void hdmi_start_infoframe_trans(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) hda_nid_t pin_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) AC_DIPXMIT_BEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * Disable Audio InfoFrame Transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) hda_nid_t pin_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) AC_DIPXMIT_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #ifdef CONFIG_SND_DEBUG_VERBOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) size = snd_hdmi_get_eld_size(codec, pin_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) size = snd_hda_codec_read(codec, pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) AC_VERB_GET_HDMI_DIP_SIZE, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #ifdef BE_PARANOID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int pi, bi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) size = snd_hda_codec_read(codec, pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) AC_VERB_GET_HDMI_DIP_SIZE, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) hdmi_set_dip_index(codec, pin_nid, i, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) for (j = 1; j < 1000; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) hdmi_write_dip_byte(codec, pin_nid, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (pi != i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) codec_dbg(codec, "dip index %d: %d != %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) bi, pi, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (bi == 0) /* byte index wrapped around */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) codec_dbg(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) i, size, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u8 *bytes = (u8 *)hdmi_ai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u8 sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) hdmi_ai->checksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) for (i = 0; i < sizeof(*hdmi_ai); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) sum += bytes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) hdmi_ai->checksum = -sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) hda_nid_t pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u8 *dip, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) hdmi_debug_dip_size(codec, pin_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) for (i = 0; i < size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) hdmi_write_dip_byte(codec, pin_nid, dip[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u8 *dip, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) != AC_DIPXMIT_BEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) val = snd_hda_codec_read(codec, pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) AC_VERB_GET_HDMI_DIP_DATA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (val != dip[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int dev_id, unsigned char *buf, int *eld_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) snd_hda_set_dev_select(codec, nid, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return snd_hdmi_get_eld(codec, nid, buf, eld_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) hda_nid_t pin_nid, int dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int ca, int active_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) int conn_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) union audio_infoframe ai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) memset(&ai, 0, sizeof(ai));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (conn_type == 0) { /* HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) hdmi_ai->type = 0x84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) hdmi_ai->ver = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) hdmi_ai->len = 0x0a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) hdmi_ai->CC02_CT47 = active_channels - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) hdmi_ai->CA = ca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) hdmi_checksum_audio_infoframe(hdmi_ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) } else if (conn_type == 1) { /* DisplayPort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct dp_audio_infoframe *dp_ai = &ai.dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dp_ai->type = 0x84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dp_ai->len = 0x1b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dp_ai->ver = 0x11 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dp_ai->CC02_CT47 = active_channels - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dp_ai->CA = ca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) pin_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) snd_hda_set_dev_select(codec, pin_nid, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * sizeof(*dp_ai) to avoid partial match/update problems when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * the user switches between HDMI/DP monitors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) sizeof(ai))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) codec_dbg(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) active_channels, ca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) hdmi_stop_infoframe_trans(codec, pin_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) hdmi_fill_audio_infoframe(codec, pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ai.bytes, sizeof(ai));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) hdmi_start_infoframe_trans(codec, pin_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct hdmi_spec_per_pin *per_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) bool non_pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct hdac_chmap *chmap = &spec->chmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) hda_nid_t pin_nid = per_pin->pin_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int dev_id = per_pin->dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int channels = per_pin->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int active_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct hdmi_eld *eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int ca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (!channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) snd_hda_set_dev_select(codec, pin_nid, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) snd_hda_codec_write(codec, pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) AC_VERB_SET_AMP_GAIN_MUTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) AMP_OUT_UNMUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) eld = &per_pin->sink_eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ca = snd_hdac_channel_allocation(&codec->core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) eld->info.spk_alloc, channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) per_pin->chmap_set, non_pcm, per_pin->chmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) active_channels = snd_hdac_get_active_channels(ca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) active_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * always configure channel mapping, it may have been changed by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * user in the meantime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) snd_hdac_setup_channel_mapping(&spec->chmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) pin_nid, non_pcm, ca, channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) per_pin->chmap, per_pin->chmap_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ca, active_channels, eld->info.conn_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) per_pin->non_pcm = non_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * Unsolicited events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (pin_idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mutex_lock(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) hdmi_present_sense(get_pin(spec, pin_idx), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) mutex_unlock(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static void jack_callback(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct hda_jack_callback *jack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* stop polling when notification is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (codec_has_acomp(codec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) check_presence_and_report(codec, jack->nid, jack->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct hda_jack_tbl *jack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) jack->jack_dirty = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) codec_dbg(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) check_presence_and_report(codec, jack->nid, jack->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) codec_info(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) codec->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) subtag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) cp_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) cp_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* TODO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (cp_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (cp_ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct hda_jack_tbl *jack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (codec_has_acomp(codec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (codec->dp_mst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int dev_entry =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (!jack) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (subtag == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) hdmi_intrinsic_event(codec, res, jack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) hdmi_non_intrinsic_event(codec, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static void haswell_verify_D0(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) hda_nid_t cvt_nid, hda_nid_t nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * thus pins could only choose converter 0 for use. Make sure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * converters are in correct power state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) AC_PWRST_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) msleep(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * Callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* HBR should be Non-PCM, 8 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define is_hbr_format(format) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int dev_id, bool hbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int pinctl, new_pinctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) snd_hda_set_dev_select(codec, pin_nid, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pinctl = snd_hda_codec_read(codec, pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (pinctl < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return hbr ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) new_pinctl = pinctl & ~AC_PINCTL_EPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (hbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) new_pinctl |= AC_PINCTL_EPT_HBR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) new_pinctl |= AC_PINCTL_EPT_NATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) codec_dbg(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) pinctl == new_pinctl ? "" : "new-",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) new_pinctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (pinctl != new_pinctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) snd_hda_codec_write(codec, pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) AC_VERB_SET_PIN_WIDGET_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) new_pinctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) } else if (hbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) hda_nid_t pin_nid, int dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u32 stream_tag, int format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) unsigned int param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) is_hbr_format(format));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (spec->intel_hsw_fixup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * on recent platforms IEC Coding Type is required for HBR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * support, read current Digital Converter settings and set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * ICT bitfield if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) param = snd_hda_codec_read(codec, cvt_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) AC_VERB_GET_DIGI_CONVERT_1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) param = (param >> 16) & ~(AC_DIG3_ICT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* on recent platforms ICT mode is required for HBR support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (is_hbr_format(format))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) param |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) snd_hda_codec_write(codec, cvt_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) AC_VERB_SET_DIGI_CONVERT_3, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* Try to find an available converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * If pin_idx is less then zero, just try to find an available converter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * Otherwise, try to find an available converter and get the cvt mux index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * of the pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static int hdmi_choose_cvt(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) int pin_idx, int *cvt_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct hdmi_spec_per_pin *per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct hdmi_spec_per_cvt *per_cvt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) int cvt_idx, mux_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* pin_idx < 0 means no pin will be bound to the converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (pin_idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) per_pin = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (per_pin && per_pin->silent_stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (cvt_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) *cvt_id = cvt_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* Dynamically assign converter to stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) per_cvt = get_cvt(spec, cvt_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* Must not already be assigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (per_cvt->assigned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (per_pin == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* Must be in pin's mux's list of converters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* Not in mux list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (mux_idx == per_pin->num_mux_nids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* No free converters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (cvt_idx == spec->num_cvts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (per_pin != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) per_pin->mux_idx = mux_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (cvt_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) *cvt_id = cvt_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* Assure the pin select the right convetor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct hdmi_spec_per_pin *per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) hda_nid_t pin_nid = per_pin->pin_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) int mux_idx, curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) mux_idx = per_pin->mux_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) curr = snd_hda_codec_read(codec, pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) AC_VERB_GET_CONNECT_SEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (curr != mux_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) snd_hda_codec_write_cache(codec, pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) AC_VERB_SET_CONNECT_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) mux_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* get the mux index for the converter of the pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * converter's mux index is the same for all pins on Intel platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) hda_nid_t cvt_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) for (i = 0; i < spec->num_cvts; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (spec->cvt_nids[i] == cvt_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* Intel HDMI workaround to fix audio routing issue:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * For some Intel display codecs, pins share the same connection list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * So a conveter can be selected by multiple pins and playback on any of these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * pins will generate sound on the external display, because audio flows from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * the same converter to the display pipeline. Also muting one pin may make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * other pins have no sound output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * So this function assures that an assigned converter for a pin is not selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * by any other pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static void intel_not_share_assigned_cvt(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) hda_nid_t pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) int dev_id, int mux_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) hda_nid_t nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) int cvt_idx, curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct hdmi_spec_per_cvt *per_cvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct hdmi_spec_per_pin *per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) int pin_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* configure the pins connections */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) int dev_id_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) int dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * pin not connected to monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * no need to operate on it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (!per_pin->pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if ((per_pin->pin_nid == pin_nid) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) (per_pin->dev_id == dev_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * if per_pin->dev_id >= dev_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * snd_hda_get_dev_select() will fail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * and the following operation is unpredictable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * So skip this situation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (per_pin->dev_id >= dev_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) nid = per_pin->pin_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * Calling this function should not impact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * on the device entry selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * So let's save the dev id for each pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * and restore it when return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) dev_id_saved = snd_hda_get_dev_select(codec, nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) curr = snd_hda_codec_read(codec, nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) AC_VERB_GET_CONNECT_SEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (curr != mux_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) snd_hda_set_dev_select(codec, nid, dev_id_saved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* choose an unassigned converter. The conveters in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * connection list are in the same order as in the codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) per_cvt = get_cvt(spec, cvt_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (!per_cvt->assigned) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) codec_dbg(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) "choose cvt %d for pin nid %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) cvt_idx, nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) snd_hda_codec_write_cache(codec, nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) AC_VERB_SET_CONNECT_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) cvt_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) snd_hda_set_dev_select(codec, nid, dev_id_saved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* A wrapper of intel_not_share_asigned_cvt() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) int mux_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* On Intel platform, the mapping of converter nid to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * mux index of the pins are always the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * The pin nid may be 0, this means all pins will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * share the converter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (mux_idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /* skeleton caller of pin_cvt_fixup ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static void pin_cvt_fixup(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct hdmi_spec_per_pin *per_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) hda_nid_t cvt_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (spec->ops.pin_cvt_fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* called in hdmi_pcm_open when no pin is assigned to the PCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * in dyn_pcm_assign mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) int cvt_idx, pcm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct hdmi_spec_per_cvt *per_cvt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) pcm_idx = hinfo_to_pcm_index(codec, hinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (pcm_idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) err = hdmi_choose_cvt(codec, -1, &cvt_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) per_cvt = get_cvt(spec, cvt_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) per_cvt->assigned = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) hinfo->nid = per_cvt->cvt_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) set_bit(pcm_idx, &spec->pcm_in_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /* todo: setup spdif ctls assign */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /* Initially set the converter's capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) hinfo->channels_min = per_cvt->channels_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) hinfo->channels_max = per_cvt->channels_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) hinfo->rates = per_cvt->rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) hinfo->formats = per_cvt->formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) hinfo->maxbps = per_cvt->maxbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* Store the updated parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) runtime->hw.channels_min = hinfo->channels_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) runtime->hw.channels_max = hinfo->channels_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) runtime->hw.formats = hinfo->formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) runtime->hw.rates = hinfo->rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) snd_pcm_hw_constraint_step(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) SNDRV_PCM_HW_PARAM_CHANNELS, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * HDA PCM callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) int pin_idx, cvt_idx, pcm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) struct hdmi_spec_per_pin *per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct hdmi_eld *eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct hdmi_spec_per_cvt *per_cvt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* Validate hinfo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) pcm_idx = hinfo_to_pcm_index(codec, hinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (pcm_idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) mutex_lock(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) pin_idx = hinfo_to_pin_index(codec, hinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (!spec->dyn_pcm_assign) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (snd_BUG_ON(pin_idx < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* no pin is assigned to the PCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * PA need pcm open successfully when probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (pin_idx < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) per_cvt = get_cvt(spec, cvt_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* Claim converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) per_cvt->assigned = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) set_bit(pcm_idx, &spec->pcm_in_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) per_pin->cvt_nid = per_cvt->cvt_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) hinfo->nid = per_cvt->cvt_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* flip stripe flag for the assigned stream if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) azx_stream(get_azx_dev(substream))->stripe = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) AC_VERB_SET_CONNECT_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) per_pin->mux_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /* configure unused pins to choose other converters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) pin_cvt_fixup(codec, per_pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* Initially set the converter's capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) hinfo->channels_min = per_cvt->channels_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) hinfo->channels_max = per_cvt->channels_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) hinfo->rates = per_cvt->rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) hinfo->formats = per_cvt->formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) hinfo->maxbps = per_cvt->maxbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) eld = &per_pin->sink_eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /* Restrict capabilities by ELD if this isn't disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (!static_hdmi_pcm && eld->eld_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (hinfo->channels_min > hinfo->channels_max ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) !hinfo->rates || !hinfo->formats) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) per_cvt->assigned = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) hinfo->nid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) snd_hda_spdif_ctls_unassign(codec, pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* Store the updated parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) runtime->hw.channels_min = hinfo->channels_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) runtime->hw.channels_max = hinfo->channels_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) runtime->hw.formats = hinfo->formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) runtime->hw.rates = hinfo->rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) snd_pcm_hw_constraint_step(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) SNDRV_PCM_HW_PARAM_CHANNELS, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) mutex_unlock(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * HDA/HDMI auto parsing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) hda_nid_t pin_nid = per_pin->pin_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) int dev_id = per_pin->dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) int conns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) codec_warn(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) "HDMI: pin %d wcaps %#x does not support connection list\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) pin_nid, get_wcaps(codec, pin_nid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) snd_hda_set_dev_select(codec, pin_nid, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (spec->intel_hsw_fixup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) conns = spec->num_cvts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) memcpy(per_pin->mux_nids, spec->cvt_nids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) sizeof(hda_nid_t) * conns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) conns = snd_hda_get_raw_connections(codec, pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) per_pin->mux_nids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) HDA_MAX_CONNECTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) /* all the device entries on the same pin have the same conn list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) per_pin->num_mux_nids = conns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) struct hdmi_spec_per_pin *per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) * generic_hdmi_build_pcms() may allocate extra PCMs on some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * platforms (with maximum of 'num_nids + dev_num - 1')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) * if m==0. This guarantees that dynamic pcm assignments are compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) * with the legacy static per_pin-pcm assignment that existed in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) * days before DP-MST.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * Intel DP-MST prefers this legacy behavior for compatibility, too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return per_pin->pin_nid_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) i = spec->num_nids + (per_pin->dev_id - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /* have a second try; check the area over num_nids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) for (i = spec->num_nids; i < spec->pcm_used; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (!test_bit(i, &spec->pcm_bitmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /* the last try; check the empty slots in pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) for (i = 0; i < spec->num_nids; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (!test_bit(i, &spec->pcm_bitmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) struct hdmi_spec_per_pin *per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* pcm already be attached to the pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (per_pin->pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) idx = hdmi_find_pcm_slot(spec, per_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (idx == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) per_pin->pcm_idx = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) per_pin->pcm = get_hdmi_pcm(spec, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) set_bit(idx, &spec->pcm_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) struct hdmi_spec_per_pin *per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /* pcm already be detached from the pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (!per_pin->pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) idx = per_pin->pcm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) per_pin->pcm_idx = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) per_pin->pcm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (idx >= 0 && idx < spec->pcm_used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) clear_bit(idx, &spec->pcm_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) int mux_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (per_pin->mux_nids[mux_idx] == cvt_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) return mux_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct hdmi_spec_per_pin *per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) struct hda_codec *codec = per_pin->codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct hda_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) struct hda_pcm_stream *hinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) int mux_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) bool non_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) pcm = get_pcm_rec(spec, per_pin->pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (!pcm->pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /* hdmi audio only uses playback and one substream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) hinfo = pcm->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) substream = pcm->pcm->streams[0].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) per_pin->cvt_nid = hinfo->nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (mux_idx < per_pin->num_mux_nids) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) snd_hda_set_dev_select(codec, per_pin->pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) per_pin->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) AC_VERB_SET_CONNECT_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) mux_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (substream->runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) per_pin->channels = substream->runtime->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) per_pin->setup = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) per_pin->mux_idx = mux_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) struct hdmi_spec_per_pin *per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) per_pin->chmap_set = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) per_pin->setup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) per_pin->channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct hdmi_spec_per_pin *per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (per_pin->pcm_idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return spec->pcm_rec[per_pin->pcm_idx].jack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /* update per_pin ELD from the given new ELD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) * setup info frame and notification accordingly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * also notify ELD kctl and report jack status changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static void update_eld(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) struct hdmi_spec_per_pin *per_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) struct hdmi_eld *eld,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) int repoll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct hdmi_eld *pin_eld = &per_pin->sink_eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) struct snd_jack *pcm_jack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) bool old_eld_valid = pin_eld->eld_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) bool eld_changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) int pcm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (eld->eld_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (eld->eld_size <= 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) eld->eld_size) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) eld->eld_valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (repoll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) schedule_delayed_work(&per_pin->work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) msecs_to_jiffies(300));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (!eld->eld_valid || eld->eld_size <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) eld->eld_valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) eld->eld_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* for monitor disconnection, save pcm_idx firstly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) pcm_idx = per_pin->pcm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * pcm_idx >=0 before update_eld() means it is in monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) * disconnected event. Jack must be fetched before update_eld().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) if (spec->dyn_pcm_assign) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (eld->eld_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) hdmi_attach_hda_pcm(spec, per_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) hdmi_pcm_setup_pin(spec, per_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) hdmi_pcm_reset_pin(spec, per_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) hdmi_detach_hda_pcm(spec, per_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) /* if pcm_idx == -1, it means this is in monitor connection event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * we can get the correct pcm_idx now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (pcm_idx == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) pcm_idx = per_pin->pcm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (!pcm_jack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (eld->eld_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) snd_hdmi_show_eld(codec, &eld->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) eld_changed = (pin_eld->eld_valid != eld->eld_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (pin_eld->eld_size != eld->eld_size ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) memcmp(pin_eld->eld_buffer, eld->eld_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) eld->eld_size) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) eld_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (eld_changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) pin_eld->monitor_present = eld->monitor_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) pin_eld->eld_valid = eld->eld_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) pin_eld->eld_size = eld->eld_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (eld->eld_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) memcpy(pin_eld->eld_buffer, eld->eld_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) eld->eld_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) pin_eld->info = eld->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * Re-setup pin and infoframe. This is needed e.g. when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * - sink is first plugged-in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) * - transcoder can change during stream playback on Haswell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * and this can make HW reset converter selection on a pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) pin_cvt_fixup(codec, per_pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (eld_changed && pcm_idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) snd_ctl_notify(codec->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) SNDRV_CTL_EVENT_MASK_VALUE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) SNDRV_CTL_EVENT_MASK_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (eld_changed && pcm_jack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) snd_jack_report(pcm_jack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) (eld->monitor_present && eld->eld_valid) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) SND_JACK_AVOUT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) /* update ELD and jack state via HD-audio verbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) int repoll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) struct hda_codec *codec = per_pin->codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) struct hdmi_eld *eld = &spec->temp_eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) struct device *dev = hda_codec_dev(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) hda_nid_t pin_nid = per_pin->pin_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) int dev_id = per_pin->dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) * Always execute a GetPinSense verb here, even when called from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) * response's PD bit is not the real PD value, but indicates that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) * the real PD value changed. An older version of the HD-audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * specification worked this way. Hence, we just ignore the data in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) * the unsolicited response to avoid custom WARs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) int present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (dev->power.runtime_status == RPM_SUSPENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) ret = snd_hda_power_up_pm(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if (ret < 0 && pm_runtime_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) mutex_lock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (eld->monitor_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) eld->eld_valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) codec_dbg(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (eld->eld_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) eld->eld_buffer, &eld->eld_size) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) eld->eld_valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) update_eld(codec, per_pin, eld, repoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) mutex_unlock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) snd_hda_power_down_pm(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #define I915_SILENT_RATE 48000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) #define I915_SILENT_CHANNELS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) #define I915_SILENT_FORMAT_BITS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) #define I915_SILENT_FMT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static void silent_stream_enable(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) struct hdmi_spec_per_pin *per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) struct hdmi_spec_per_cvt *per_cvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) int cvt_idx, pin_idx, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) unsigned int format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) mutex_lock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (per_pin->setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) codec_dbg(codec, "hdmi: PCM already open, no silent stream\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) goto unlock_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) codec_err(codec, "hdmi: no free converter to enable silent mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) goto unlock_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) per_cvt = get_cvt(spec, cvt_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) per_cvt->assigned = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) per_pin->cvt_nid = per_cvt->cvt_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) per_pin->silent_stream = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) per_pin->pin_nid, per_cvt->cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) AC_VERB_SET_CONNECT_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) per_pin->mux_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /* configure unused pins to choose other converters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) pin_cvt_fixup(codec, per_pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) per_pin->dev_id, I915_SILENT_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) /* trigger silent stream generation in hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) snd_hda_codec_setup_stream(codec, per_pin->cvt_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) per_pin->channels = I915_SILENT_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) unlock_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) mutex_unlock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static void silent_stream_disable(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) struct hdmi_spec_per_pin *per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) struct hdmi_spec_per_cvt *per_cvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) int cvt_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) mutex_lock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (!per_pin->silent_stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) goto unlock_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) per_pin->pin_nid, per_pin->cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) per_cvt = get_cvt(spec, cvt_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) per_cvt->assigned = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) per_pin->cvt_nid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) per_pin->silent_stream = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) unlock_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) mutex_unlock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) /* update ELD and jack state via audio component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) static void sync_eld_via_acomp(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) struct hdmi_spec_per_pin *per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) struct hdmi_eld *eld = &spec->temp_eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) bool monitor_prev, monitor_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) mutex_lock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) eld->monitor_present = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) monitor_prev = per_pin->sink_eld.monitor_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) per_pin->dev_id, &eld->monitor_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) eld->eld_buffer, ELD_MAX_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) eld->eld_valid = (eld->eld_size > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) update_eld(codec, per_pin, eld, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) monitor_next = per_pin->sink_eld.monitor_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) mutex_unlock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) * Power-up will call hdmi_present_sense, so the PM calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) * have to be done without mutex held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (spec->send_silent_stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) int pm_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (!monitor_prev && monitor_next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) pm_ret = snd_hda_power_up_pm(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (pm_ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) codec_err(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) "Monitor plugged-in, Failed to power up codec ret=[%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) pm_ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) silent_stream_enable(codec, per_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) } else if (monitor_prev && !monitor_next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) silent_stream_disable(codec, per_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) pm_ret = snd_hda_power_down_pm(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) if (pm_ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) codec_err(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) "Monitor plugged-out, Failed to power down codec ret=[%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) pm_ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) struct hda_codec *codec = per_pin->codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (!codec_has_acomp(codec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) hdmi_present_sense_via_verbs(per_pin, repoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) sync_eld_via_acomp(codec, per_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) static void hdmi_repoll_eld(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) struct hdmi_spec_per_pin *per_pin =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct hda_codec *codec = per_pin->codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) struct hda_jack_tbl *jack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) per_pin->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (jack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) jack->jack_dirty = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (per_pin->repoll_count++ > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) per_pin->repoll_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) mutex_lock(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) hdmi_present_sense(per_pin, per_pin->repoll_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) mutex_unlock(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) unsigned int caps, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) int pin_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct hdmi_spec_per_pin *per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) int dev_num, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) caps = snd_hda_query_pin_caps(codec, pin_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) * For DP MST audio, Configuration Default is the same for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) * all device entries on the same pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) config = snd_hda_codec_get_pincfg(codec, pin_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) !spec->force_connect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) * To simplify the implementation, malloc all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) * the virtual pins in the initialization statically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (spec->intel_hsw_fixup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) * On Intel platforms, device entries number is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) * changed dynamically. If there is a DP MST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) * hub connected, the device entries number is 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) * Otherwise, it is 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) * Here we manually set dev_num to 3, so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) * we can initialize all the device entries when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) * bootup statically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) dev_num = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) spec->dev_num = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) } else if (spec->dyn_pcm_assign && codec->dp_mst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) * spec->dev_num is the maxinum number of device entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) * among all the pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) spec->dev_num = (spec->dev_num > dev_num) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) spec->dev_num : dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) * If the platform doesn't support DP MST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) * manually set dev_num to 1. This means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) * the pin has only one device entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) dev_num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) spec->dev_num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) for (i = 0; i < dev_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) pin_idx = spec->num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) per_pin = snd_array_new(&spec->pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) if (!per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) if (spec->dyn_pcm_assign) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) per_pin->pcm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) per_pin->pcm_idx = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) per_pin->pcm_idx = pin_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) per_pin->pin_nid = pin_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) per_pin->pin_nid_idx = spec->num_nids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) per_pin->dev_id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) per_pin->non_pcm = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) snd_hda_set_dev_select(codec, pin_nid, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) err = hdmi_read_pin_conn(codec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) spec->num_pins++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) spec->num_nids++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) struct hdmi_spec_per_cvt *per_cvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) unsigned int chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) chans = get_wcaps(codec, cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) chans = get_wcaps_channels(chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) per_cvt = snd_array_new(&spec->cvts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) if (!per_cvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) per_cvt->cvt_nid = cvt_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) per_cvt->channels_min = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (chans <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) per_cvt->channels_max = chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if (chans > spec->chmap.channels_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) spec->chmap.channels_max = chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) err = snd_hda_query_supported_pcm(codec, cvt_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) &per_cvt->rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) &per_cvt->formats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) &per_cvt->maxbps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) spec->cvt_nids[spec->num_cvts] = cvt_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) spec->num_cvts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) static const struct snd_pci_quirk force_connect_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) static int hdmi_parse_codec(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) hda_nid_t start_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) unsigned int caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) int i, nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) const struct snd_pci_quirk *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) if (!start_nid || nodes < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) if (q && q->value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) spec->force_connect = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) * hdmi_add_pin() assumes total amount of converters to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) * be known, so first discover all converters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) for (i = 0; i < nodes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) hda_nid_t nid = start_nid + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) caps = get_wcaps(codec, nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) if (!(caps & AC_WCAP_DIGITAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) hdmi_add_cvt(codec, nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) /* discover audio pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) for (i = 0; i < nodes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) hda_nid_t nid = start_nid + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) caps = get_wcaps(codec, nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) if (!(caps & AC_WCAP_DIGITAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) if (get_wcaps_type(caps) == AC_WID_PIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) hdmi_add_pin(codec, nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) struct hda_spdif_out *spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) bool non_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) mutex_lock(&codec->spdif_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) /* Add sanity check to pass klockwork check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) * This should never happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (WARN_ON(spdif == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) mutex_unlock(&codec->spdif_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) mutex_unlock(&codec->spdif_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) return non_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) * HDMI callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) unsigned int stream_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) unsigned int format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) hda_nid_t cvt_nid = hinfo->nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) int pin_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) struct hdmi_spec_per_pin *per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) bool non_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) int pinctl, stripe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) mutex_lock(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) pin_idx = hinfo_to_pin_index(codec, hinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) if (spec->dyn_pcm_assign && pin_idx < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) /* when dyn_pcm_assign and pcm is not bound to a pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) * skip pin setup and return 0 to make audio playback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) * be ongoing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) pin_cvt_fixup(codec, NULL, cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) snd_hda_codec_setup_stream(codec, cvt_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) stream_tag, 0, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) if (snd_BUG_ON(pin_idx < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) /* Verify pin:cvt selections to avoid silent audio after S3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) * After S3, the audio driver restores pin:cvt selections
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) * but this can happen before gfx is ready and such selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * is overlooked by HW. Thus multiple pins can share a same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) * default convertor and mute control will affect each other,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) * which can cause a resumed audio playback become silent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) * after S3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) pin_cvt_fixup(codec, per_pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) /* Todo: add DP1.2 MST audio support later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (codec_has_acomp(codec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) per_pin->dev_id, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) mutex_lock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) per_pin->channels = substream->runtime->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) per_pin->setup = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) snd_hda_codec_write(codec, cvt_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) AC_VERB_SET_STRIPE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) stripe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) mutex_unlock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (spec->dyn_pin_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) snd_hda_set_dev_select(codec, per_pin->pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) per_pin->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) snd_hda_codec_write(codec, per_pin->pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) AC_VERB_SET_PIN_WIDGET_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) pinctl | PIN_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) /* snd_hda_set_dev_select() has been called before */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) per_pin->dev_id, stream_tag, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) mutex_unlock(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) snd_hda_codec_cleanup_stream(codec, hinfo->nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) int cvt_idx, pin_idx, pcm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) struct hdmi_spec_per_cvt *per_cvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) struct hdmi_spec_per_pin *per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) int pinctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) mutex_lock(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) if (hinfo->nid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) pcm_idx = hinfo_to_pcm_index(codec, hinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) if (snd_BUG_ON(pcm_idx < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (snd_BUG_ON(cvt_idx < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) per_cvt = get_cvt(spec, cvt_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) per_cvt->assigned = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) hinfo->nid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) azx_stream(get_azx_dev(substream))->stripe = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) snd_hda_spdif_ctls_unassign(codec, pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) clear_bit(pcm_idx, &spec->pcm_in_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) pin_idx = hinfo_to_pin_index(codec, hinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (spec->dyn_pcm_assign && pin_idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) if (snd_BUG_ON(pin_idx < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) if (spec->dyn_pin_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) snd_hda_set_dev_select(codec, per_pin->pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) per_pin->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) snd_hda_codec_write(codec, per_pin->pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) AC_VERB_SET_PIN_WIDGET_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) pinctl & ~PIN_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) mutex_lock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) per_pin->chmap_set = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) per_pin->setup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) per_pin->channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) mutex_unlock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) mutex_unlock(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) static const struct hda_pcm_ops generic_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .open = hdmi_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .close = hdmi_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .prepare = generic_hdmi_playback_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .cleanup = generic_hdmi_playback_pcm_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) struct hda_codec *codec = hdac_to_hda_codec(hdac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if (!per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) return per_pin->sink_eld.info.spk_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) unsigned char *chmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) struct hda_codec *codec = hdac_to_hda_codec(hdac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) /* chmap is already set to 0 in caller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) if (!per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) unsigned char *chmap, int prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) struct hda_codec *codec = hdac_to_hda_codec(hdac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) if (!per_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) mutex_lock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) per_pin->chmap_set = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) if (prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) mutex_unlock(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) struct hda_codec *codec = hdac_to_hda_codec(hdac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) return per_pin ? true:false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) static int generic_hdmi_build_pcms(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) int idx, pcm_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) * for non-mst mode, pcm number is the same as before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) * for DP MST mode without extra PCM, pcm number is same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) * for DP MST mode with extra PCMs, pcm number is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) * (nid number + dev_num - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) * dev_num is the device entry number in a pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) if (codec->mst_no_extra_pcms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) pcm_num = spec->num_nids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) pcm_num = spec->num_nids + spec->dev_num - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) for (idx = 0; idx < pcm_num; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) struct hda_pcm *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) struct hda_pcm_stream *pstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) spec->pcm_rec[idx].pcm = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) spec->pcm_used++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) info->pcm_type = HDA_PCM_TYPE_HDMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) info->own_chmap = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) pstr->substreams = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) pstr->ops = generic_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) /* pcm number is less than 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) if (spec->pcm_used >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) /* other pstr fields are set in open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) static void free_hdmi_jack_priv(struct snd_jack *jack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) struct hdmi_pcm *pcm = jack->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) pcm->jack = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) char hdmi_str[32] = "HDMI/DP";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) struct snd_jack *jack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) if (pcmdev > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) if (!spec->dyn_pcm_assign &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) !is_jack_detectable(codec, per_pin->pin_nid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) strncat(hdmi_str, " Phantom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) sizeof(hdmi_str) - strlen(hdmi_str) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) spec->pcm_rec[pcm_idx].jack = jack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) jack->private_data = &spec->pcm_rec[pcm_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) jack->private_free = free_hdmi_jack_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) static int generic_hdmi_build_controls(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) int dev, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) int pin_idx, pcm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) if (!get_pcm_rec(spec, pcm_idx)->pcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) /* no PCM: mark this for skipping permanently */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) set_bit(pcm_idx, &spec->pcm_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) err = generic_hdmi_build_jack(codec, pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) /* create the spdif for each pcm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) * pin will be bound when monitor is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) if (spec->dyn_pcm_assign)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) err = snd_hda_create_dig_out_ctls(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) 0, spec->cvt_nids[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) HDA_PCM_TYPE_HDMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) struct hdmi_spec_per_pin *per_pin =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) get_pin(spec, pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) err = snd_hda_create_dig_out_ctls(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) per_pin->pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) per_pin->mux_nids[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) HDA_PCM_TYPE_HDMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) snd_hda_spdif_ctls_unassign(codec, pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) dev = get_pcm_rec(spec, pcm_idx)->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) if (dev != SNDRV_PCM_INVALID_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) /* add control for ELD Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) struct hdmi_eld *pin_eld = &per_pin->sink_eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) pin_eld->eld_valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) hdmi_present_sense(per_pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) /* add channel maps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) struct hda_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) pcm = get_pcm_rec(spec, pcm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) if (!pcm || !pcm->pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) static int generic_hdmi_init_per_pins(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) int pin_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) per_pin->codec = codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) mutex_init(&per_pin->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) eld_proc_new(per_pin, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) static int generic_hdmi_init(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) int pin_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) mutex_lock(&spec->bind_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) hda_nid_t pin_nid = per_pin->pin_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) int dev_id = per_pin->dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) snd_hda_set_dev_select(codec, pin_nid, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) hdmi_init_pin(codec, pin_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) if (codec_has_acomp(codec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) jack_callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) mutex_unlock(&spec->bind_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static void hdmi_array_init(struct hdmi_spec *spec, int nums)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) static void hdmi_array_free(struct hdmi_spec *spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) snd_array_free(&spec->pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) snd_array_free(&spec->cvts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) static void generic_spec_free(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) if (spec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) hdmi_array_free(spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) kfree(spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) codec->spec = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) codec->dp_mst = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) static void generic_hdmi_free(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) int pin_idx, pcm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) if (spec->acomp_registered) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) snd_hdac_acomp_exit(&codec->bus->core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) } else if (codec_has_acomp(codec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) codec->relaxed_resume = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) cancel_delayed_work_sync(&per_pin->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) eld_proc_free(per_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) if (spec->pcm_rec[pcm_idx].jack == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) if (spec->dyn_pcm_assign)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) snd_device_free(codec->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) spec->pcm_rec[pcm_idx].jack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) spec->pcm_rec[pcm_idx].jack = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) generic_spec_free(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) static int generic_hdmi_suspend(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) int pin_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) cancel_delayed_work_sync(&per_pin->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) static int generic_hdmi_resume(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) int pin_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) codec->patch_ops.init(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) snd_hda_regmap_sync(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) hdmi_present_sense(per_pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) static const struct hda_codec_ops generic_hdmi_patch_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .init = generic_hdmi_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .free = generic_hdmi_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .build_pcms = generic_hdmi_build_pcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .build_controls = generic_hdmi_build_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .unsol_event = hdmi_unsol_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .suspend = generic_hdmi_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .resume = generic_hdmi_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) static const struct hdmi_ops generic_standard_hdmi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .pin_get_eld = hdmi_pin_get_eld,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .pin_setup_infoframe = hdmi_pin_setup_infoframe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .pin_hbr_setup = hdmi_pin_hbr_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .setup_stream = hdmi_setup_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) /* allocate codec->spec and assign/initialize generic parser ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) static int alloc_generic_hdmi(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) struct hdmi_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) spec = kzalloc(sizeof(*spec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) if (!spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) spec->codec = codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) spec->ops = generic_standard_hdmi_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) spec->dev_num = 1; /* initialize to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) mutex_init(&spec->pcm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) mutex_init(&spec->bind_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) spec->chmap.ops.get_chmap = hdmi_get_chmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) spec->chmap.ops.set_chmap = hdmi_set_chmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) codec->spec = spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) hdmi_array_init(spec, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) codec->patch_ops = generic_hdmi_patch_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) /* generic HDMI parser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) static int patch_generic_hdmi(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) err = alloc_generic_hdmi(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) err = hdmi_parse_codec(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) generic_spec_free(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) generic_hdmi_init_per_pins(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) * generic audio component binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) /* turn on / off the unsol event jack detection dynamically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) int dev_id, bool use_acomp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) struct hda_jack_tbl *tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) if (tbl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) /* clear unsol even if component notifier is used, or re-enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) * if notifier is cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) snd_hda_codec_write_cache(codec, nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) AC_VERB_SET_UNSOLICITED_ENABLE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) /* set up / clear component notifier dynamically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) bool use_acomp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) struct hdmi_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) mutex_lock(&spec->bind_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) spec->use_acomp_notifier = use_acomp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) spec->codec->relaxed_resume = use_acomp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) spec->codec->bus->keep_power = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) /* reprogram each jack detection logic depending on the notifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) for (i = 0; i < spec->num_pins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) reprogram_jack_detect(spec->codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) get_pin(spec, i)->pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) get_pin(spec, i)->dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) use_acomp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) mutex_unlock(&spec->bind_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) /* enable / disable the notifier via master bind / unbind */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) static int generic_acomp_master_bind(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) struct drm_audio_component *acomp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) generic_acomp_notifier_set(acomp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) static void generic_acomp_master_unbind(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) struct drm_audio_component *acomp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) generic_acomp_notifier_set(acomp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) /* check whether both HD-audio and DRM PCI devices belong to the same bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static int match_bound_vga(struct device *dev, int subtype, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) struct hdac_bus *bus = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) struct pci_dev *pci, *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) master = to_pci_dev(bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) pci = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) return master->bus == pci->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) /* audio component notifier for AMD/Nvidia HDMI codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) struct hda_codec *codec = audio_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) hda_nid_t pin_nid = spec->port2pin(codec, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) if (!pin_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) /* skip notification during system suspend (but not in runtime PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) * the state will be updated at resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) /* ditto during suspend/resume process itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) if (snd_hdac_is_in_pm(&codec->core))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) check_presence_and_report(codec, pin_nid, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) /* set up the private drm_audio_ops from the template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) static void setup_drm_audio_ops(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) const struct drm_audio_component_audio_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) spec->drm_audio_ops.audio_ptr = codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) /* intel_audio_codec_enable() or intel_audio_codec_disable()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) * will call pin_eld_notify with using audio_ptr pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) * We need make sure audio_ptr is really setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) spec->drm_audio_ops.pin2port = ops->pin2port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) spec->drm_audio_ops.master_bind = ops->master_bind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) spec->drm_audio_ops.master_unbind = ops->master_unbind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) /* initialize the generic HDMI audio component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) static void generic_acomp_init(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) const struct drm_audio_component_audio_ops *ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) int (*port2pin)(struct hda_codec *, int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) if (!enable_acomp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) codec_info(codec, "audio component disabled by module option\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) spec->port2pin = port2pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) setup_drm_audio_ops(codec, ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) match_bound_vga, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) spec->acomp_registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) * Intel codec parsers and helpers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) #define INTEL_GET_VENDOR_VERB 0xf81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) #define INTEL_SET_VENDOR_VERB 0x781
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) static void intel_haswell_enable_all_pins(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) bool update_tree)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) unsigned int vendor_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) INTEL_GET_VENDOR_VERB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) vendor_param |= INTEL_EN_ALL_PIN_CVTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) INTEL_SET_VENDOR_VERB, vendor_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) if (vendor_param == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) if (update_tree)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) snd_hda_codec_update_widgets(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) unsigned int vendor_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) INTEL_GET_VENDOR_VERB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) /* enable DP1.2 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) vendor_param |= INTEL_EN_DP12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) INTEL_SET_VENDOR_VERB, vendor_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) * Otherwise you may get severe h/w communication errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) unsigned int power_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) if (power_state == AC_PWRST_D0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) intel_haswell_enable_all_pins(codec, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) intel_haswell_fixup_enable_dp12(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) snd_hda_codec_set_power_to_all(codec, fg, power_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) /* There is a fixed mapping between audio pin node and display port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) * Pin Widget 5 - PORT B (port = 1 in i915 driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) * Pin Widget 6 - PORT C (port = 2 in i915 driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) * Pin Widget 7 - PORT D (port = 3 in i915 driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) * on VLV, ILK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) * Pin Widget 4 - PORT B (port = 1 in i915 driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) * Pin Widget 5 - PORT C (port = 2 in i915 driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) * Pin Widget 6 - PORT D (port = 3 in i915 driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) static int intel_base_nid(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) switch (codec->core.vendor_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) case 0x80860054: /* ILK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) case 0x80862804: /* ILK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) case 0x80862882: /* VLV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) return 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) static int intel_pin2port(void *audio_ptr, int pin_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) struct hda_codec *codec = audio_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) int base_nid, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) if (!spec->port_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) base_nid = intel_base_nid(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) return pin_nid - base_nid + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) * looking for the pin number in the mapping table and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) * the index which indicate the port number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) for (i = 0; i < spec->port_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) if (pin_nid == spec->port_map[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) static int intel_port2pin(struct hda_codec *codec, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) if (!spec->port_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) /* we assume only from port-B to port-D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) if (port < 1 || port > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) return port + intel_base_nid(codec) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) if (port < 0 || port >= spec->port_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) return spec->port_map[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) struct hda_codec *codec = audio_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) int pin_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) int dev_id = pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) pin_nid = intel_port2pin(codec, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) if (!pin_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) /* skip notification during system suspend (but not in runtime PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) * the state will be updated at resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) /* ditto during suspend/resume process itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) if (snd_hdac_is_in_pm(&codec->core))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) snd_hdac_i915_set_bclk(&codec->bus->core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) check_presence_and_report(codec, pin_nid, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) static const struct drm_audio_component_audio_ops intel_audio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) .pin2port = intel_pin2port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) .pin_eld_notify = intel_pin_eld_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) /* register i915 component pin_eld_notify callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) static void register_i915_notifier(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) spec->use_acomp_notifier = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) spec->port2pin = intel_port2pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) setup_drm_audio_ops(codec, &intel_audio_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) snd_hdac_acomp_register_notifier(&codec->bus->core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) &spec->drm_audio_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) /* no need for forcible resume for jack check thanks to notifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) codec->relaxed_resume = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) /* setup_stream ops override for HSW+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) hda_nid_t pin_nid, int dev_id, u32 stream_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) int format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) haswell_verify_D0(codec, cvt_nid, pin_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) stream_tag, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) /* pin_cvt_fixup ops override for HSW+ and VLV+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) static void i915_pin_cvt_fixup(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) struct hdmi_spec_per_pin *per_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) hda_nid_t cvt_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) if (per_pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) snd_hda_set_dev_select(codec, per_pin->pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) per_pin->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) intel_verify_pin_cvt_connect(codec, per_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) per_pin->dev_id, per_pin->mux_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) /* precondition and allocation for Intel codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) static int alloc_intel_hdmi(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) /* requires i915 binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) if (!codec->bus->core.audio_component) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) /* set probe_id here to prevent generic fallback binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) err = alloc_generic_hdmi(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) /* no need to handle unsol events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) codec->patch_ops.unsol_event = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) /* parse and post-process for Intel codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) static int parse_intel_hdmi(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) int err, retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) err = hdmi_parse_codec(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) } while (err < 0 && retries--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) generic_spec_free(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) generic_hdmi_init_per_pins(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) register_i915_notifier(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) /* Intel Haswell and onwards; audio component with eld notifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) const int *port_map, int port_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) struct hdmi_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) err = alloc_intel_hdmi(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) codec->dp_mst = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) spec->dyn_pcm_assign = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) spec->vendor_nid = vendor_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) spec->port_map = port_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) spec->port_num = port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) spec->intel_hsw_fixup = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) intel_haswell_enable_all_pins(codec, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) intel_haswell_fixup_enable_dp12(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) codec->display_power_control = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) codec->patch_ops.set_power_state = haswell_set_power_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) codec->depop_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) codec->auto_runtime_pm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) spec->ops.setup_stream = i915_hsw_setup_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) * Enable silent stream feature, if it is enabled via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) * module param or Kconfig option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) if (enable_silent_stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) spec->send_silent_stream = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) return parse_intel_hdmi(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) static int patch_i915_hsw_hdmi(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) return intel_hsw_common_init(codec, 0x08, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) static int patch_i915_glk_hdmi(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) return intel_hsw_common_init(codec, 0x0b, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) static int patch_i915_icl_hdmi(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) * pin to port mapping table where the value indicate the pin number and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) * the index indicate the port number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) static int patch_i915_tgl_hdmi(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) * pin to port mapping table where the value indicate the pin number and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) * the index indicate the port number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) /* Intel Baytrail and Braswell; with eld notifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) static int patch_i915_byt_hdmi(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) struct hdmi_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) err = alloc_intel_hdmi(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) /* For Valleyview/Cherryview, only the display codec is in the display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) * power well and can use link_power ops to request/release the power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) codec->display_power_control = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) codec->depop_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) codec->auto_runtime_pm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) return parse_intel_hdmi(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) static int patch_i915_cpt_hdmi(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) err = alloc_intel_hdmi(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) return parse_intel_hdmi(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) * Shared non-generic implementations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) static int simple_playback_build_pcms(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) struct hda_pcm *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) unsigned int chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) struct hda_pcm_stream *pstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) struct hdmi_spec_per_cvt *per_cvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) per_cvt = get_cvt(spec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) chans = get_wcaps(codec, per_cvt->cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) chans = get_wcaps_channels(chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) info = snd_hda_codec_pcm_new(codec, "HDMI 0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) spec->pcm_rec[0].pcm = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) info->pcm_type = HDA_PCM_TYPE_HDMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) *pstr = spec->pcm_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) pstr->nid = per_cvt->cvt_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) if (pstr->channels_max <= 2 && chans && chans <= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) pstr->channels_max = chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) /* unsolicited event for jack sensing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) static void simple_hdmi_unsol_event(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) unsigned int res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) snd_hda_jack_set_dirty_all(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) snd_hda_jack_report_sync(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) /* generic_hdmi_build_jack can be used for simple_hdmi, too,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) * as long as spec->pins[] is set correctly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) #define simple_hdmi_build_jack generic_hdmi_build_jack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) static int simple_playback_build_controls(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) struct hdmi_spec_per_cvt *per_cvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) per_cvt = get_cvt(spec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) per_cvt->cvt_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) HDA_PCM_TYPE_HDMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) return simple_hdmi_build_jack(codec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) static int simple_playback_init(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) hda_nid_t pin = per_pin->pin_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) snd_hda_codec_write(codec, pin, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) /* some codecs require to unmute the pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) AMP_OUT_UNMUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) static void simple_playback_free(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) hdmi_array_free(spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) kfree(spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) * Nvidia specific implementations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) #define Nv_VERB_SET_Channel_Allocation 0xF79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) #define Nv_VERB_SET_Audio_Protection_On 0xF98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) #define Nv_VERB_SET_Audio_Protection_Off 0xF99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) #define nvhdmi_master_con_nid_7x 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) #define nvhdmi_master_pin_nid_7x 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) static const hda_nid_t nvhdmi_con_nids_7x[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) /*front, rear, clfe, rear_surr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) 0x6, 0x8, 0xa, 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) /* set audio protect on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) /* enable digital output on pin widget */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) {} /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) /* set audio protect on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) /* enable digital output on pin widget */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) {} /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) #ifdef LIMITED_RATE_FMT_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) /* support only the safe format and rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) #define SUPPORTED_MAXBPS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) /* support all rates and formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) #define SUPPORTED_RATES \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) SNDRV_PCM_RATE_192000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) #define SUPPORTED_MAXBPS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) #define SUPPORTED_FORMATS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) static const unsigned int channels_2_6_8[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) 2, 6, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) static const unsigned int channels_2_8[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) 2, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) .count = ARRAY_SIZE(channels_2_6_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) .list = channels_2_6_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) .count = ARRAY_SIZE(channels_2_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) .list = channels_2_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) switch (codec->preset->vendor_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) case 0x10de0002:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) case 0x10de0003:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) case 0x10de0005:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) case 0x10de0006:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) hw_constraints_channels = &hw_constraints_2_8_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) case 0x10de0007:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) hw_constraints_channels = &hw_constraints_2_6_8_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) if (hw_constraints_channels != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) snd_pcm_hw_constraint_list(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) SNDRV_PCM_HW_PARAM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) hw_constraints_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) snd_pcm_hw_constraint_step(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) SNDRV_PCM_HW_PARAM_CHANNELS, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) return snd_hda_multi_out_dig_open(codec, &spec->multiout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) return snd_hda_multi_out_dig_close(codec, &spec->multiout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) unsigned int stream_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) unsigned int format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) stream_tag, format, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) static const struct hda_pcm_stream simple_pcm_playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) .substreams = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) .open = simple_playback_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) .close = simple_playback_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) .prepare = simple_playback_pcm_prepare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) static const struct hda_codec_ops simple_hdmi_patch_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) .build_controls = simple_playback_build_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) .build_pcms = simple_playback_build_pcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) .init = simple_playback_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) .free = simple_playback_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) .unsol_event = simple_hdmi_unsol_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) static int patch_simple_hdmi(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) hda_nid_t cvt_nid, hda_nid_t pin_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) struct hdmi_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) struct hdmi_spec_per_cvt *per_cvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) struct hdmi_spec_per_pin *per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) spec = kzalloc(sizeof(*spec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) if (!spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) spec->codec = codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) codec->spec = spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) hdmi_array_init(spec, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) spec->multiout.num_dacs = 0; /* no analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) spec->multiout.max_channels = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) spec->multiout.dig_out_nid = cvt_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) spec->num_cvts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) spec->num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) per_pin = snd_array_new(&spec->pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) per_cvt = snd_array_new(&spec->cvts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) if (!per_pin || !per_cvt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) simple_playback_free(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) per_cvt->cvt_nid = cvt_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) per_pin->pin_nid = pin_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) spec->pcm_playback = simple_pcm_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) codec->patch_ops = simple_hdmi_patch_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) int channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) unsigned int chanmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) int chan = channels ? (channels - 1) : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) switch (channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) chanmask = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) chanmask = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) chanmask = 0x0b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) chanmask = 0x13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) /* Set the audio infoframe channel allocation and checksum fields. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) * channel count is computed implicitly by the hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) snd_hda_codec_write(codec, 0x1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) Nv_VERB_SET_Channel_Allocation, chanmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) snd_hda_codec_write(codec, 0x1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) Nv_VERB_SET_Info_Frame_Checksum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) (0x71 - chan - chanmask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) /* set the stream id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) AC_VERB_SET_CHANNEL_STREAMID, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) /* set the stream format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) AC_VERB_SET_STREAM_FORMAT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) /* The audio hardware sends a channel count of 0x7 (8ch) when all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) * streams are disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) return snd_hda_multi_out_dig_close(codec, &spec->multiout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) unsigned int stream_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) unsigned int format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) int chs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) unsigned int dataDCC2, channel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) struct hda_spdif_out *spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) struct hdmi_spec_per_cvt *per_cvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) mutex_lock(&codec->spdif_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) per_cvt = get_cvt(spec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) chs = substream->runtime->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) dataDCC2 = 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) snd_hda_codec_write(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) nvhdmi_master_con_nid_7x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) AC_VERB_SET_DIGI_CONVERT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) /* set the stream id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) /* set the stream format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) AC_VERB_SET_STREAM_FORMAT, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) /* turn on again (if needed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) /* enable and set the channel status audio/data flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) snd_hda_codec_write(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) nvhdmi_master_con_nid_7x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) AC_VERB_SET_DIGI_CONVERT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) spdif->ctls & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) snd_hda_codec_write(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) nvhdmi_master_con_nid_7x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) if (chs == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) channel_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) channel_id = i * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) /* turn off SPDIF once;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) *otherwise the IEC958 bits won't be updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) if (codec->spdif_status_reset &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) (spdif->ctls & AC_DIG1_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) snd_hda_codec_write(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) nvhdmi_con_nids_7x[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) AC_VERB_SET_DIGI_CONVERT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) /* set the stream id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) snd_hda_codec_write(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) nvhdmi_con_nids_7x[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) AC_VERB_SET_CHANNEL_STREAMID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) (stream_tag << 4) | channel_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) /* set the stream format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) snd_hda_codec_write(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) nvhdmi_con_nids_7x[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) AC_VERB_SET_STREAM_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) /* turn on again (if needed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) /* enable and set the channel status audio/data flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) if (codec->spdif_status_reset &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) (spdif->ctls & AC_DIG1_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) snd_hda_codec_write(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) nvhdmi_con_nids_7x[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) AC_VERB_SET_DIGI_CONVERT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) spdif->ctls & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) snd_hda_codec_write(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) nvhdmi_con_nids_7x[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) mutex_unlock(&codec->spdif_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) .substreams = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) .nid = nvhdmi_master_con_nid_7x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) .rates = SUPPORTED_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) .maxbps = SUPPORTED_MAXBPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) .formats = SUPPORTED_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) .open = simple_playback_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) .close = nvhdmi_8ch_7x_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) .prepare = nvhdmi_8ch_7x_pcm_prepare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) static int patch_nvhdmi_2ch(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) struct hdmi_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) nvhdmi_master_pin_nid_7x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) codec->patch_ops.init = nvhdmi_7x_init_2ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) /* override the PCM rates, etc, as the codec doesn't give full list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) spec->pcm_playback.rates = SUPPORTED_RATES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) spec->pcm_playback.formats = SUPPORTED_FORMATS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) int err = simple_playback_build_pcms(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) struct hda_pcm *info = get_pcm_rec(spec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) info->own_chmap = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) struct hda_pcm *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) struct snd_pcm_chmap *chmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) err = simple_playback_build_controls(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) /* add channel maps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) info = get_pcm_rec(spec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) err = snd_pcm_add_chmap_ctls(info->pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) snd_pcm_alt_chmaps, 8, 0, &chmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) switch (codec->preset->vendor_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) case 0x10de0002:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) case 0x10de0003:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) case 0x10de0005:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) case 0x10de0006:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) chmap->channel_mask = (1U << 2) | (1U << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) case 0x10de0007:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) struct hdmi_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) int err = patch_nvhdmi_2ch(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) spec->multiout.max_channels = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) codec->patch_ops.init = nvhdmi_7x_init_8ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) /* Initialize the audio infoframe channel mask and checksum to something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) * valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) * - 0x10de0015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) * - 0x10de0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) struct hdac_cea_channel_speaker_allocation *cap, int channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) if (cap->ca_index == 0x00 && channels == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) return SNDRV_CTL_TLVT_CHMAP_FIXED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) /* If the speaker allocation matches the channel count, it is OK. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) if (cap->channels != channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) /* all channels are remappable freely */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) return SNDRV_CTL_TLVT_CHMAP_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) int ca, int chs, unsigned char *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) /* map from pin NID to port; port is 0-based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) return pin_nid - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) /* reverse-map from port to pin NID: see above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) static int nvhdmi_port2pin(struct hda_codec *codec, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) return port + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) .pin2port = nvhdmi_pin2port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) .pin_eld_notify = generic_acomp_pin_eld_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) .master_bind = generic_acomp_master_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) .master_unbind = generic_acomp_master_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) static int patch_nvhdmi(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) struct hdmi_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) err = alloc_generic_hdmi(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) codec->dp_mst = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) spec->dyn_pcm_assign = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) err = hdmi_parse_codec(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) generic_spec_free(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) generic_hdmi_init_per_pins(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) spec->dyn_pin_out = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) spec->chmap.ops.chmap_cea_alloc_validate_get_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) nvhdmi_chmap_cea_alloc_validate_get_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) codec->link_down_at_suspend = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) static int patch_nvhdmi_legacy(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) struct hdmi_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) err = patch_generic_hdmi(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) spec->dyn_pin_out = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) spec->chmap.ops.chmap_cea_alloc_validate_get_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) nvhdmi_chmap_cea_alloc_validate_get_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) codec->link_down_at_suspend = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) * The HDA codec on NVIDIA Tegra contains two scratch registers that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) * accessed using vendor-defined verbs. These registers can be used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) * interoperability between the HDA and HDMI drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) /* Audio Function Group node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) #define NVIDIA_AFG_NID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) * additional bit (at position 30) to signal the validity of the format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) * | 31 | 30 | 29 16 | 15 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) * +---------+-------+--------+--------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) * | TRIGGER | VALID | UNUSED | FORMAT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) * +-----------------------------------|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) * Note that for the trigger bit to take effect it needs to change value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) * (i.e. it needs to be toggled).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) #define NVIDIA_GET_SCRATCH0 0xfa6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) #define NVIDIA_SCRATCH_VALID (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) #define NVIDIA_GET_SCRATCH1 0xfab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) * the format is invalidated so that the HDMI codec can be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) /* bits [31:30] contain the trigger and valid bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) NVIDIA_GET_SCRATCH0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) value = (value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) /* bits [15:0] are used to store the HDA format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) NVIDIA_SET_SCRATCH0_BYTE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) (format >> 0) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) NVIDIA_SET_SCRATCH0_BYTE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) (format >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) /* bits [16:24] are unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) NVIDIA_SET_SCRATCH0_BYTE2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) * Bit 30 signals that the data is valid and hence that HDMI audio can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) * be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) if (format == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) value &= ~NVIDIA_SCRATCH_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) value |= NVIDIA_SCRATCH_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) * Whenever the trigger bit is toggled, an interrupt is raised in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) * HDMI codec. The HDMI driver will use that as trigger to update its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) * configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) value ^= NVIDIA_SCRATCH_TRIGGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) NVIDIA_SET_SCRATCH0_BYTE3, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) unsigned int stream_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) unsigned int format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) format, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) /* notify the HDMI codec of the format change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) tegra_hdmi_set_format(codec, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) /* invalidate the format in the HDMI codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) tegra_hdmi_set_format(codec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) for (i = 0; i < spec->num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) struct hda_pcm *pcm = get_pcm_rec(spec, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) if (pcm->pcm_type == type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) return pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) static int tegra_hdmi_build_pcms(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) struct hda_pcm_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) struct hda_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) err = generic_hdmi_build_pcms(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) if (!pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) * Override ->prepare() and ->cleanup() operations to notify the HDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) * codec about format changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) stream->ops.prepare = tegra_hdmi_pcm_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) static int patch_tegra_hdmi(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) struct hdmi_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) err = patch_generic_hdmi(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) spec->chmap.ops.chmap_cea_alloc_validate_get_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) nvhdmi_chmap_cea_alloc_validate_get_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) * ATI/AMD-specific implementations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) #define is_amdhdmi_rev3_or_later(codec) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) ((codec)->core.vendor_id == 0x1002aa01 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) ((codec)->core.revision_id & 0xff00) >= 0x0300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) #define ATI_VERB_SET_DOWNMIX_INFO 0x772
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) #define ATI_VERB_SET_MULTICHANNEL_01 0x777
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) #define ATI_VERB_SET_MULTICHANNEL_23 0x778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) #define ATI_VERB_SET_MULTICHANNEL_45 0x779
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) #define ATI_VERB_SET_HBR_CONTROL 0x77c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) #define ATI_VERB_SET_MULTICHANNEL_1 0x785
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) #define ATI_VERB_SET_MULTICHANNEL_3 0x786
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) #define ATI_VERB_SET_MULTICHANNEL_5 0x787
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) #define ATI_VERB_SET_MULTICHANNEL_7 0x788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) #define ATI_VERB_GET_HBR_CONTROL 0xf7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) /* AMD specific HDA cvt verbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) #define ATI_VERB_SET_RAMP_RATE 0x770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) #define ATI_VERB_GET_RAMP_RATE 0xf70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) #define ATI_OUT_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) #define ATI_MULTICHANNEL_MODE_PAIRED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) #define ATI_MULTICHANNEL_MODE_SINGLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) #define ATI_HBR_CAPABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) #define ATI_HBR_ENABLE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) int dev_id, unsigned char *buf, int *eld_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) WARN_ON(dev_id != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) /* call hda_eld.c ATI/AMD-specific function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) is_amdhdmi_rev3_or_later(codec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) hda_nid_t pin_nid, int dev_id, int ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) int active_channels, int conn_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) WARN_ON(dev_id != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) static int atihdmi_paired_swap_fc_lfe(int pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) * ATI/AMD have automatic FC/LFE swap built-in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) * when in pairwise mapping mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) switch (pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) /* see channel_allocations[].speakers[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) case 2: return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) case 3: return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) default: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) int ca, int chs, unsigned char *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) struct hdac_cea_channel_speaker_allocation *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) cap = snd_hdac_get_ch_alloc_from_ca(ca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) for (i = 0; i < chs; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) int mask = snd_hdac_chmap_to_spk_mask(map[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) bool ok = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) bool companion_ok = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) if (!mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) for (j = 0 + i % 2; j < 8; j += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) if (cap->speakers[chan_idx] == mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) /* channel is in a supported position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) ok = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) if (i % 2 == 0 && i + 1 < chs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) /* even channel, check the odd companion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) int comp_mask_act = cap->speakers[comp_chan_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) if (comp_mask_req == comp_mask_act)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) companion_ok = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) if (!ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) if (companion_ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) i++; /* companion channel already checked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) struct hda_codec *codec = hdac_to_hda_codec(hdac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) int verb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) int ati_channel_setup = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) if (hdmi_slot > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) if (!has_amd_full_remap_support(codec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) /* In case this is an odd slot but without stream channel, do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) * disable the slot since the corresponding even slot could have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) * channel. In case neither have a channel, the slot pair will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) * disabled when this function is called for the even slot. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) hdmi_slot -= hdmi_slot % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) if (stream_channel != 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) stream_channel -= stream_channel % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) if (stream_channel != 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) hda_nid_t pin_nid, int asp_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) struct hda_codec *codec = hdac_to_hda_codec(hdac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) bool was_odd = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) int ati_asp_slot = asp_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) int verb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) int ati_channel_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) if (asp_slot > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) if (!has_amd_full_remap_support(codec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) if (ati_asp_slot % 2 != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) ati_asp_slot -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) was_odd = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) if (!(ati_channel_setup & ATI_OUT_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) return 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) struct hdac_chmap *chmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) struct hdac_cea_channel_speaker_allocation *cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) int channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) * we need to take that into account (a single channel may take 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) * channel slots if we need to carry a silent channel next to it).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) * On Rev3+ AMD codecs this function is not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) int chanpairs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) /* We only produce even-numbered channel count TLVs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) if ((channels % 2) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) for (c = 0; c < 7; c += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) if (cap->speakers[c] || cap->speakers[c+1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) chanpairs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) if (chanpairs * 2 != channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) return SNDRV_CTL_TLVT_CHMAP_PAIRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) struct hdac_cea_channel_speaker_allocation *cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) unsigned int *chmap, int channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) /* produce paired maps for pre-rev3 ATI/AMD codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) for (c = 7; c >= 0; c--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) int spk = cap->speakers[chan];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) if (!spk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) /* add N/A channel if the companion channel is occupied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) chmap[count++] = SNDRV_CHMAP_NA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) chmap[count++] = snd_hdac_spk_to_chmap(spk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) WARN_ON(count != channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) int dev_id, bool hbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) int hbr_ctl, hbr_ctl_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) WARN_ON(dev_id != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) if (hbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) codec_dbg(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) pin_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) hbr_ctl == hbr_ctl_new ? "" : "new-",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) hbr_ctl_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) if (hbr_ctl != hbr_ctl_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) snd_hda_codec_write(codec, pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) ATI_VERB_SET_HBR_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) hbr_ctl_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) } else if (hbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) hda_nid_t pin_nid, int dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) u32 stream_tag, int format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) if (is_amdhdmi_rev3_or_later(codec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) int ramp_rate = 180; /* default as per AMD spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) /* disable ramp-up/down for non-pcm as per AMD spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) if (format & AC_FMT_TYPE_NON_PCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) ramp_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) stream_tag, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) static int atihdmi_init(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) struct hdmi_spec *spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) int pin_idx, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) err = generic_hdmi_init(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) /* make sure downmix information in infoframe is zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) /* enable channel-wise remap mode if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) if (has_amd_full_remap_support(codec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) snd_hda_codec_write(codec, per_pin->pin_nid, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) ATI_VERB_SET_MULTICHANNEL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) ATI_MULTICHANNEL_MODE_SINGLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) codec->auto_runtime_pm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) /* map from pin NID to port; port is 0-based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) return pin_nid / 2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) /* reverse-map from port to pin NID: see above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) static int atihdmi_port2pin(struct hda_codec *codec, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) return port * 2 + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) .pin2port = atihdmi_pin2port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) .pin_eld_notify = generic_acomp_pin_eld_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) .master_bind = generic_acomp_master_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) .master_unbind = generic_acomp_master_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) static int patch_atihdmi(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) struct hdmi_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) struct hdmi_spec_per_cvt *per_cvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) int err, cvt_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) err = patch_generic_hdmi(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) codec->patch_ops.init = atihdmi_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) spec = codec->spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) spec->ops.pin_get_eld = atihdmi_pin_get_eld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) spec->ops.setup_stream = atihdmi_setup_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) if (!has_amd_full_remap_support(codec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) /* override to ATI/AMD-specific versions with pairwise mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) spec->chmap.ops.chmap_cea_alloc_validate_get_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) atihdmi_paired_chmap_cea_alloc_validate_get_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) spec->chmap.ops.cea_alloc_to_tlv_chmap =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) atihdmi_paired_cea_alloc_to_tlv_chmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) /* ATI/AMD converters do not advertise all of their capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) per_cvt = get_cvt(spec, cvt_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) per_cvt->channels_max = max(per_cvt->channels_max, 8u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) per_cvt->rates |= SUPPORTED_RATES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) per_cvt->formats |= SUPPORTED_FORMATS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) per_cvt->maxbps = max(per_cvt->maxbps, 24u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) * the link-down as is. Tell the core to allow it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) codec->link_down_at_suspend = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) /* VIA HDMI Implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) static int patch_via_hdmi(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) * patch entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) static const struct hda_device_id snd_hda_id_hdmi[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) /* 17 is known to be absent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_tgl_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_tgl_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) /* special ID for generic HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) {} /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) MODULE_DESCRIPTION("HDMI HD-audio codec");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) MODULE_ALIAS("snd-hda-codec-intelhdmi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) MODULE_ALIAS("snd-hda-codec-nvhdmi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) MODULE_ALIAS("snd-hda-codec-atihdmi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) static struct hda_codec_driver hdmi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) .id = snd_hda_id_hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) module_hda_codec_driver(hdmi_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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