^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/hda_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "hda_controller.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Defines for Nvidia Tegra HDA support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HDA_BAR0 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HDA_CFG_CMD 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HDA_CFG_BAR0 0x1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HDA_ENABLE_IO_SPACE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HDA_ENABLE_MEM_SPACE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HDA_ENABLE_BUS_MASTER (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HDA_ENABLE_SERR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HDA_DISABLE_INTR (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HDA_BAR0_FINAL_PROGRAM (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* IPFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HDA_IPFS_CONFIG 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HDA_IPFS_EN_FPCI 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HDA_IPFS_FPCI_BAR0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HDA_FPCI_BAR0_START 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HDA_IPFS_INTR_MASK 0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HDA_IPFS_EN_INTR (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* FPCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FPCI_DBG_CFG_2 0x10F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FPCI_GCAP_NSDO_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* max number of SDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define NUM_CAPTURE_SD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define NUM_PLAYBACK_SD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Tegra194 does not reflect correct number of SDO lines. Below macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * is used to update the GCAP register to workaround the issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEGRA194_NUM_SDO_LINES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct hda_tegra {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct azx chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk *hda_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clk *hda2codec_2x_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct clk *hda2hdmi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct work_struct probe_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) module_param(power_save, bint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MODULE_PARM_DESC(power_save,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "Automatic power-saving timeout (in seconds, 0 = disable).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define power_save 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void hda_tegra_init(struct hda_tegra *hda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Enable PCI access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) v = readl(hda->regs + HDA_IPFS_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) v |= HDA_IPFS_EN_FPCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel(v, hda->regs + HDA_IPFS_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Enable MEM/IO space and bus master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) v = readl(hda->regs + HDA_CFG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) v &= ~HDA_DISABLE_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel(v, hda->regs + HDA_CFG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) v = readl(hda->regs + HDA_IPFS_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) v |= HDA_IPFS_EN_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(v, hda->regs + HDA_IPFS_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int hda_tegra_enable_clocks(struct hda_tegra *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) rc = clk_prepare_enable(data->hda_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) rc = clk_prepare_enable(data->hda2codec_2x_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) goto disable_hda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) rc = clk_prepare_enable(data->hda2hdmi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) goto disable_codec_2x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) disable_codec_2x:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) clk_disable_unprepare(data->hda2codec_2x_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) disable_hda:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clk_disable_unprepare(data->hda_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void hda_tegra_disable_clocks(struct hda_tegra *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) clk_disable_unprepare(data->hda2hdmi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clk_disable_unprepare(data->hda2codec_2x_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) clk_disable_unprepare(data->hda_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * power management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int __maybe_unused hda_tegra_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) rc = pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int __maybe_unused hda_tegra_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) rc = pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct azx *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (chip && chip->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* enable controller wake up event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) STATESTS_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) azx_stop_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) azx_enter_link_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) hda_tegra_disable_clocks(hda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct azx *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) rc = hda_tegra_enable_clocks(hda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (rc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (chip && chip->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) hda_tegra_init(hda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) azx_init_chip(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* disable controller wake up event*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ~STATESTS_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct dev_pm_ops hda_tegra_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) hda_tegra_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int hda_tegra_dev_disconnect(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct azx *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) chip->bus.shutdown = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * destructor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int hda_tegra_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct azx *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) cancel_work_sync(&hda->probe_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (azx_bus(chip)->chip_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) azx_stop_all_streams(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) azx_stop_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) azx_free_stream_pages(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) azx_free_streams(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) snd_hdac_bus_exit(azx_bus(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct device *dev = hda->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) hda->regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (IS_ERR(hda->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return PTR_ERR(hda->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) bus->remap_addr = hda->regs + HDA_BAR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) bus->addr = res->start + HDA_BAR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) hda_tegra_init(hda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int hda_tegra_init_clk(struct hda_tegra *hda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct device *dev = hda->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) hda->hda_clk = devm_clk_get(dev, "hda");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (IS_ERR(hda->hda_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_err(dev, "failed to get hda clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return PTR_ERR(hda->hda_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (IS_ERR(hda->hda2codec_2x_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev_err(dev, "failed to get hda2codec_2x clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return PTR_ERR(hda->hda2codec_2x_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (IS_ERR(hda->hda2hdmi_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_err(dev, "failed to get hda2hdmi clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return PTR_ERR(hda->hda2hdmi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct snd_card *card = chip->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned short gcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int irq_id = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) const char *sname, *drv_name = "tegra-hda";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (irq_id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return irq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) err = hda_tegra_init_chip(chip, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) IRQF_SHARED, KBUILD_MODNAME, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "unable to request IRQ %d, disabling device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) irq_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) bus->irq = irq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) bus->dma_stop_delay = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) card->sync_irq = bus->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Tegra194 has 4 SDO lines and the STRIPE can be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * indicate how many of the SDO lines the stream should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * striped. But GCAP register does not reflect the true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * capability of HW. Below workaround helps to fix this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (of_device_is_compatible(np, "nvidia,tegra194-hda")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_info(card->dev, "Override SDO lines to %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) TEGRA194_NUM_SDO_LINES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) writel(val, hda->regs + FPCI_DBG_CFG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) gcap = azx_readw(chip, GCAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) chip->align_buffer_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* read number of streams from GCAP register instead of using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * hardcoded value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) chip->capture_streams = (gcap >> 8) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) chip->playback_streams = (gcap >> 12) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!chip->playback_streams && !chip->capture_streams) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* gcap didn't give any info, switching to old method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) chip->playback_streams = NUM_PLAYBACK_SD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) chip->capture_streams = NUM_CAPTURE_SD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) chip->capture_index_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) chip->playback_index_offset = chip->capture_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) chip->num_streams = chip->playback_streams + chip->capture_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* initialize streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) err = azx_init_streams(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_err(card->dev, "failed to initialize streams: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) err = azx_alloc_stream_pages(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_err(card->dev, "failed to allocate stream pages: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* initialize chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) azx_init_chip(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * 4 SDO lines due to legacy design limitation. Following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * is, from HD Audio Specification (Revision 1.0a), used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * control striping of the stream across multiple SDO lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * for sample rates <= 48K.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * Due to legacy design issue it is recommended that above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * ratio must be greater than 8. Since number of SDO lines is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * in powers of 2, next available ratio is 16 which can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * used as a limiting factor here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (of_device_is_compatible(np, "nvidia,tegra30-hda"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) chip->bus.core.sdo_limit = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* codec detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!bus->codec_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(card->dev, "no codecs found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* driver name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) strncpy(card->driver, drv_name, sizeof(card->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* shortname for card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) sname = of_get_property(np, "nvidia,model", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!sname)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) sname = drv_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (strlen(sname) > sizeof(card->shortname))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_info(card->dev, "truncating shortname for card\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) strncpy(card->shortname, sname, sizeof(card->shortname));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* longname for card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) snprintf(card->longname, sizeof(card->longname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "%s at 0x%lx irq %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) card->shortname, bus->addr, bus->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * constructor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void hda_tegra_probe_work(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int hda_tegra_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int driver_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct hda_tegra *hda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .dev_disconnect = hda_tegra_dev_disconnect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .dev_free = hda_tegra_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) chip = &hda->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mutex_init(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) chip->ops = &hda_tegra_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) chip->driver_caps = driver_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) chip->driver_type = driver_caps & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) chip->dev_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) INIT_LIST_HEAD(&chip->pcm_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) chip->codec_probe_mask = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) chip->single_cmd = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) chip->snoop = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) err = azx_bus_init(chip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) chip->bus.core.sync_write = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) chip->bus.core.needs_damn_long_delay = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) chip->bus.core.aligned_mmio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_err(card->dev, "Error creating device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static const struct of_device_id hda_tegra_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { .compatible = "nvidia,tegra30-hda" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { .compatible = "nvidia,tegra194-hda" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MODULE_DEVICE_TABLE(of, hda_tegra_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int hda_tegra_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) AZX_DCAPS_PM_RUNTIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct hda_tegra *hda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!hda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) hda->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) chip = &hda->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) THIS_MODULE, 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_err(&pdev->dev, "Error creating card!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) err = hda_tegra_init_clk(hda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) err = hda_tegra_create(card, driver_flags, hda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) card->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_set_drvdata(&pdev->dev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pm_runtime_enable(hda->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (!azx_has_pm_runtime(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pm_runtime_forbid(hda->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) schedule_work(&hda->probe_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static void hda_tegra_probe_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct azx *chip = &hda->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct platform_device *pdev = to_platform_device(hda->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pm_runtime_get_sync(hda->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) err = hda_tegra_first_init(chip, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* create codec instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) err = azx_probe_codecs(chip, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) err = azx_codec_configure(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) err = snd_card_register(chip->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) chip->running = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) snd_hda_set_power_save(&chip->bus, power_save * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pm_runtime_put(hda->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return; /* no error return from async probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int hda_tegra_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = snd_card_free(dev_get_drvdata(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static void hda_tegra_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct snd_card *card = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (!card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (chip && chip->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) azx_stop_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static struct platform_driver tegra_platform_hda = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .name = "tegra-hda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .pm = &hda_tegra_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .of_match_table = hda_tegra_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .probe = hda_tegra_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .remove = hda_tegra_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .shutdown = hda_tegra_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) module_platform_driver(tegra_platform_hda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) MODULE_DESCRIPTION("Tegra HDA bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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