^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * hda_intel.c - Implementation of primary alsa driver code base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * for Intel HD Audio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright(c) 2004 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * PeiSen Hou <pshou@realtek.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * CONTACTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Matt Jared matt.jared@intel.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Andy Kopp andy.kopp@intel.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Dan Kogan dan.d.kogan@intel.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * CHANGES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* for snoop control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/set_memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/cpufeature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <sound/hdaudio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <sound/hda_i915.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <sound/intel-dsp-config.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/vgaarb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/vga_switcheroo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <sound/hda_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include "hda_controller.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include "hda_intel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CREATE_TRACE_POINTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include "hda_intel_trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* position fix mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) POS_FIX_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) POS_FIX_LPIB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) POS_FIX_POSBUF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) POS_FIX_VIACOMBO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) POS_FIX_COMBO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) POS_FIX_SKL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) POS_FIX_FIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Defines for ATI HD Audio support in SB450 south bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Defines for Nvidia HDA support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define NVIDIA_HDA_ISTRM_COH 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define NVIDIA_HDA_OSTRM_COH 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define NVIDIA_HDA_ENABLE_COHBIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Defines for Intel SCH HDA snoop control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define INTEL_HDA_CGCTL 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define INTEL_SCH_HDA_DEVC 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Define VIA HD Audio Device ID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define VIA_HDAC_DEVICE_ID 0x3288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* max number of SDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* ICH, ATI and VIA have 4 playback and 4 capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ICH6_NUM_CAPTURE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ICH6_NUM_PLAYBACK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* ULI has 6 playback and 5 capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ULI_NUM_CAPTURE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ULI_NUM_PLAYBACK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* ATI HDMI may have up to 8 playbacks and 0 capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ATIHDMI_NUM_CAPTURE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ATIHDMI_NUM_PLAYBACK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* TERA has 4 playback and 3 capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TERA_NUM_CAPTURE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TERA_NUM_PLAYBACK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static char *model[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int probe_only[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int jackpoll_ms[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int single_cmd = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int enable_msi = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #ifdef CONFIG_SND_HDA_PATCH_LOADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static char *patch[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #ifdef CONFIG_SND_HDA_INPUT_BEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) CONFIG_SND_HDA_INPUT_BEEP_MODE};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static bool dmic_detect = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) module_param_array(model, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MODULE_PARM_DESC(model, "Use the given board model.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) module_param_array(position_fix, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MODULE_PARM_DESC(position_fix, "DMA pointer read method."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) module_param_array(bdl_pos_adj, int, NULL, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) module_param_array(probe_mask, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) module_param_array(probe_only, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) module_param_array(jackpoll_ms, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) module_param(single_cmd, bint, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "(for debugging only).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) module_param(enable_msi, bint, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #ifdef CONFIG_SND_HDA_PATCH_LOADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) module_param_array(patch, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #ifdef CONFIG_SND_HDA_INPUT_BEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) module_param_array(beep_mode, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "(0=off, 1=on) (default=1).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) module_param(dmic_detect, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "(0=off, 1=on) (default=1); "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int param_set_xint(const char *val, const struct kernel_param *kp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct kernel_param_ops param_ops_xint = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .set = param_set_xint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .get = param_get_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define param_check_xint param_check_int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) module_param(power_save, xint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "(in second, 0 = disable).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static bool pm_blacklist = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) module_param(pm_blacklist, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* reset the HD-audio controller in power save mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * this may give more power-saving, but will take longer time to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * wake up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static bool power_save_controller = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) module_param(power_save_controller, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define power_save 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int align_buffer_size = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) module_param(align_buffer_size, bint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MODULE_PARM_DESC(align_buffer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "Force buffer and period sizes to be multiple of 128 bytes.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int hda_snoop = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) module_param_named(snoop, hda_snoop, bint, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MODULE_PARM_DESC(snoop, "Enable/disable snooping");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define hda_snoop true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "{Intel, ICH6M},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "{Intel, ICH7},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "{Intel, ESB2},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "{Intel, ICH8},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "{Intel, ICH9},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "{Intel, ICH10},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "{Intel, PCH},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "{Intel, CPT},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "{Intel, PPT},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "{Intel, LPT},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "{Intel, LPT_LP},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "{Intel, WPT_LP},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "{Intel, SPT},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "{Intel, SPT_LP},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "{Intel, HPT},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "{Intel, PBG},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "{Intel, SCH},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "{ATI, SB450},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "{ATI, SB600},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "{ATI, RS600},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "{ATI, RS690},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "{ATI, RS780},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "{ATI, R600},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "{ATI, RV630},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "{ATI, RV610},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "{ATI, RV670},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "{ATI, RV635},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "{ATI, RV620},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "{ATI, RV770},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "{VIA, VT8251},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "{VIA, VT8237A},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "{SiS, SIS966},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "{ULI, M5461}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MODULE_DESCRIPTION("Intel HDA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SUPPORT_VGA_SWITCHEROO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* driver types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) AZX_DRIVER_ICH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) AZX_DRIVER_PCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) AZX_DRIVER_SCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) AZX_DRIVER_SKL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) AZX_DRIVER_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) AZX_DRIVER_ATI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) AZX_DRIVER_ATIHDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) AZX_DRIVER_ATIHDMI_NS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) AZX_DRIVER_VIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) AZX_DRIVER_SIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) AZX_DRIVER_ULI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) AZX_DRIVER_NVIDIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) AZX_DRIVER_TERA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) AZX_DRIVER_CTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) AZX_DRIVER_CTHDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) AZX_DRIVER_CMEDIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) AZX_DRIVER_ZHAOXIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) AZX_DRIVER_GENERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) AZX_NUM_DRIVERS, /* keep this as last entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define azx_get_snoop_type(chip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* quirks for old Intel chipsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define AZX_DCAPS_INTEL_ICH \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* quirks for Intel PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define AZX_DCAPS_INTEL_PCH_BASE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) AZX_DCAPS_SNOOP_TYPE(SCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* PCH up to IVB; no runtime PM; bind with i915 gfx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define AZX_DCAPS_INTEL_PCH_NOPM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* PCH for HSW/BDW; with runtime PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* no i915 binding for this as HSW/BDW has another controller for HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define AZX_DCAPS_INTEL_PCH \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* HSW HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define AZX_DCAPS_INTEL_HASWELL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) AZX_DCAPS_SNOOP_TYPE(SCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define AZX_DCAPS_INTEL_BROADWELL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) AZX_DCAPS_SNOOP_TYPE(SCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define AZX_DCAPS_INTEL_BAYTRAIL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define AZX_DCAPS_INTEL_BRASWELL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) AZX_DCAPS_I915_COMPONENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define AZX_DCAPS_INTEL_SKYLAKE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* quirks for ATI SB / AMD Hudson */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define AZX_DCAPS_PRESET_ATI_SB \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) AZX_DCAPS_SNOOP_TYPE(ATI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* quirks for ATI/AMD HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define AZX_DCAPS_PRESET_ATI_HDMI \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) AZX_DCAPS_NO_MSI64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* quirks for ATI HDMI with snoop off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* quirks for AMD SB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define AZX_DCAPS_PRESET_AMD_SB \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) AZX_DCAPS_RETRY_PROBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* quirks for Nvidia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define AZX_DCAPS_PRESET_NVIDIA \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) AZX_DCAPS_SNOOP_TYPE(NVIDIA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define AZX_DCAPS_PRESET_CTHDA \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) AZX_DCAPS_NO_64BIT |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * vga_switcheroo support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #ifdef SUPPORT_VGA_SWITCHEROO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define use_vga_switcheroo(chip) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define needs_eld_notify_link(chip) false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ((pci)->device == 0x0c0c) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ((pci)->device == 0x0d0c) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ((pci)->device == 0x160c) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ((pci)->device == 0x490d) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ((pci)->device == 0x4f90) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ((pci)->device == 0x4f91) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ((pci)->device == 0x4f92))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const char * const driver_short_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) [AZX_DRIVER_ICH] = "HDA Intel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) [AZX_DRIVER_PCH] = "HDA Intel PCH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) [AZX_DRIVER_SCH] = "HDA Intel MID",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) [AZX_DRIVER_ATI] = "HDA ATI SB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) [AZX_DRIVER_SIS] = "HDA SIS966",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) [AZX_DRIVER_ULI] = "HDA ULI M5461",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) [AZX_DRIVER_NVIDIA] = "HDA NVidia",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) [AZX_DRIVER_TERA] = "HDA Teradici",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) [AZX_DRIVER_CTX] = "HDA Creative",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) [AZX_DRIVER_CTHDA] = "HDA Creative",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) [AZX_DRIVER_CMEDIA] = "HDA C-Media",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int azx_acquire_irq(struct azx *chip, int do_disconnect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void set_default_power_save(struct azx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * initialize the PCI registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* update bits in a PCI register byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned char mask, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned char data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pci_read_config_byte(pci, reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) data |= (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pci_write_config_byte(pci, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void azx_init_pci(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int snoop_type = azx_get_snoop_type(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * TCSEL == Traffic Class Select Register, which sets PCI express QOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * Ensuring these bits are 0 clears playback static on some HD Audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * codecs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * The PCI register TCSEL is defined in the Intel manuals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_dbg(chip->card->dev, "Clearing TCSEL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * we need to enable snoop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (snoop_type == AZX_SNOOP_TYPE_ATI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) azx_snoop(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) update_pci_byte(chip->pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* For NVIDIA HDA, enable snoop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) azx_snoop(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) update_pci_byte(chip->pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) NVIDIA_HDA_TRANSREG_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) update_pci_byte(chip->pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) NVIDIA_HDA_ISTRM_COH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 0x01, NVIDIA_HDA_ENABLE_COHBIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) update_pci_byte(chip->pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) NVIDIA_HDA_OSTRM_COH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 0x01, NVIDIA_HDA_ENABLE_COHBIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Enable SCH/PCH snoop if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (snoop_type == AZX_SNOOP_TYPE_SCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned short snoop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (!azx_snoop(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pci_read_config_word(chip->pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) INTEL_SCH_HDA_DEVC, &snoop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_dbg(chip->card->dev, "SCH snoop: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) "Disabled" : "Enabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * In BXT-P A0, HD-Audio DMA requests is later than expected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * and makes an audio stream sensitive to system latencies when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * 24/32 bits are playing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Adjusting threshold of DMA fifo to force the DMA request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * sooner to improve latency tolerance at the expense of power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static void bxt_reduce_dma_latency(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) val = azx_readl(chip, VS_EM4L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) val &= (0x3 << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) azx_writel(chip, VS_EM4L, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * ML_LCAP bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * bit 0: 6 MHz Supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * bit 1: 12 MHz Supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * bit 2: 24 MHz Supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * bit 3: 48 MHz Supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * bit 4: 96 MHz Supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * bit 5: 192 MHz Supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int intel_get_lctl_scf(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 val, t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) t = preferred_bits[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (val & (1 << t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int intel_ml_lctl_set_power(struct azx *chip, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * the codecs are sharing the first link setting by default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * If other links are enabled for stream, they need similar fix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) val &= ~AZX_MLCTL_SPA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) val |= state << AZX_MLCTL_SPA_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* wait for CPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) timeout = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) while (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static void intel_init_lctl(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* 0. check lctl register value is correct or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* if SCF is already set, let's use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if ((val & ML_LCTL_SCF_MASK) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * Before operating on SPA, CPA must match SPA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * Any deviation may result in undefined behavior.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = intel_ml_lctl_set_power(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) goto set_spa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* 2. update SCF to select a properly audio clock*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) val &= ~ML_LCTL_SCF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) val |= intel_get_lctl_scf(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) set_spa:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) intel_ml_lctl_set_power(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static void hda_intel_init_chip(struct azx *chip, bool full_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct pci_dev *pci = chip->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) snd_hdac_set_codec_wakeup(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (chip->driver_type == AZX_DRIVER_SKL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) azx_init_chip(chip, full_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (chip->driver_type == AZX_DRIVER_SKL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) val = val | INTEL_HDA_CGCTL_MISCBDCGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) snd_hdac_set_codec_wakeup(bus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* reduce dma latency to avoid noise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (IS_BXT(pci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) bxt_reduce_dma_latency(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (bus->mlcap != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) intel_init_lctl(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* calculate runtime delay from LPIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned int pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct snd_pcm_substream *substream = azx_dev->core.substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int stream = substream->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) delay = pos - lpib_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) delay = lpib_pos - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (delay < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (delay >= azx_dev->core.delay_negative_threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) delay += azx_dev->core.bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (delay >= azx_dev->core.period_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_info(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) delay, azx_dev->core.period_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) chip->get_delay[stream] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return bytes_to_frames(substream->runtime, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* called from IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ok = azx_position_ok(chip, azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (ok == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) azx_dev->irq_pending = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) } else if (ok == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* bogus IRQ, process it later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) azx_dev->irq_pending = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) schedule_work(&hda->irq_pending_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define display_power(chip, enable) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * Check whether the current DMA position is acceptable for updating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * periods. Returns non-zero if it's OK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * Many HD-audio controllers appear pretty inaccurate about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * the update-IRQ timing. The IRQ is issued before actually the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * data is processed. So, we need to process it afterwords in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * workqueue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct snd_pcm_substream *substream = azx_dev->core.substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int stream = substream->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u32 wallclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) unsigned int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) snd_pcm_uframes_t hwptr, target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return -1; /* bogus (too early) interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (chip->get_position[stream])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) pos = chip->get_position[stream](chip, azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) else { /* use the position buffer as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) pos = azx_get_pos_posbuf(chip, azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (!pos || pos == (u32)-1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_info(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) "Invalid position buffer, using LPIB read method instead.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) chip->get_position[stream] = azx_get_pos_lpib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (chip->get_position[0] == azx_get_pos_lpib &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) chip->get_position[1] == azx_get_pos_lpib)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) azx_bus(chip)->use_posbuf = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) pos = azx_get_pos_lpib(chip, azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) chip->get_delay[stream] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) chip->get_position[stream] = azx_get_pos_posbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) chip->get_delay[stream] = azx_get_delay_from_lpib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (pos >= azx_dev->core.bufsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (WARN_ONCE(!azx_dev->core.period_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) "hda-intel: zero azx_dev->period_bytes"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return -1; /* this shouldn't happen! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* NG - it's below the first next period boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return chip->bdl_pos_adj ? 0 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) azx_dev->core.start_wallclk += wallclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (azx_dev->core.no_period_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return 1; /* OK, no need to check period boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return 1; /* OK, already in hwptr updating process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* check whether the period gets really elapsed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) pos = bytes_to_frames(runtime, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) hwptr = runtime->hw_ptr_base + pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (hwptr < runtime->status->hw_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) hwptr += runtime->buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) target = runtime->hw_ptr_interrupt + runtime->period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (hwptr < target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* too early wakeup, process it later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return chip->bdl_pos_adj ? 0 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 1; /* OK, it's fine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * The work for pending PCM period updates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static void azx_irq_pending_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct azx *chip = &hda->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct hdac_stream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) int pending, ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (!hda->irq_pending_warned) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev_info(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) chip->card->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) hda->irq_pending_warned = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) pending = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) spin_lock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) list_for_each_entry(s, &bus->stream_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct azx_dev *azx_dev = stream_to_azx_dev(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (!azx_dev->irq_pending ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) !s->substream ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) !s->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ok = azx_position_ok(chip, azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (ok > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) azx_dev->irq_pending = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) spin_unlock(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) snd_pcm_period_elapsed(s->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) spin_lock(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) } else if (ok < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pending = 0; /* too early */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) pending++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) spin_unlock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* clear irq_pending flags and assure no on-going workq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static void azx_clear_irq_pending(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct hdac_stream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) spin_lock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) list_for_each_entry(s, &bus->stream_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct azx_dev *azx_dev = stream_to_azx_dev(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) azx_dev->irq_pending = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) spin_unlock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int azx_acquire_irq(struct azx *chip, int do_disconnect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (request_irq(chip->pci->irq, azx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) chip->msi ? 0 : IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) chip->card->irq_descr, chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "unable to grab IRQ %d, disabling device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) chip->pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (do_disconnect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) snd_card_disconnect(chip->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) bus->irq = chip->pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) chip->card->sync_irq = bus->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) pci_intx(chip->pci, !chip->msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* get the current DMA position with correction on VIA chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static unsigned int azx_via_get_position(struct azx *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct azx_dev *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) unsigned int link_pos, mini_pos, bound_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) unsigned int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Playback, no problem using link position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return link_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* Capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* For new chipset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * use mod to get the DMA position just like old chipset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) mod_dma_pos %= azx_dev->core.period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) fifo_size = azx_stream(azx_dev)->fifo_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (azx_dev->insufficient) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* Link position never gather than FIFO size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (link_pos <= fifo_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) azx_dev->insufficient = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (link_pos <= fifo_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) mini_pos = link_pos - fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* Find nearest previous boudary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) mod_link_pos = link_pos % azx_dev->core.period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (mod_link_pos >= fifo_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) bound_pos = link_pos - mod_link_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) else if (mod_dma_pos >= mod_mini_pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) bound_pos = mini_pos - mod_mini_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (bound_pos >= azx_dev->core.bufsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) bound_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* Calculate real DMA position we want */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return bound_pos + mod_dma_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define AMD_FIFO_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* get the current DMA position with FIFO size correction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct snd_pcm_substream *substream = azx_dev->core.substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) unsigned int pos, delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (!runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) runtime->delay = AMD_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (azx_dev->insufficient) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (pos < delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) delay = pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) runtime->delay = bytes_to_frames(runtime, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) azx_dev->insufficient = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* correct the DMA position for capture stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (pos < delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) pos += azx_dev->core.bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) pos -= delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) unsigned int pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct snd_pcm_substream *substream = azx_dev->core.substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* just read back the calculated value in the above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return substream->runtime->delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) azx_stop_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (!skip_link_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) azx_enter_link_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) azx_clear_irq_pending(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) display_power(chip, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static DEFINE_MUTEX(card_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static LIST_HEAD(card_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static void azx_shutdown_chip(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) __azx_shutdown_chip(chip, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static void azx_add_card_list(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) mutex_lock(&card_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) list_add(&hda->list, &card_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) mutex_unlock(&card_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static void azx_del_card_list(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) mutex_lock(&card_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) list_del_init(&hda->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) mutex_unlock(&card_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* trigger power-save check at writing parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static int param_set_xint(const char *val, const struct kernel_param *kp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct hda_intel *hda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) int prev = power_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) int ret = param_set_int(val, kp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (ret || prev == power_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) mutex_lock(&card_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) list_for_each_entry(hda, &card_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) chip = &hda->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (!hda->probe_continued || chip->disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) snd_hda_set_power_save(&chip->bus, power_save * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) mutex_unlock(&card_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * power management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static bool azx_is_pm_ready(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct hda_intel *hda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (!card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (chip->disabled || hda->init_failed || !chip->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static void __azx_runtime_resume(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct hda_codec *codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) display_power(chip, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (hda->need_i915_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) snd_hdac_i915_set_bclk(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* Read STATESTS before controller reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) status = azx_readw(chip, STATESTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) azx_init_pci(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) hda_intel_init_chip(chip, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* Avoid codec resume if runtime resume is for system suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (!chip->pm_prepared) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) list_for_each_codec(codec, &chip->bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (codec->relaxed_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (codec->forced_resume || (status & (1 << codec->addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) pm_request_resume(hda_codec_dev(codec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* power down again for link-controlled chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (!hda->need_i915_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) display_power(chip, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static int azx_prepare(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (!azx_is_pm_ready(card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) chip->pm_prepared = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) flush_work(&azx_bus(chip)->unsol_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* HDA controller always requires different WAKEEN for runtime suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * and system suspend, so don't use direct-complete here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static void azx_complete(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (!azx_is_pm_ready(card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) chip->pm_prepared = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static int azx_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct hdac_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (!azx_is_pm_ready(card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) azx_shutdown_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (bus->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) free_irq(bus->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) bus->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) chip->card->sync_irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (chip->msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) pci_disable_msi(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) trace_azx_suspend(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static int azx_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (!azx_is_pm_ready(card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (chip->msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (pci_enable_msi(chip->pci) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) chip->msi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (azx_acquire_irq(chip, 1) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) __azx_runtime_resume(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) trace_azx_resume(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* put codec down to D3 at hibernation for Intel SKL+;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * otherwise BIOS may still access the codec and screw up the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static int azx_freeze_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct azx *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct pci_dev *pci = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (!azx_is_pm_ready(card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (chip->driver_type == AZX_DRIVER_SKL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) pci_set_power_state(pci, PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static int azx_thaw_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct azx *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct pci_dev *pci = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (!azx_is_pm_ready(card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (chip->driver_type == AZX_DRIVER_SKL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) pci_set_power_state(pci, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static int azx_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (!azx_is_pm_ready(card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* enable controller wake up event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) azx_shutdown_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) trace_azx_runtime_suspend(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static int azx_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (!azx_is_pm_ready(card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) __azx_runtime_resume(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* disable controller Wake Up event*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) trace_azx_runtime_resume(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static int azx_runtime_idle(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct hda_intel *hda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (!card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (chip->disabled || hda->init_failed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (!power_save_controller || !azx_has_pm_runtime(chip) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) azx_bus(chip)->codec_powered || !chip->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /* ELD notification gets broken when HD-audio bus is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (needs_eld_notify_link(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static const struct dev_pm_ops azx_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .prepare = azx_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .complete = azx_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .freeze_noirq = azx_freeze_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .thaw_noirq = azx_thaw_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define AZX_PM_OPS &azx_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define azx_add_card_list(chip) /* NOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define azx_del_card_list(chip) /* NOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define AZX_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static int azx_probe_continue(struct azx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #ifdef SUPPORT_VGA_SWITCHEROO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static struct pci_dev *get_bound_vga(struct pci_dev *pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static void azx_vs_set_state(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) enum vga_switcheroo_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct snd_card *card = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct azx *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct hda_codec *codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) bool disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) wait_for_completion(&hda->probe_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (hda->init_failed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) disabled = (state == VGA_SWITCHEROO_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (chip->disabled == disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (!hda->probe_continued) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) chip->disabled = disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (!disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) dev_info(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) "Start delayed initialization\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (azx_probe_continue(chip) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) dev_err(chip->card->dev, "initialization error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) dev_info(chip->card->dev, "%s via vga_switcheroo\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) disabled ? "Disabling" : "Enabling");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) list_for_each_codec(codec, &chip->bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) pm_runtime_suspend(hda_codec_dev(codec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) pm_runtime_disable(hda_codec_dev(codec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) pm_runtime_suspend(card->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) pm_runtime_disable(card->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* when we get suspended by vga_switcheroo we end up in D3cold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * however we have no ACPI handle, so pci/acpi can't put us there,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * put ourselves there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) pci->current_state = PCI_D3cold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) chip->disabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (snd_hda_lock_devices(&chip->bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) dev_warn(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) "Cannot lock devices!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) snd_hda_unlock_devices(&chip->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) chip->disabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) pm_runtime_enable(card->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) list_for_each_codec(codec, &chip->bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) pm_runtime_enable(hda_codec_dev(codec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) pm_runtime_resume(hda_codec_dev(codec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static bool azx_vs_can_switch(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct snd_card *card = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct azx *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) wait_for_completion(&hda->probe_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (hda->init_failed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (chip->disabled || !hda->probe_continued)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (snd_hda_lock_devices(&chip->bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) snd_hda_unlock_devices(&chip->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) * The discrete GPU cannot power down unless the HDA controller runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * suspends, so activate runtime PM on codecs even if power_save == 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct hda_codec *codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) list_for_each_codec(codec, &chip->bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) codec->auto_runtime_pm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /* reset the power save setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (chip->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) set_default_power_save(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static void azx_vs_gpu_bound(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) enum vga_switcheroo_client_id client_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct snd_card *card = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct azx *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (client_id == VGA_SWITCHEROO_DIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) chip->bus.keep_power = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) setup_vga_switcheroo_runtime_pm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static void init_vga_switcheroo(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) struct pci_dev *p = get_bound_vga(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) struct pci_dev *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dev_info(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) "Handle vga_switcheroo audio client\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) hda->use_vga_switcheroo = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* cleared in either gpu_bound op or codec probe, or when its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * upstream port has _PR3 (i.e. dGPU).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) parent = pci_upstream_bridge(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) pci_dev_put(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) static const struct vga_switcheroo_client_ops azx_vs_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .set_gpu_state = azx_vs_set_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .can_switch = azx_vs_can_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .gpu_bound = azx_vs_gpu_bound,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static int register_vga_switcheroo(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) struct pci_dev *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (!hda->use_vga_switcheroo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) p = get_bound_vga(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) pci_dev_put(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) hda->vga_switcheroo_registered = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define init_vga_switcheroo(chip) /* NOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define register_vga_switcheroo(chip) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define check_hdmi_disabled(pci) false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #endif /* SUPPORT_VGA_SWITCHER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * destructor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static void azx_free(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) struct pci_dev *pci = chip->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (hda->freed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (azx_has_pm_runtime(chip) && chip->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) pm_runtime_get_noresume(&pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) chip->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) azx_del_card_list(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) hda->init_failed = 1; /* to be sure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) complete_all(&hda->probe_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (use_vga_switcheroo(hda)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (chip->disabled && hda->probe_continued)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) snd_hda_unlock_devices(&chip->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (hda->vga_switcheroo_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) vga_switcheroo_unregister_client(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (bus->chip_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) azx_clear_irq_pending(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) azx_stop_all_streams(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) azx_stop_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (bus->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) free_irq(bus->irq, (void*)chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (chip->msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) pci_disable_msi(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) iounmap(bus->remap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) azx_free_stream_pages(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) azx_free_streams(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) snd_hdac_bus_exit(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (chip->region_requested)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) pci_release_regions(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) pci_disable_device(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #ifdef CONFIG_SND_HDA_PATCH_LOADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) release_firmware(chip->fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) display_power(chip, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) snd_hdac_i915_exit(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) hda->freed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static int azx_dev_disconnect(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct azx *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) chip->bus.shutdown = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) cancel_work_sync(&bus->unsol_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static int azx_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) azx_free(device->device_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #ifdef SUPPORT_VGA_SWITCHEROO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* ATPX is in the integrated GPU's namespace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static bool atpx_present(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) struct pci_dev *pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) acpi_handle dhandle, atpx_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) dhandle = ACPI_HANDLE(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (dhandle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (!ACPI_FAILURE(status)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) dhandle = ACPI_HANDLE(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (dhandle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (!ACPI_FAILURE(status)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static bool atpx_present(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) * Check of disabled HDMI controller by vga_switcheroo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static struct pci_dev *get_bound_vga(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) struct pci_dev *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* check only discrete GPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) switch (pci->vendor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) case PCI_VENDOR_ID_ATI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) case PCI_VENDOR_ID_AMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (pci->devfn == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) pci->bus->number, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* ATPX is in the integrated GPU's ACPI namespace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * rather than the dGPU's namespace. However,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * the dGPU is the one who is involved in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * vgaswitcheroo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) atpx_present())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) pci_dev_put(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) case PCI_VENDOR_ID_NVIDIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (pci->devfn == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) pci->bus->number, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) pci_dev_put(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static bool check_hdmi_disabled(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) bool vga_inactive = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) struct pci_dev *p = get_bound_vga(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) vga_inactive = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) pci_dev_put(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) return vga_inactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #endif /* SUPPORT_VGA_SWITCHEROO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * allow/deny-listing for position_fix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) static const struct snd_pci_quirk position_fix_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) static int check_position_fix(struct azx *chip, int fix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) const struct snd_pci_quirk *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) switch (fix) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) case POS_FIX_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) case POS_FIX_LPIB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) case POS_FIX_POSBUF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) case POS_FIX_VIACOMBO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) case POS_FIX_COMBO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) case POS_FIX_SKL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) case POS_FIX_FIFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) return fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (q) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) dev_info(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) "position_fix set to %d for device %04x:%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) q->value, q->subvendor, q->subdevice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) return q->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) /* Check VIA/ATI HD Audio Controller exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (chip->driver_type == AZX_DRIVER_VIA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return POS_FIX_VIACOMBO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) dev_dbg(chip->card->dev, "Using FIFO position fix\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) return POS_FIX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) dev_dbg(chip->card->dev, "Using LPIB position fix\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return POS_FIX_LPIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (chip->driver_type == AZX_DRIVER_SKL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) dev_dbg(chip->card->dev, "Using SKL position fix\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return POS_FIX_SKL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) return POS_FIX_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static void assign_position_fix(struct azx *chip, int fix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static const azx_get_pos_callback_t callbacks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) [POS_FIX_AUTO] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) [POS_FIX_LPIB] = azx_get_pos_lpib,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) [POS_FIX_POSBUF] = azx_get_pos_posbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) [POS_FIX_VIACOMBO] = azx_via_get_position,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) [POS_FIX_COMBO] = azx_get_pos_lpib,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) [POS_FIX_SKL] = azx_get_pos_posbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) [POS_FIX_FIFO] = azx_get_pos_fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) chip->get_position[0] = chip->get_position[1] = callbacks[fix];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) /* combo mode uses LPIB only for playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (fix == POS_FIX_COMBO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) chip->get_position[1] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) chip->get_delay[0] = chip->get_delay[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) azx_get_delay_from_lpib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (fix == POS_FIX_FIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) chip->get_delay[0] = chip->get_delay[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) azx_get_delay_from_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) * deny-lists for probe_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static const struct snd_pci_quirk probe_mask_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /* Thinkpad often breaks the controller communication when accessing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) * to the non-working (or non-existing) modem codec slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /* broken BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /* forced codec slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) /* WinFast VP200 H (Teradici) user reported broken communication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #define AZX_FORCE_CODEC_MASK 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static void check_probe_mask(struct azx *chip, int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) const struct snd_pci_quirk *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) chip->codec_probe_mask = probe_mask[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (chip->codec_probe_mask == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (q) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) dev_info(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) "probe_mask set to 0x%x for device %04x:%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) q->value, q->subvendor, q->subdevice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) chip->codec_probe_mask = q->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) /* check forced option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (chip->codec_probe_mask != -1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) (int)azx_bus(chip)->codec_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) * allow/deny-list for enable_msi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) static const struct snd_pci_quirk msi_deny_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static void check_msi(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) const struct snd_pci_quirk *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (enable_msi >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) chip->msi = !!enable_msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) chip->msi = 1; /* enable MSI as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (q) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) dev_info(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) "msi for device %04x:%04x set to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) q->subvendor, q->subdevice, q->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) chip->msi = q->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) /* NVidia chipsets seem to cause troubles with MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) dev_info(chip->card->dev, "Disabling MSI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) chip->msi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) /* check the snoop mode availability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) static void azx_check_snoop_available(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) int snoop = hda_snoop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (snoop >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) dev_info(chip->card->dev, "Force to %s mode by module option\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) snoop ? "snoop" : "non-snoop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) chip->snoop = snoop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) chip->uc_buffer = !snoop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) snoop = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) chip->driver_type == AZX_DRIVER_VIA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /* force to non-snoop mode for a new VIA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) * when BIOS is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) pci_read_config_byte(chip->pci, 0x42, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) chip->pci->revision == 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) snoop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) snoop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) chip->snoop = snoop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (!snoop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) dev_info(chip->card->dev, "Force to non-snoop mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* C-Media requires non-cached pages only for CORB/RIRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (chip->driver_type != AZX_DRIVER_CMEDIA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) chip->uc_buffer = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static void azx_probe_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) azx_probe_continue(&hda->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static int default_bdl_pos_adj(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) /* some exceptions: Atoms seem problematic with value 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) switch (chip->pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) case 0x0f04: /* Baytrail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) case 0x2284: /* Braswell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) return 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) switch (chip->driver_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) case AZX_DRIVER_ICH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) case AZX_DRIVER_PCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) return 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) * constructor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) static const struct hda_controller_ops pci_hda_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) static int azx_create(struct snd_card *card, struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) int dev, unsigned int driver_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) struct azx **rchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .dev_disconnect = azx_dev_disconnect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .dev_free = azx_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) struct hda_intel *hda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) *rchip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) err = pci_enable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (!hda) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) chip = &hda->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) mutex_init(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) chip->ops = &pci_hda_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) chip->driver_caps = driver_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) chip->driver_type = driver_caps & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) check_msi(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) chip->dev_index = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) INIT_LIST_HEAD(&chip->pcm_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) INIT_LIST_HEAD(&hda->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) init_vga_switcheroo(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) init_completion(&hda->probe_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) if (single_cmd < 0) /* allow fallback to single_cmd at errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) chip->fallback_to_single_cmd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) else /* explicitly set to single_cmd or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) chip->single_cmd = single_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) azx_check_snoop_available(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (bdl_pos_adj[dev] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) chip->bdl_pos_adj = default_bdl_pos_adj(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) chip->bdl_pos_adj = bdl_pos_adj[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) err = azx_bus_init(chip, model[dev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) /* use the non-cached pages in non-snoop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (!azx_snoop(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (chip->driver_type == AZX_DRIVER_NVIDIA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) chip->bus.core.needs_damn_long_delay = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) check_probe_mask(chip, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) dev_err(card->dev, "Error creating device [card]!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) azx_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) /* continue probing in work context as may trigger request module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) *rchip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) static int azx_first_init(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) int dev = chip->dev_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) struct pci_dev *pci = chip->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) struct snd_card *card = chip->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) unsigned short gcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) unsigned int dma_bits = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) #if BITS_PER_LONG != 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) /* Fix up base address on ULI M5461 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) if (chip->driver_type == AZX_DRIVER_ULI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) u16 tmp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) pci_read_config_word(pci, 0x40, &tmp3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) pci_write_config_word(pci, 0x40, tmp3 | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) err = pci_request_regions(pci, "ICH HD audio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) chip->region_requested = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) bus->addr = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) bus->remap_addr = pci_ioremap_bar(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) if (bus->remap_addr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) dev_err(card->dev, "ioremap error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) if (chip->driver_type == AZX_DRIVER_SKL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) snd_hdac_bus_parse_capabilities(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) * Some Intel CPUs has always running timer (ART) feature and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) * controller may have Global time sync reporting capability, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) * check both of these before declaring synchronized time reporting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) chip->gts_present = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) chip->gts_present = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (chip->msi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) dev_dbg(card->dev, "Disabling 64bit MSI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) pci->no_64bit_msi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (pci_enable_msi(pci) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) chip->msi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) gcap = azx_readw(chip, GCAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) /* AMD devices support 40 or 48bit DMA, take the safe one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) dma_bits = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) /* disable SB600 64bit support for safety */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) struct pci_dev *p_smbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) dma_bits = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) PCI_DEVICE_ID_ATI_SBX00_SMBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if (p_smbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) if (p_smbus->revision < 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) gcap &= ~AZX_GCAP_64OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) pci_dev_put(p_smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) /* NVidia hardware normally only supports up to 40 bits of DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) dma_bits = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) /* disable 64bit DMA address on some devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) dev_dbg(card->dev, "Disabling 64bit DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) gcap &= ~AZX_GCAP_64OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /* disable buffer size rounding to 128-byte multiples if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (align_buffer_size >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) chip->align_buffer_size = !!align_buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) chip->align_buffer_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) chip->align_buffer_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) /* allow 64bit DMA address if supported by H/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) if (!(gcap & AZX_GCAP_64OK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) dma_bits = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) /* read number of streams from GCAP register instead of using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) * hardcoded value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) chip->capture_streams = (gcap >> 8) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) chip->playback_streams = (gcap >> 12) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) if (!chip->playback_streams && !chip->capture_streams) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) /* gcap didn't give any info, switching to old method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) switch (chip->driver_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) case AZX_DRIVER_ULI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) chip->playback_streams = ULI_NUM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) chip->capture_streams = ULI_NUM_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) case AZX_DRIVER_ATIHDMI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) case AZX_DRIVER_ATIHDMI_NS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) chip->capture_streams = ATIHDMI_NUM_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) case AZX_DRIVER_GENERIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) chip->playback_streams = ICH6_NUM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) chip->capture_streams = ICH6_NUM_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) chip->capture_index_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) chip->playback_index_offset = chip->capture_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) chip->num_streams = chip->playback_streams + chip->capture_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) /* sanity check for the SDxCTL.STRM field overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) if (chip->num_streams > 15 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) dev_warn(chip->card->dev, "number of I/O streams is %d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) "forcing separate stream tags", chip->num_streams);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) /* initialize streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) err = azx_init_streams(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) err = azx_alloc_stream_pages(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) /* initialize chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) azx_init_pci(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) snd_hdac_i915_set_bclk(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) /* codec detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if (!azx_bus(chip)->codec_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) dev_err(card->dev, "no codecs found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) /* keep running the rest for the runtime PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (azx_acquire_irq(chip, 0) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) strcpy(card->driver, "HDA-Intel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) strlcpy(card->shortname, driver_short_names[chip->driver_type],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) sizeof(card->shortname));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) snprintf(card->longname, sizeof(card->longname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) "%s at 0x%lx irq %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) card->shortname, bus->addr, bus->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) #ifdef CONFIG_SND_HDA_PATCH_LOADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) /* callback from request_firmware_nowait() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) static void azx_firmware_cb(const struct firmware *fw, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) struct snd_card *card = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) struct azx *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) chip->fw = fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) dev_err(card->dev, "Cannot load firmware, continue without patching\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) if (!chip->disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) /* continue probing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) azx_probe_continue(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) static int disable_msi_reset_irq(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) free_irq(bus->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) bus->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) chip->card->sync_irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) pci_disable_msi(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) chip->msi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) err = azx_acquire_irq(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) struct vm_area_struct *area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) struct azx *chip = apcm->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) if (chip->uc_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) /* Denylist for skipping the whole probe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) * some HD-audio PCI entries are exposed without any codecs, and such devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) * should be ignored from the beginning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) static const struct pci_device_id driver_denylist[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static const struct hda_controller_ops pci_hda_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .disable_msi_reset_irq = disable_msi_reset_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .pcm_mmap_prepare = pcm_mmap_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .position_check = azx_position_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) static int azx_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) struct hda_intel *hda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) bool schedule_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (pci_match_id(driver_denylist, pci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) dev_info(&pci->dev, "Skipping the device on the denylist\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) * stop probe if another Intel's DSP driver should be activated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) if (dmic_detect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) err = snd_intel_dsp_driver_probe(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) dev_err(&pci->dev, "Error creating card!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) card->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) err = register_vga_switcheroo(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) dev_err(card->dev, "Error registering vga_switcheroo client\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (check_hdmi_disabled(pci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) dev_info(card->dev, "VGA controller is disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) dev_info(card->dev, "Delaying initialization\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) chip->disabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) schedule_probe = !chip->disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) #ifdef CONFIG_SND_HDA_PATCH_LOADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) if (patch[dev] && *patch[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) dev_info(card->dev, "Applying patch firmware '%s'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) patch[dev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) &pci->dev, GFP_KERNEL, card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) azx_firmware_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) schedule_probe = false; /* continued in azx_firmware_cb() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) #endif /* CONFIG_SND_HDA_PATCH_LOADER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) #ifndef CONFIG_SND_HDA_I915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) if (CONTROLLER_IN_GPU(pci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) if (schedule_probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) schedule_delayed_work(&hda->probe_work, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) if (chip->disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) complete_all(&hda->probe_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) /* On some boards setting power_save to a non 0 value leads to clicking /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) * popping sounds when ever we enter/leave powersaving mode. Ideally we would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) * figure out how to avoid these sounds, but that is not always feasible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) * So we keep a list of devices where we disable powersaving as its known
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) * to causes problems on these devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) static const struct snd_pci_quirk power_save_denylist[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) /* https://bugs.launchpad.net/bugs/1821663 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) /* https://bugs.launchpad.net/bugs/1821663 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) static void set_default_power_save(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) int val = power_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) if (pm_blacklist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) const struct snd_pci_quirk *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) if (q && val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) q->subvendor, q->subdevice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) snd_hda_set_power_save(&chip->bus, val * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) [AZX_DRIVER_NVIDIA] = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) [AZX_DRIVER_TERA] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) static int azx_probe_continue(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) struct pci_dev *pci = chip->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) int dev = chip->dev_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) if (chip->disabled || hda->init_failed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) if (hda->probe_retry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) goto probe_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) to_hda_bus(bus)->bus_probing = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) hda->probe_continued = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) /* bind with i915 if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) err = snd_hdac_i915_init(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) /* if the controller is bound only with HDMI/DP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) * (for HSW and BDW), we need to abort the probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) * for other chips, still continue probing as other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) * codecs can be on the same link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) if (CONTROLLER_IN_GPU(pci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) /* don't bother any longer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) /* HSW/BDW controllers need this power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) if (CONTROLLER_IN_GPU(pci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) hda->need_i915_power = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) /* Request display power well for the HDA controller or codec. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) * Haswell/Broadwell, both the display HDA controller and codec need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) * this power. For other platforms, like Baytrail/Braswell, only the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) * display codec needs the power and it can be released after probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) display_power(chip, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) err = azx_first_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) #ifdef CONFIG_SND_HDA_INPUT_BEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) chip->beep_mode = beep_mode[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) /* create codec instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) if (bus->codec_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) #ifdef CONFIG_SND_HDA_PATCH_LOADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) if (chip->fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) err = snd_hda_load_patch(&chip->bus, chip->fw->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) chip->fw->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) #ifndef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) release_firmware(chip->fw); /* no longer needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) chip->fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) probe_retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) if (bus->codec_mask && !(probe_only[dev] & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) err = azx_codec_configure(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) ++hda->probe_retry < 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) schedule_delayed_work(&hda->probe_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) return 0; /* keep things up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) err = snd_card_register(chip->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) setup_vga_switcheroo_runtime_pm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) chip->running = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) azx_add_card_list(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) set_default_power_save(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) if (azx_has_pm_runtime(chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) pm_runtime_use_autosuspend(&pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) pm_runtime_allow(&pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) pm_runtime_put_autosuspend(&pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) pci_set_drvdata(pci, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) snd_card_free(chip->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) if (!hda->need_i915_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) display_power(chip, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) complete_all(&hda->probe_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) to_hda_bus(bus)->bus_probing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) hda->probe_retry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) static void azx_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) struct snd_card *card = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) struct hda_intel *hda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) if (card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) /* cancel the pending probing work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) hda = container_of(chip, struct hda_intel, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) /* FIXME: below is an ugly workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) * Both device_release_driver() and driver_probe_device()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) * take *both* the device's and its parent's lock before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) * calling the remove() and probe() callbacks. The codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) * probe takes the locks of both the codec itself and its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) * parent, i.e. the PCI controller dev. Meanwhile, when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) * the PCI controller is unbound, it takes its lock, too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) * ==> ouch, a deadlock!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) * As a workaround, we unlock temporarily here the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) * device during cancel_work_sync() call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) device_unlock(&pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) cancel_delayed_work_sync(&hda->probe_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) device_lock(&pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) static void azx_shutdown(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) struct snd_card *card = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) if (!card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) if (chip && chip->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) __azx_shutdown_chip(chip, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) /* PCI IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) static const struct pci_device_id azx_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) /* CPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) { PCI_DEVICE(0x8086, 0x1c20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) /* PBG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) { PCI_DEVICE(0x8086, 0x1d20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) /* Panther Point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) { PCI_DEVICE(0x8086, 0x1e20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) /* Lynx Point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) { PCI_DEVICE(0x8086, 0x8c20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) /* 9 Series */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) { PCI_DEVICE(0x8086, 0x8ca0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) /* Wellsburg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) { PCI_DEVICE(0x8086, 0x8d20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) { PCI_DEVICE(0x8086, 0x8d21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) /* Lewisburg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) { PCI_DEVICE(0x8086, 0xa1f0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) { PCI_DEVICE(0x8086, 0xa270),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) /* Lynx Point-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) { PCI_DEVICE(0x8086, 0x9c20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) /* Lynx Point-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) { PCI_DEVICE(0x8086, 0x9c21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) /* Wildcat Point-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) { PCI_DEVICE(0x8086, 0x9ca0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) /* Sunrise Point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) { PCI_DEVICE(0x8086, 0xa170),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) /* Sunrise Point-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) { PCI_DEVICE(0x8086, 0x9d70),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) /* Kabylake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) { PCI_DEVICE(0x8086, 0xa171),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) /* Kabylake-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) { PCI_DEVICE(0x8086, 0x9d71),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) /* Kabylake-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) { PCI_DEVICE(0x8086, 0xa2f0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) /* Coffelake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) { PCI_DEVICE(0x8086, 0xa348),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) /* Cannonlake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) { PCI_DEVICE(0x8086, 0x9dc8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) /* CometLake-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) { PCI_DEVICE(0x8086, 0x02C8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) /* CometLake-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) { PCI_DEVICE(0x8086, 0x06C8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) { PCI_DEVICE(0x8086, 0xf1c8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) /* CometLake-S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) { PCI_DEVICE(0x8086, 0xa3f0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) /* CometLake-R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) { PCI_DEVICE(0x8086, 0xf0c8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) /* Icelake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) { PCI_DEVICE(0x8086, 0x34c8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) /* Icelake-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) { PCI_DEVICE(0x8086, 0x3dc8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) /* Jasperlake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) { PCI_DEVICE(0x8086, 0x38c8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) { PCI_DEVICE(0x8086, 0x4dc8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) /* Tigerlake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) { PCI_DEVICE(0x8086, 0xa0c8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) /* Tigerlake-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) { PCI_DEVICE(0x8086, 0x43c8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) /* DG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) { PCI_DEVICE(0x8086, 0x490d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) /* DG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) { PCI_DEVICE(0x8086, 0x4f90),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) { PCI_DEVICE(0x8086, 0x4f91),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) { PCI_DEVICE(0x8086, 0x4f92),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) /* Alderlake-S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) { PCI_DEVICE(0x8086, 0x7ad0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) /* Alderlake-P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) { PCI_DEVICE(0x8086, 0x51c8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) /* Elkhart Lake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) { PCI_DEVICE(0x8086, 0x4b55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) { PCI_DEVICE(0x8086, 0x4b58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) /* Broxton-P(Apollolake) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) { PCI_DEVICE(0x8086, 0x5a98),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) /* Broxton-T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) { PCI_DEVICE(0x8086, 0x1a98),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) /* Gemini-Lake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) { PCI_DEVICE(0x8086, 0x3198),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) /* Haswell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) { PCI_DEVICE(0x8086, 0x0a0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) { PCI_DEVICE(0x8086, 0x0c0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) { PCI_DEVICE(0x8086, 0x0d0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) /* Broadwell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) { PCI_DEVICE(0x8086, 0x160c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) /* 5 Series/3400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) { PCI_DEVICE(0x8086, 0x3b56),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) /* Poulsbo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) { PCI_DEVICE(0x8086, 0x811b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) /* Oaktrail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) { PCI_DEVICE(0x8086, 0x080a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) /* BayTrail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) { PCI_DEVICE(0x8086, 0x0f04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) /* Braswell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) { PCI_DEVICE(0x8086, 0x2284),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) /* ICH6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) { PCI_DEVICE(0x8086, 0x2668),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) /* ICH7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) { PCI_DEVICE(0x8086, 0x27d8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) /* ESB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) { PCI_DEVICE(0x8086, 0x269a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) /* ICH8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) { PCI_DEVICE(0x8086, 0x284b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) /* ICH9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) { PCI_DEVICE(0x8086, 0x293e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) /* ICH9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) { PCI_DEVICE(0x8086, 0x293f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) /* ICH10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) { PCI_DEVICE(0x8086, 0x3a3e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) /* ICH10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) { PCI_DEVICE(0x8086, 0x3a6e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) /* Generic Intel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .class_mask = 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) /* ATI SB 450/600/700/800/900 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) { PCI_DEVICE(0x1002, 0x437b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) { PCI_DEVICE(0x1002, 0x4383),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) /* AMD Hudson */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) { PCI_DEVICE(0x1022, 0x780d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) /* AMD, X370 & co */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) { PCI_DEVICE(0x1022, 0x1457),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) /* AMD, X570 & co */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) { PCI_DEVICE(0x1022, 0x1487),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) /* AMD Stoney */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) { PCI_DEVICE(0x1022, 0x157a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) AZX_DCAPS_PM_RUNTIME },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) /* AMD Raven */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) { PCI_DEVICE(0x1022, 0x15e3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) /* ATI HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) { PCI_DEVICE(0x1002, 0x0002),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) { PCI_DEVICE(0x1002, 0x1308),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) { PCI_DEVICE(0x1002, 0x157a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) { PCI_DEVICE(0x1002, 0x15b3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) { PCI_DEVICE(0x1002, 0x793b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) { PCI_DEVICE(0x1002, 0x7919),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) { PCI_DEVICE(0x1002, 0x960f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) { PCI_DEVICE(0x1002, 0x970f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) { PCI_DEVICE(0x1002, 0x9840),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) { PCI_DEVICE(0x1002, 0xaa00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) { PCI_DEVICE(0x1002, 0xaa08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) { PCI_DEVICE(0x1002, 0xaa10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) { PCI_DEVICE(0x1002, 0xaa18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) { PCI_DEVICE(0x1002, 0xaa20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) { PCI_DEVICE(0x1002, 0xaa28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) { PCI_DEVICE(0x1002, 0xaa30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) { PCI_DEVICE(0x1002, 0xaa38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) { PCI_DEVICE(0x1002, 0xaa40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) { PCI_DEVICE(0x1002, 0xaa48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) { PCI_DEVICE(0x1002, 0xaa50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) { PCI_DEVICE(0x1002, 0xaa58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) { PCI_DEVICE(0x1002, 0xaa60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) { PCI_DEVICE(0x1002, 0xaa68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) { PCI_DEVICE(0x1002, 0xaa80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) { PCI_DEVICE(0x1002, 0xaa88),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) { PCI_DEVICE(0x1002, 0xaa90),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) { PCI_DEVICE(0x1002, 0xaa98),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) { PCI_DEVICE(0x1002, 0x9902),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) { PCI_DEVICE(0x1002, 0xaaa0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) { PCI_DEVICE(0x1002, 0xaaa8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) { PCI_DEVICE(0x1002, 0xaab0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) { PCI_DEVICE(0x1002, 0xaac0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) { PCI_DEVICE(0x1002, 0xaac8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) { PCI_DEVICE(0x1002, 0xaad8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) AZX_DCAPS_PM_RUNTIME },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) { PCI_DEVICE(0x1002, 0xaae0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) AZX_DCAPS_PM_RUNTIME },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) { PCI_DEVICE(0x1002, 0xaae8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) AZX_DCAPS_PM_RUNTIME },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) { PCI_DEVICE(0x1002, 0xaaf0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) AZX_DCAPS_PM_RUNTIME },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) { PCI_DEVICE(0x1002, 0xaaf8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) AZX_DCAPS_PM_RUNTIME },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) { PCI_DEVICE(0x1002, 0xab00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) AZX_DCAPS_PM_RUNTIME },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) { PCI_DEVICE(0x1002, 0xab08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) AZX_DCAPS_PM_RUNTIME },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) { PCI_DEVICE(0x1002, 0xab10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) AZX_DCAPS_PM_RUNTIME },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) { PCI_DEVICE(0x1002, 0xab18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) AZX_DCAPS_PM_RUNTIME },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) { PCI_DEVICE(0x1002, 0xab20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) AZX_DCAPS_PM_RUNTIME },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) { PCI_DEVICE(0x1002, 0xab28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) AZX_DCAPS_PM_RUNTIME },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) { PCI_DEVICE(0x1002, 0xab38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) AZX_DCAPS_PM_RUNTIME },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) /* VIA VT8251/VT8237A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) /* VIA GFX VT7122/VX900 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) /* VIA GFX VT6122/VX11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) /* SIS966 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) /* ULI M5461 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) /* NVIDIA MCP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) .class_mask = 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) /* Teradici */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) { PCI_DEVICE(0x6549, 0x1200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) { PCI_DEVICE(0x6549, 0x2200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) /* Creative X-Fi (CA0110-IBG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) /* CTHDA chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) { PCI_DEVICE(0x1102, 0x0010),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) { PCI_DEVICE(0x1102, 0x0012),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) #if !IS_ENABLED(CONFIG_SND_CTXFI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) /* the following entry conflicts with snd-ctxfi driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) * as ctxfi driver mutates from HD-audio to native mode with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) * a special command sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) .class_mask = 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) /* this entry seems still valid -- i.e. without emu20kx chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) { PCI_DEVICE(0x1102, 0x0009),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) /* CM8888 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) { PCI_DEVICE(0x13f6, 0x5011),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) .driver_data = AZX_DRIVER_CMEDIA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) /* Vortex86MX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) /* VMware HDAudio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) .class_mask = 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) .class_mask = 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) /* Zhaoxin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) MODULE_DEVICE_TABLE(pci, azx_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) /* pci_driver definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) static struct pci_driver azx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) .id_table = azx_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) .probe = azx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) .remove = azx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) .shutdown = azx_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) .pm = AZX_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) module_pci_driver(azx_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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