Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Common functionality for the alsa driver code base for HD Audio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef __SOUND_HDA_CONTROLLER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define __SOUND_HDA_CONTROLLER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/timecounter.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <sound/hda_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <sound/hda_register.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define AZX_MAX_CODECS		HDA_MAX_CODECS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AZX_DEFAULT_CODECS	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* driver quirks (capabilities) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* bits 0-7 are used for indicating driver type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AZX_DCAPS_NO_TCSEL	(1 << 8)	/* No Intel TCSEL bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AZX_DCAPS_NO_MSI	(1 << 9)	/* No MSI support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AZX_DCAPS_SNOOP_MASK	(3 << 10)	/* snoop type mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AZX_DCAPS_SNOOP_OFF	(1 << 12)	/* snoop default off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #ifdef CONFIG_SND_HDA_I915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AZX_DCAPS_I915_COMPONENT (1 << 13)	/* bind with i915 gfx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AZX_DCAPS_I915_COMPONENT 0		/* NOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* 14 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)	/* X-Fi workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AZX_DCAPS_POSFIX_LPIB	(1 << 16)	/* Use LPIB as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AZX_DCAPS_AMD_WORKAROUND (1 << 17)	/* AMD-specific workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AZX_DCAPS_NO_64BIT	(1 << 18)	/* No 64bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* 19 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AZX_DCAPS_OLD_SSYNC	(1 << 20)	/* Old SSYNC reg for ICH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AZX_DCAPS_NO_ALIGN_BUFSIZE (1 << 21)	/* no buffer size alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* 22 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)	/* BDLE in 4k boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* 24 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)	/* Take LPIB as delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AZX_DCAPS_PM_RUNTIME	(1 << 26)	/* runtime PM support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define AZX_DCAPS_RETRY_PROBE	(1 << 27)	/* retry probe if no codec is configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28)	/* CORBRP clears itself after reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AZX_DCAPS_NO_MSI64      (1 << 29)	/* Stick to 32-bit MSIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define AZX_DCAPS_SEPARATE_STREAM_TAG	(1 << 30) /* capture and playback use separate stream tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	AZX_SNOOP_TYPE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	AZX_SNOOP_TYPE_SCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	AZX_SNOOP_TYPE_ATI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	AZX_SNOOP_TYPE_NVIDIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) struct azx_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct hdac_stream core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	unsigned int irq_pending:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 * For VIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 *  A flag to ensure DMA position is 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 *  when link position is not greater than FIFO size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	unsigned int insufficient:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define azx_stream(dev)		(&(dev)->core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define stream_to_azx_dev(s)	container_of(s, struct azx_dev, core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) struct azx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* Functions to read/write to hda registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) struct hda_controller_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	/* Disable msi if supported, PCI only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	int (*disable_msi_reset_irq)(struct azx *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	void (*pcm_mmap_prepare)(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 				 struct vm_area_struct *area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* Check if current position is acceptable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int (*position_check)(struct azx *chip, struct azx_dev *azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	/* enable/disable the link power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	int (*link_power)(struct azx *chip, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) struct azx_pcm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct azx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct hda_codec *codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct hda_pcm *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) typedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) typedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) struct azx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct hda_bus bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	int dev_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* chip type specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	int driver_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	unsigned int driver_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	int playback_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int playback_index_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	int capture_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	int capture_index_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int num_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int jackpoll_interval; /* jack poll interval in jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* Register interaction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	const struct hda_controller_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	/* position adjustment callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	azx_get_pos_callback_t get_position[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	azx_get_delay_callback_t get_delay[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* locks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct mutex open_mutex; /* Prevents concurrent open/close operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct list_head pcm_list; /* azx_pcm list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* HD codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	int  codec_probe_mask; /* copied from probe_mask option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned int beep_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifdef CONFIG_SND_HDA_PATCH_LOADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int bdl_pos_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	unsigned int running:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	unsigned int fallback_to_single_cmd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	unsigned int single_cmd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	unsigned int msi:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	unsigned int probing:1; /* codec probing phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	unsigned int snoop:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	unsigned int uc_buffer:1; /* non-cached pages for stream buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	unsigned int align_buffer_size:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	unsigned int region_requested:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	unsigned int disabled:1; /* disabled by vga_switcheroo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	unsigned int pm_prepared:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	/* GTS present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	unsigned int gts_present:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #ifdef CONFIG_SND_HDA_DSP_LOADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct azx_dev saved_azx_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define azx_bus(chip)	(&(chip)->bus.core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define bus_to_azx(_bus)	container_of(_bus, struct azx, bus.core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static inline bool azx_snoop(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return !IS_ENABLED(CONFIG_X86) || chip->snoop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * macros for easy use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define azx_writel(chip, reg, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	snd_hdac_chip_writel(azx_bus(chip), reg, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define azx_readl(chip, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	snd_hdac_chip_readl(azx_bus(chip), reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define azx_writew(chip, reg, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	snd_hdac_chip_writew(azx_bus(chip), reg, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define azx_readw(chip, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	snd_hdac_chip_readw(azx_bus(chip), reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define azx_writeb(chip, reg, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	snd_hdac_chip_writeb(azx_bus(chip), reg, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define azx_readb(chip, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	snd_hdac_chip_readb(azx_bus(chip), reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define azx_has_pm_runtime(chip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	((chip)->driver_caps & AZX_DCAPS_PM_RUNTIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* PCM setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline struct azx_dev *get_azx_dev(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	return substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int azx_get_position(struct azx *chip, struct azx_dev *azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Stream control. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void azx_stop_all_streams(struct azx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Allocation functions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define azx_alloc_stream_pages(chip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	snd_hdac_bus_alloc_stream_pages(azx_bus(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define azx_free_stream_pages(chip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	snd_hdac_bus_free_stream_pages(azx_bus(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Low level azx interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) void azx_init_chip(struct azx *chip, bool full_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void azx_stop_chip(struct azx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define azx_enter_link_reset(chip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	snd_hdac_bus_enter_link_reset(azx_bus(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) irqreturn_t azx_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Codec interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int azx_bus_init(struct azx *chip, const char *model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int azx_probe_codecs(struct azx *chip, unsigned int max_slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int azx_codec_configure(struct azx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int azx_init_streams(struct azx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) void azx_free_streams(struct azx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #endif /* __SOUND_HDA_CONTROLLER_H */