^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Implementation of primary alsa driver code base for Intel HD Audio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright(c) 2004 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * PeiSen Hou <pshou@realtek.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* for art-tsc conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/tsc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "hda_controller.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "hda_local.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CREATE_TRACE_POINTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "hda_controller_trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* DSP lock helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define dsp_lock(dev) snd_hdac_dsp_lock(azx_stream(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define dsp_unlock(dev) snd_hdac_dsp_unlock(azx_stream(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define dsp_is_locked(dev) snd_hdac_stream_is_locked(azx_stream(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* assign a stream for the PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static inline struct azx_dev *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct hdac_stream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) s = snd_hdac_stream_assign(azx_bus(chip), substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return stream_to_azx_dev(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* release the assigned stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static inline void azx_release_device(struct azx_dev *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) snd_hdac_stream_release(azx_stream(azx_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline struct hda_pcm_stream *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) to_hda_pcm_stream(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return &apcm->info->stream[substream->stream];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u64 nsec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u64 codec_frames, codec_nsecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (!hinfo->ops.get_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) codec_nsecs = div_u64(codec_frames * 1000000000LL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) substream->runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return nsec + codec_nsecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * PCM ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int azx_pcm_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct azx *chip = apcm->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct azx_dev *azx_dev = get_azx_dev(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) trace_azx_pcm_close(chip, azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mutex_lock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) azx_release_device(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (hinfo->ops.close)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) hinfo->ops.close(hinfo, apcm->codec, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) snd_hda_power_down(apcm->codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mutex_unlock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) snd_hda_codec_pcm_put(apcm->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct azx *chip = apcm->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct azx_dev *azx_dev = get_azx_dev(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) trace_azx_pcm_hw_params(chip, azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dsp_lock(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (dsp_is_locked(azx_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) azx_dev->core.bufsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) azx_dev->core.period_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) azx_dev->core.format_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dsp_unlock(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct azx_dev *azx_dev = get_azx_dev(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* reset BDL address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dsp_lock(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (!dsp_is_locked(azx_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) snd_hdac_stream_cleanup(azx_stream(azx_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) azx_stream(azx_dev)->prepared = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dsp_unlock(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int azx_pcm_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct azx *chip = apcm->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct azx_dev *azx_dev = get_azx_dev(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int format_val, stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct hda_spdif_out *spdif =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned short ctls = spdif ? spdif->ctls : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) trace_azx_pcm_prepare(chip, azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dsp_lock(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (dsp_is_locked(azx_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) snd_hdac_stream_reset(azx_stream(azx_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) format_val = snd_hdac_calc_stream_format(runtime->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) runtime->channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) runtime->format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) hinfo->maxbps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ctls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (!format_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "invalid format_val, rate=%d, ch=%d, format=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) runtime->rate, runtime->channels, runtime->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) snd_hdac_stream_setup(azx_stream(azx_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) stream_tag = azx_dev->core.stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* CA-IBG chips need the playback stream starting from 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) stream_tag > chip->capture_streams)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) stream_tag -= chip->capture_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) azx_dev->core.format_val, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) azx_stream(azx_dev)->prepared = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dsp_unlock(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct azx *chip = apcm->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct azx_dev *azx_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct snd_pcm_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct hdac_stream *hstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bool start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int sbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int sync_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) azx_dev = get_azx_dev(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) trace_azx_pcm_trigger(chip, azx_dev, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) hstr = azx_stream(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) sync_reg = AZX_REG_OLD_SSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) sync_reg = AZX_REG_SSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (dsp_is_locked(azx_dev) || !hstr->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) start = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) start = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (s->pcm->card != substream->pcm->card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) azx_dev = get_azx_dev(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) sbits |= 1 << azx_dev->core.index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) spin_lock(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* first, set SYNC bits of corresponding streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (s->pcm->card != substream->pcm->card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) azx_dev = get_azx_dev(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) azx_dev->insufficient = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) snd_hdac_stream_start(azx_stream(azx_dev), true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) snd_hdac_stream_stop(azx_stream(azx_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) spin_unlock(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) snd_hdac_stream_sync(hstr, start, sbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spin_lock(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* reset SYNC bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) snd_hdac_stream_timecounter_init(hstr, sbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spin_unlock(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int azx_get_position(struct azx *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct azx_dev *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct snd_pcm_substream *substream = azx_dev->core.substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int stream = substream->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (chip->get_position[stream])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pos = chip->get_position[stream](chip, azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) else /* use the position buffer as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pos = azx_get_pos_posbuf(chip, azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (pos >= azx_dev->core.bufsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (substream->runtime) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (chip->get_delay[stream])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) delay += chip->get_delay[stream](chip, azx_dev, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (hinfo->ops.get_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) delay += hinfo->ops.get_delay(hinfo, apcm->codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) substream->runtime->delay = delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) trace_azx_get_position(chip, azx_dev, pos, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) EXPORT_SYMBOL_GPL(azx_get_position);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct azx *chip = apcm->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct azx_dev *azx_dev = get_azx_dev(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return bytes_to_frames(substream->runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) azx_get_position(chip, azx_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * azx_scale64: Scale base by mult/div while not overflowing sanely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * Derived from scale64_check_overflow in kernel/time/timekeeping.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * is about 384307 ie ~4.5 days.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * This scales the calculation so that overflow will happen but after 2^64 /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * 48000 secs, which is pretty large!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * In caln below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * base may overflow, but since there isn’t any additional division
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * performed on base it’s OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * rem can’t overflow because both are 32-bit values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static u64 azx_scale64(u64 base, u32 num, u32 den)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u64 rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) rem = do_div(base, den);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) base *= num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) rem *= num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) do_div(rem, den);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return base + rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int azx_get_sync_time(ktime_t *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct system_counterval_t *system, void *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct snd_pcm_substream *substream = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct azx_dev *azx_dev = get_azx_dev(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct azx *chip = apcm->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct snd_pcm_runtime *runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u64 ll_counter, ll_counter_l, ll_counter_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u64 tsc_counter, tsc_counter_l, tsc_counter_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u32 wallclk_ctr, wallclk_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) bool direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u32 dma_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 retry_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) direction = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) direction = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dma_select = (direction << GTSCC_CDMAS_DMA_DIR_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) (azx_dev->core.stream_tag - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) snd_hdac_chip_writel(azx_bus(chip), GTSCC, dma_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Enable the capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) snd_hdac_chip_updatel(azx_bus(chip), GTSCC, 0, GTSCC_TSCCI_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) while (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) GTSCC_TSCCD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_err(chip->card->dev, "GTSCC capture Timedout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Read wall clock counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Read TSC counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Read Link counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Ack: registers read done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) snd_hdac_chip_writel(azx_bus(chip), GTSCC, GTSCC_TSCCD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) tsc_counter = (tsc_counter_h << TSCCU_CCU_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) tsc_counter_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ll_counter = (ll_counter_h << LLPC_CCU_SHIFT) | ll_counter_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) wallclk_cycles = wallclk_ctr & WALFCC_CIF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * An error occurs near frame "rollover". The clocks in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * frame value indicates whether this error may have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * occurred. Here we use the value of 10 i.e.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * HDA_MAX_CYCLE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (wallclk_cycles < HDA_MAX_CYCLE_VALUE - HDA_MAX_CYCLE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) && wallclk_cycles > HDA_MAX_CYCLE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * Sleep before we read again, else we may again get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * value near to MAX_CYCLE. Try to sleep for different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * amount of time so we dont hit the same number again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) udelay(retry_count++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) } while (retry_count != HDA_MAX_CYCLE_READ_RETRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (retry_count == HDA_MAX_CYCLE_READ_RETRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err_ratelimited(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "Error in WALFCC cycle count\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *device = ns_to_ktime(azx_scale64(ll_counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) NSEC_PER_SEC, runtime->rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) *system = convert_art_to_tsc(tsc_counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int azx_get_sync_time(ktime_t *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct system_counterval_t *system, void *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int azx_get_crosststamp(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct system_device_crosststamp *xtstamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return get_device_system_crosststamp(azx_get_sync_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) substream, NULL, xtstamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static inline bool is_link_time_supported(struct snd_pcm_runtime *runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct snd_pcm_audio_tstamp_config *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ts->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int azx_get_time_info(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct timespec64 *system_ts, struct timespec64 *audio_ts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct azx_dev *azx_dev = get_azx_dev(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct system_device_crosststamp xtstamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u64 nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) snd_pcm_gettime(substream->runtime, system_ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) nsec = timecounter_read(&azx_dev->core.tc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) nsec = div_u64(nsec, 3); /* can be optimized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (audio_tstamp_config->report_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) nsec = azx_adjust_codec_delay(substream, nsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) *audio_ts = ns_to_timespec64(nsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) } else if (is_link_time_supported(runtime, audio_tstamp_config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = azx_get_crosststamp(substream, &xtstamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) switch (runtime->tstamp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) *system_ts = ktime_to_timespec64(xtstamp.sys_monoraw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) *system_ts = ktime_to_timespec64(xtstamp.sys_realtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) *audio_ts = ktime_to_timespec64(xtstamp.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) audio_tstamp_report->actual_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) audio_tstamp_report->accuracy_report = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* 24 MHz WallClock == 42ns resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) audio_tstamp_report->accuracy = 42;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const struct snd_pcm_hardware azx_pcm_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* No full-resume yet implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* SNDRV_PCM_INFO_RESUME |*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) SNDRV_PCM_INFO_SYNC_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) SNDRV_PCM_INFO_HAS_LINK_ATIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .rate_min = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .buffer_bytes_max = AZX_MAX_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .period_bytes_min = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .periods_max = AZX_MAX_FRAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int azx_pcm_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct azx *chip = apcm->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct azx_dev *azx_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int buff_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) snd_hda_codec_pcm_get(apcm->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mutex_lock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) azx_dev = azx_assign_device(chip, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) trace_azx_pcm_open(chip, azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (azx_dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) runtime->private_data = azx_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) runtime->hw = azx_pcm_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (chip->gts_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) runtime->hw.info |= SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) runtime->hw.channels_min = hinfo->channels_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) runtime->hw.channels_max = hinfo->channels_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) runtime->hw.formats = hinfo->formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) runtime->hw.rates = hinfo->rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) snd_pcm_limit_hw_rates(runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* avoid wrap-around with wall-clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 178000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (chip->align_buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* constrain buffer sizes to be multiple of 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) bytes. This is more efficient in terms of memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) access but isn't required by the HDA spec and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) prevents users from specifying exact period/buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) sizes. For example for 44.1kHz, a period size set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) to 20ms will be rounded to 19.59ms. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) buff_step = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Don't enforce steps on buffer sizes, still need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) be multiple of 4 bytes (HDA spec). Tested on Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) HDA controllers, may not work on all devices where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) option needs to be disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) buff_step = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) buff_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) buff_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) snd_hda_power_up(apcm->codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (hinfo->ops.open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) err = hinfo->ops.open(hinfo, apcm->codec, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) azx_release_device(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) goto powerdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) snd_pcm_limit_hw_rates(runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (snd_BUG_ON(!runtime->hw.channels_min) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) snd_BUG_ON(!runtime->hw.channels_max) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) snd_BUG_ON(!runtime->hw.formats) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) snd_BUG_ON(!runtime->hw.rates)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) azx_release_device(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (hinfo->ops.close)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) hinfo->ops.close(hinfo, apcm->codec, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) goto powerdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* disable LINK_ATIME timestamps for capture streams
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) until we figure out how to handle digital inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) mutex_unlock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) powerdown:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) snd_hda_power_down(apcm->codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) mutex_unlock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) snd_hda_codec_pcm_put(apcm->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int azx_pcm_mmap(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct vm_area_struct *area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct azx *chip = apcm->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (chip->ops->pcm_mmap_prepare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) chip->ops->pcm_mmap_prepare(substream, area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return snd_pcm_lib_default_mmap(substream, area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static const struct snd_pcm_ops azx_pcm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .open = azx_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .close = azx_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .hw_params = azx_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .hw_free = azx_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .prepare = azx_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .trigger = azx_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .pointer = azx_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .get_time_info = azx_get_time_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .mmap = azx_pcm_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static void azx_pcm_free(struct snd_pcm *pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct azx_pcm *apcm = pcm->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (apcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) list_del(&apcm->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) apcm->info->pcm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) kfree(apcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct hda_pcm *cpcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct hdac_bus *bus = &_bus->core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct azx *chip = bus_to_azx(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct azx_pcm *apcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int pcm_dev = cpcm->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int s, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int type = SNDRV_DMA_TYPE_DEV_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) list_for_each_entry(apcm, &chip->pcm_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (apcm->pcm->device == pcm_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dev_err(chip->card->dev, "PCM %d already exists\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pcm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (apcm == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) snd_device_free(chip->card, pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) apcm->chip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) apcm->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) apcm->codec = codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) apcm->info = cpcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) pcm->private_data = apcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) pcm->private_free = azx_pcm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) list_add_tail(&apcm->list, &chip->pcm_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) cpcm->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) for (s = 0; s < 2; s++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (cpcm->stream[s].substreams)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* buffer pre-allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (size > MAX_PREALLOC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) size = MAX_PREALLOC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (chip->uc_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) type = SNDRV_DMA_TYPE_DEV_UC_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) snd_pcm_set_managed_buffer_all(pcm, type, chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) size, MAX_PREALLOC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static unsigned int azx_command_addr(u32 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) unsigned int addr = cmd >> 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (addr >= AZX_MAX_CODECS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* receive a response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) unsigned int *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct azx *chip = bus_to_azx(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct hda_bus *hbus = &chip->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) err = snd_hdac_bus_get_response(bus, addr, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (hbus->no_response_fallback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!bus->polling_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dev_warn(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) bus->last_cmd[addr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) bus->polling_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (chip->msi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_warn(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) "No response from codec, disabling MSI: last cmd=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) bus->last_cmd[addr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (chip->ops->disable_msi_reset_irq &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) chip->ops->disable_msi_reset_irq(chip) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (chip->probing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* If this critical timeout happens during the codec probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * phase, this is likely an access to a non-existing codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * slot. Better to return an error and reset the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* no fallback mechanism? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (!chip->fallback_to_single_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* a fatal communication error; need either to reset or to fallback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * to the single_cmd mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) hbus->response_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) "No response from codec, resetting bus: last cmd=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) bus->last_cmd[addr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return -EAGAIN; /* give a chance to retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) bus->last_cmd[addr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) chip->single_cmd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) hbus->response_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) snd_hdac_bus_stop_cmd_io(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * Use the single immediate command instead of CORB/RIRB for simplicity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * Note: according to Intel, this is not preferred use. The command was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * intended for the BIOS only, and may get confused with unsolicited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * responses. So, we shouldn't use it for normal operation from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * I left the codes, however, for debugging/testing purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* receive a response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) int timeout = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) while (timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* check IRV busy bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* reuse rirb.res as the response return value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (printk_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) azx_readw(chip, IRS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) azx_bus(chip)->rirb.res[addr] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* send a command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static int azx_single_send_cmd(struct hdac_bus *bus, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct azx *chip = bus_to_azx(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) unsigned int addr = azx_command_addr(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) int timeout = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) bus->last_cmd[azx_command_addr(val)] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) while (timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* check ICB busy bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* Clear IRV valid bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) azx_writew(chip, IRS, azx_readw(chip, IRS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) AZX_IRS_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) azx_writel(chip, IC, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) azx_writew(chip, IRS, azx_readw(chip, IRS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) AZX_IRS_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return azx_single_wait_for_response(chip, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (printk_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) "send_cmd timeout: IRS=0x%x, val=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) azx_readw(chip, IRS), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* receive a response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) unsigned int *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) *res = bus->rirb.res[addr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * The below are the main callbacks from hda_codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * They are just the skeleton to call sub-callbacks according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * current setting of chip->single_cmd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* send a command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static int azx_send_cmd(struct hdac_bus *bus, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct azx *chip = bus_to_azx(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (chip->disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (chip->single_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return azx_single_send_cmd(bus, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return snd_hdac_bus_send_cmd(bus, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* get a response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static int azx_get_response(struct hdac_bus *bus, unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) unsigned int *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct azx *chip = bus_to_azx(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (chip->disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (chip->single_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return azx_single_get_response(bus, addr, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return azx_rirb_get_response(bus, addr, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static const struct hdac_bus_ops bus_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .command = azx_send_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .get_response = azx_get_response,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #ifdef CONFIG_SND_HDA_DSP_LOADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * DSP loading code (e.g. for CA0132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* use the first stream for loading DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static struct azx_dev *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) azx_get_dsp_loader_dev(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct hdac_stream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) list_for_each_entry(s, &bus->stream_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (s->index == chip->playback_index_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return stream_to_azx_dev(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) unsigned int byte_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct snd_dma_buffer *bufp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct hdac_bus *bus = &codec->bus->core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct azx *chip = bus_to_azx(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct azx_dev *azx_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct hdac_stream *hstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) bool saved = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) azx_dev = azx_get_dsp_loader_dev(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) hstr = azx_stream(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) spin_lock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (hstr->opened) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) chip->saved_azx_dev = *azx_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) saved = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) spin_unlock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) spin_lock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (saved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) *azx_dev = chip->saved_azx_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) spin_unlock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) hstr->prepared = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct hdac_bus *bus = &codec->bus->core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct azx *chip = bus_to_azx(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct snd_dma_buffer *dmab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct hdac_bus *bus = &codec->bus->core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct azx *chip = bus_to_azx(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct hdac_stream *hstr = azx_stream(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (!dmab->area || !hstr->locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) snd_hdac_dsp_cleanup(hstr, dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) spin_lock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (hstr->opened)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) *azx_dev = chip->saved_azx_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) hstr->locked = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) spin_unlock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #endif /* CONFIG_SND_HDA_DSP_LOADER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * reset and start the controller registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) void azx_init_chip(struct azx *chip, bool full_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* correct RINTCNT for CXT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) azx_writew(chip, RINTCNT, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) EXPORT_SYMBOL_GPL(azx_init_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) void azx_stop_all_streams(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct hdac_stream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) list_for_each_entry(s, &bus->stream_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) snd_hdac_stream_stop(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) EXPORT_SYMBOL_GPL(azx_stop_all_streams);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) void azx_stop_chip(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) snd_hdac_bus_stop_chip(azx_bus(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) EXPORT_SYMBOL_GPL(azx_stop_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct azx *chip = bus_to_azx(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct azx_dev *azx_dev = stream_to_azx_dev(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* check whether this IRQ is really acceptable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (!chip->ops->position_check ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) chip->ops->position_check(chip, azx_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) spin_unlock(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) spin_lock(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) irqreturn_t azx_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct azx *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) bool active, handled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) int repeat = 0; /* count for avoiding endless loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (azx_has_pm_runtime(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (!pm_runtime_active(chip->card->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) spin_lock(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (chip->disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) status = azx_readl(chip, INTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (status == 0 || status == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) status = azx_readb(chip, RIRBSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (status & RIRB_INT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * Clearing the interrupt status here ensures that no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * interrupt gets masked after the RIRB wp is read in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * snd_hdac_bus_update_rirb. This avoids a possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * race condition where codec response in RIRB may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * remain unserviced by IRQ, eventually falling back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * to polling mode in azx_rirb_get_response.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (status & RIRB_INT_RESPONSE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) udelay(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) snd_hdac_bus_update_rirb(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) } while (active && ++repeat < 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) spin_unlock(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) EXPORT_SYMBOL_GPL(azx_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * Codec initerface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * Probe the given codec address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static int probe_codec(struct azx *chip, int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) unsigned int res = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) mutex_lock(&bus->cmd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) chip->probing = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) azx_send_cmd(bus, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) err = azx_get_response(bus, addr, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) chip->probing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) mutex_unlock(&bus->cmd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (err < 0 || res == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) void snd_hda_bus_reset(struct hda_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct azx *chip = bus_to_azx(&bus->core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) bus->in_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) azx_stop_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) azx_init_chip(chip, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (bus->core.chip_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) snd_hda_bus_reset_codecs(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) bus->in_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* HD-audio bus initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) int azx_bus_init(struct azx *chip, const char *model)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct hda_bus *bus = &chip->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) bus->card = chip->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) mutex_init(&bus->prepare_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) bus->pci = chip->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) bus->modelname = model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) bus->mixer_assigned = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) bus->core.snoop = azx_snoop(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (chip->get_position[0] != azx_get_pos_lpib ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) chip->get_position[1] != azx_get_pos_lpib)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) bus->core.use_posbuf = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) bus->core.bdl_pos_adj = chip->bdl_pos_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) bus->core.corbrp_self_clear = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) bus->core.align_bdle_4k = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* enable sync_write flag for stable communication as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) bus->core.sync_write = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) EXPORT_SYMBOL_GPL(azx_bus_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* Probe codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) int c, codecs, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) codecs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (!max_slots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) max_slots = AZX_DEFAULT_CODECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /* First try to probe all given codec slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) for (c = 0; c < max_slots; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (probe_codec(chip, c) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* Some BIOSen give you wrong codec addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * that don't exist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dev_warn(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) "Codec #%d probe error; disabling it...\n", c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) bus->codec_mask &= ~(1 << c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* More badly, accessing to a non-existing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * codec often screws up the controller chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * and disturbs the further communications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * Thus if an error occurs during probing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * better to reset the controller chip to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * get back to the sanity state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) azx_stop_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) azx_init_chip(chip, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* Then create codec instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) for (c = 0; c < max_slots; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct hda_codec *codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) codec->jackpoll_interval = chip->jackpoll_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) codec->beep_mode = chip->beep_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) codecs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (!codecs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) dev_err(chip->card->dev, "no codecs initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) EXPORT_SYMBOL_GPL(azx_probe_codecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /* configure each codec instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) int azx_codec_configure(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) struct hda_codec *codec, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) int success = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) list_for_each_codec(codec, &chip->bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (!snd_hda_codec_configure(codec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) success++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (success) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /* unregister failed codecs if any codec has been probed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) list_for_each_codec_safe(codec, next, &chip->bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (!codec->configured) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) codec_err(codec, "Unable to configure, disabling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) snd_hdac_device_unregister(&codec->core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return success ? 0 : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) EXPORT_SYMBOL_GPL(azx_codec_configure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static int stream_direction(struct azx *chip, unsigned char index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (index >= chip->capture_index_offset &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) index < chip->capture_index_offset + chip->capture_streams)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) return SNDRV_PCM_STREAM_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /* initialize SD streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) int azx_init_streams(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) int stream_tags[2] = { 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /* initialize each stream (aka device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * assign the starting bdl address to each stream (device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * and initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) for (i = 0; i < chip->num_streams; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) int dir, tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (!azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) dir = stream_direction(chip, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* stream tag must be unique throughout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * the stream direction group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * valid values 1...15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * use separate stream tag if the flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * AZX_DCAPS_SEPARATE_STREAM_TAG is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) tag = ++stream_tags[dir];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) tag = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) i, dir, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) EXPORT_SYMBOL_GPL(azx_init_streams);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) void azx_free_streams(struct azx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) struct hdac_bus *bus = azx_bus(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) struct hdac_stream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) while (!list_empty(&bus->stream_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) list_del(&s->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) kfree(stream_to_azx_dev(s));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) EXPORT_SYMBOL_GPL(azx_free_streams);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags