^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * HD audio interface patch for Creative CA0132 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * CA0132 registers defines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2011, Creative Technology Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __CA0132_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __CA0132_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DSP_CHIP_OFFSET 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DSP_DBGCNTL_MODULE_OFFSET 0xE30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DSP_DBGCNTL_INST_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) (DSP_CHIP_OFFSET + DSP_DBGCNTL_MODULE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DSP_DBGCNTL_EXEC_LOBIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DSP_DBGCNTL_EXEC_HIBIT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DSP_DBGCNTL_EXEC_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DSP_DBGCNTL_SS_LOBIT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DSP_DBGCNTL_SS_HIBIT 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DSP_DBGCNTL_SS_MASK 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DSP_DBGCNTL_STATE_LOBIT 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DSP_DBGCNTL_STATE_HIBIT 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DSP_DBGCNTL_STATE_MASK 0x3C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XRAM_CHIP_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XRAM_XRAM_CHANNEL_COUNT 0xE000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define XRAM_XRAM_MODULE_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define XRAM_XRAM_CHAN_INCR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XRAM_XRAM_INST_OFFSET(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) (XRAM_CHIP_OFFSET + XRAM_XRAM_MODULE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) (_chan * XRAM_XRAM_CHAN_INCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define YRAM_CHIP_OFFSET 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define YRAM_YRAM_CHANNEL_COUNT 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define YRAM_YRAM_MODULE_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define YRAM_YRAM_CHAN_INCR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define YRAM_YRAM_INST_OFFSET(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) (YRAM_CHIP_OFFSET + YRAM_YRAM_MODULE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) (_chan * YRAM_YRAM_CHAN_INCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UC_CHIP_OFFSET 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define UC_UC_CHANNEL_COUNT 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UC_UC_MODULE_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define UC_UC_CHAN_INCR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UC_UC_INST_OFFSET(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) (UC_CHIP_OFFSET + UC_UC_MODULE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) (_chan * UC_UC_CHAN_INCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AXRAM_CHIP_OFFSET 0x3C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AXRAM_AXRAM_CHANNEL_COUNT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AXRAM_AXRAM_MODULE_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AXRAM_AXRAM_CHAN_INCR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AXRAM_AXRAM_INST_OFFSET(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) (AXRAM_CHIP_OFFSET + AXRAM_AXRAM_MODULE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) (_chan * AXRAM_AXRAM_CHAN_INCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AYRAM_CHIP_OFFSET 0x78000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AYRAM_AYRAM_CHANNEL_COUNT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AYRAM_AYRAM_MODULE_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AYRAM_AYRAM_CHAN_INCR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AYRAM_AYRAM_INST_OFFSET(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) (AYRAM_CHIP_OFFSET + AYRAM_AYRAM_MODULE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) (_chan * AYRAM_AYRAM_CHAN_INCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DSPDMAC_CHIP_OFFSET 0x110000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DSPDMAC_DMA_CFG_CHANNEL_COUNT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DSPDMAC_DMACFG_MODULE_OFFSET 0xF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DSPDMAC_DMACFG_CHAN_INCR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DSPDMAC_DMACFG_INST_OFFSET(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (DSPDMAC_CHIP_OFFSET + DSPDMAC_DMACFG_MODULE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) (_chan * DSPDMAC_DMACFG_CHAN_INCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DSPDMAC_DMACFG_DBADR_LOBIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DSPDMAC_DMACFG_DBADR_HIBIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DSPDMAC_DMACFG_DBADR_MASK 0x1FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DSPDMAC_DMACFG_LP_LOBIT 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DSPDMAC_DMACFG_LP_HIBIT 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DSPDMAC_DMACFG_LP_MASK 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DSPDMAC_DMACFG_AINCR_LOBIT 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DSPDMAC_DMACFG_AINCR_HIBIT 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DSPDMAC_DMACFG_AINCR_MASK 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DSPDMAC_DMACFG_DWR_LOBIT 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DSPDMAC_DMACFG_DWR_HIBIT 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DSPDMAC_DMACFG_DWR_MASK 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DSPDMAC_DMACFG_AJUMP_LOBIT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DSPDMAC_DMACFG_AJUMP_HIBIT 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DSPDMAC_DMACFG_AJUMP_MASK 0xF00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DSPDMAC_DMACFG_AMODE_LOBIT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DSPDMAC_DMACFG_AMODE_HIBIT 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DSPDMAC_DMACFG_AMODE_MASK 0x3000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DSPDMAC_DMACFG_LK_LOBIT 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DSPDMAC_DMACFG_LK_HIBIT 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DSPDMAC_DMACFG_LK_MASK 0x4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DSPDMAC_DMACFG_AICS_LOBIT 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DSPDMAC_DMACFG_AICS_HIBIT 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DSPDMAC_DMACFG_AICS_MASK 0xF8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DSPDMAC_DMACFG_LP_SINGLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DSPDMAC_DMACFG_LP_LOOPING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DSPDMAC_DMACFG_AINCR_XANDY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DSPDMAC_DMACFG_AINCR_XORY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DSPDMAC_DMACFG_DWR_DMA_RD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DSPDMAC_DMACFG_DWR_DMA_WR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DSPDMAC_DMACFG_AMODE_LINEAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DSPDMAC_DMACFG_AMODE_RSV1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DSPDMAC_DMACFG_AMODE_WINTLV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DSPDMAC_DMACFG_AMODE_GINTLV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DSPDMAC_DSP_ADR_OFS_CHANNEL_COUNT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DSPDMAC_DSPADROFS_MODULE_OFFSET 0xF04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DSPDMAC_DSPADROFS_CHAN_INCR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DSPDMAC_DSPADROFS_INST_OFFSET(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) (DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADROFS_MODULE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) (_chan * DSPDMAC_DSPADROFS_CHAN_INCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DSPDMAC_DSPADROFS_COFS_LOBIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DSPDMAC_DSPADROFS_COFS_HIBIT 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DSPDMAC_DSPADROFS_COFS_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DSPDMAC_DSPADROFS_BOFS_LOBIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DSPDMAC_DSPADROFS_BOFS_HIBIT 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DSPDMAC_DSPADROFS_BOFS_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DSPDMAC_DSP_ADR_WOFS_CHANNEL_COUNT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DSPDMAC_DSPADRWOFS_MODULE_OFFSET 0xF04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DSPDMAC_DSPADRWOFS_CHAN_INCR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DSPDMAC_DSPADRWOFS_INST_OFFSET(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADRWOFS_MODULE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) (_chan * DSPDMAC_DSPADRWOFS_CHAN_INCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DSPDMAC_DSPADRWOFS_WCOFS_LOBIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DSPDMAC_DSPADRWOFS_WCOFS_HIBIT 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DSPDMAC_DSPADRWOFS_WCOFS_MASK 0x7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DSPDMAC_DSPADRWOFS_WCBFR_LOBIT 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DSPDMAC_DSPADRWOFS_WCBFR_HIBIT 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DSPDMAC_DSPADRWOFS_WCBFR_MASK 0xF800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DSPDMAC_DSPADRWOFS_WBOFS_LOBIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DSPDMAC_DSPADRWOFS_WBOFS_HIBIT 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DSPDMAC_DSPADRWOFS_WBOFS_MASK 0x7FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DSPDMAC_DSPADRWOFS_WBBFR_LOBIT 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DSPDMAC_DSPADRWOFS_WBBFR_HIBIT 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DSPDMAC_DSPADRWOFS_WBBFR_MASK 0xF8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DSPDMAC_DSP_ADR_GOFS_CHANNEL_COUNT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DSPDMAC_DSPADRGOFS_MODULE_OFFSET 0xF04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DSPDMAC_DSPADRGOFS_CHAN_INCR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DSPDMAC_DSPADRGOFS_INST_OFFSET(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) (DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADRGOFS_MODULE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) (_chan * DSPDMAC_DSPADRGOFS_CHAN_INCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DSPDMAC_DSPADRGOFS_GCOFS_LOBIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DSPDMAC_DSPADRGOFS_GCOFS_HIBIT 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DSPDMAC_DSPADRGOFS_GCOFS_MASK 0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DSPDMAC_DSPADRGOFS_GCS_LOBIT 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DSPDMAC_DSPADRGOFS_GCS_HIBIT 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DSPDMAC_DSPADRGOFS_GCS_MASK 0x1C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DSPDMAC_DSPADRGOFS_GCBFR_LOBIT 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DSPDMAC_DSPADRGOFS_GCBFR_HIBIT 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DSPDMAC_DSPADRGOFS_GCBFR_MASK 0xE000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DSPDMAC_DSPADRGOFS_GBOFS_LOBIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DSPDMAC_DSPADRGOFS_GBOFS_HIBIT 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DSPDMAC_DSPADRGOFS_GBOFS_MASK 0x3FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DSPDMAC_DSPADRGOFS_GBS_LOBIT 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DSPDMAC_DSPADRGOFS_GBS_HIBIT 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DSPDMAC_DSPADRGOFS_GBS_MASK 0x1C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DSPDMAC_DSPADRGOFS_GBBFR_LOBIT 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DSPDMAC_DSPADRGOFS_GBBFR_HIBIT 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DSPDMAC_DSPADRGOFS_GBBFR_MASK 0xE0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DSPDMAC_XFR_CNT_CHANNEL_COUNT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DSPDMAC_XFRCNT_MODULE_OFFSET 0xF08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DSPDMAC_XFRCNT_CHAN_INCR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DSPDMAC_XFRCNT_INST_OFFSET(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) (DSPDMAC_CHIP_OFFSET + DSPDMAC_XFRCNT_MODULE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) (_chan * DSPDMAC_XFRCNT_CHAN_INCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DSPDMAC_XFRCNT_CCNT_LOBIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DSPDMAC_XFRCNT_CCNT_HIBIT 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DSPDMAC_XFRCNT_CCNT_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define DSPDMAC_XFRCNT_BCNT_LOBIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DSPDMAC_XFRCNT_BCNT_HIBIT 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DSPDMAC_XFRCNT_BCNT_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DSPDMAC_IRQ_CNT_CHANNEL_COUNT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DSPDMAC_IRQCNT_MODULE_OFFSET 0xF0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define DSPDMAC_IRQCNT_CHAN_INCR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define DSPDMAC_IRQCNT_INST_OFFSET(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) (DSPDMAC_CHIP_OFFSET + DSPDMAC_IRQCNT_MODULE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) (_chan * DSPDMAC_IRQCNT_CHAN_INCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DSPDMAC_IRQCNT_CICNT_LOBIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define DSPDMAC_IRQCNT_CICNT_HIBIT 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DSPDMAC_IRQCNT_CICNT_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DSPDMAC_IRQCNT_BICNT_LOBIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DSPDMAC_IRQCNT_BICNT_HIBIT 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DSPDMAC_IRQCNT_BICNT_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DSPDMAC_AUD_CHSEL_CHANNEL_COUNT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DSPDMAC_AUDCHSEL_MODULE_OFFSET 0xFC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DSPDMAC_AUDCHSEL_CHAN_INCR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DSPDMAC_AUDCHSEL_INST_OFFSET(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) (DSPDMAC_CHIP_OFFSET + DSPDMAC_AUDCHSEL_MODULE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) (_chan * DSPDMAC_AUDCHSEL_CHAN_INCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define DSPDMAC_AUDCHSEL_ACS_LOBIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DSPDMAC_AUDCHSEL_ACS_HIBIT 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define DSPDMAC_AUDCHSEL_ACS_MASK 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define DSPDMAC_CHNLSTART_MODULE_OFFSET 0xFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DSPDMAC_CHNLSTART_INST_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) (DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLSTART_MODULE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define DSPDMAC_CHNLSTART_EN_LOBIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DSPDMAC_CHNLSTART_EN_HIBIT 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DSPDMAC_CHNLSTART_EN_MASK 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DSPDMAC_CHNLSTART_VAI1_LOBIT 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DSPDMAC_CHNLSTART_VAI1_HIBIT 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define DSPDMAC_CHNLSTART_VAI1_MASK 0xF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DSPDMAC_CHNLSTART_DIS_LOBIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define DSPDMAC_CHNLSTART_DIS_HIBIT 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define DSPDMAC_CHNLSTART_DIS_MASK 0xFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define DSPDMAC_CHNLSTART_VAI2_LOBIT 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DSPDMAC_CHNLSTART_VAI2_HIBIT 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define DSPDMAC_CHNLSTART_VAI2_MASK 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define DSPDMAC_CHNLSTATUS_MODULE_OFFSET 0xFF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DSPDMAC_CHNLSTATUS_INST_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) (DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLSTATUS_MODULE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DSPDMAC_CHNLSTATUS_ISC_LOBIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define DSPDMAC_CHNLSTATUS_ISC_HIBIT 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DSPDMAC_CHNLSTATUS_ISC_MASK 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DSPDMAC_CHNLSTATUS_AOO_LOBIT 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DSPDMAC_CHNLSTATUS_AOO_HIBIT 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DSPDMAC_CHNLSTATUS_AOO_MASK 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define DSPDMAC_CHNLSTATUS_AOU_LOBIT 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DSPDMAC_CHNLSTATUS_AOU_HIBIT 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DSPDMAC_CHNLSTATUS_AOU_MASK 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define DSPDMAC_CHNLSTATUS_AIO_LOBIT 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DSPDMAC_CHNLSTATUS_AIO_HIBIT 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DSPDMAC_CHNLSTATUS_AIO_MASK 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DSPDMAC_CHNLSTATUS_AIU_LOBIT 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DSPDMAC_CHNLSTATUS_AIU_HIBIT 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DSPDMAC_CHNLSTATUS_AIU_MASK 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DSPDMAC_CHNLSTATUS_IEN_LOBIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DSPDMAC_CHNLSTATUS_IEN_HIBIT 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define DSPDMAC_CHNLSTATUS_IEN_MASK 0xFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DSPDMAC_CHNLSTATUS_VAI0_LOBIT 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define DSPDMAC_CHNLSTATUS_VAI0_HIBIT 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define DSPDMAC_CHNLSTATUS_VAI0_MASK 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DSPDMAC_CHNLPROP_MODULE_OFFSET 0xFF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define DSPDMAC_CHNLPROP_INST_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) (DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLPROP_MODULE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DSPDMAC_CHNLPROP_DCON_LOBIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define DSPDMAC_CHNLPROP_DCON_HIBIT 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define DSPDMAC_CHNLPROP_DCON_MASK 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define DSPDMAC_CHNLPROP_FFS_LOBIT 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define DSPDMAC_CHNLPROP_FFS_HIBIT 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DSPDMAC_CHNLPROP_FFS_MASK 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DSPDMAC_CHNLPROP_NAJ_LOBIT 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DSPDMAC_CHNLPROP_NAJ_HIBIT 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DSPDMAC_CHNLPROP_NAJ_MASK 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DSPDMAC_CHNLPROP_ENH_LOBIT 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DSPDMAC_CHNLPROP_ENH_HIBIT 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DSPDMAC_CHNLPROP_ENH_MASK 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DSPDMAC_CHNLPROP_MSPCE_LOBIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DSPDMAC_CHNLPROP_MSPCE_HIBIT 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DSPDMAC_CHNLPROP_MSPCE_MASK 0xFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DSPDMAC_CHNLPROP_AC_LOBIT 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DSPDMAC_CHNLPROP_AC_HIBIT 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define DSPDMAC_CHNLPROP_AC_MASK 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define DSPDMAC_ACTIVE_MODULE_OFFSET 0xFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define DSPDMAC_ACTIVE_INST_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) (DSPDMAC_CHIP_OFFSET + DSPDMAC_ACTIVE_MODULE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define DSPDMAC_ACTIVE_AAR_LOBIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define DSPDMAC_ACTIVE_AAR_HIBIT 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define DSPDMAC_ACTIVE_AAR_MASK 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define DSPDMAC_ACTIVE_WFR_LOBIT 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define DSPDMAC_ACTIVE_WFR_HIBIT 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DSPDMAC_ACTIVE_WFR_MASK 0xFFF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define DSP_AUX_MEM_BASE 0xE000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define INVALID_CHIP_ADDRESS (~0U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define X_SIZE (XRAM_XRAM_CHANNEL_COUNT * XRAM_XRAM_CHAN_INCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define Y_SIZE (YRAM_YRAM_CHANNEL_COUNT * YRAM_YRAM_CHAN_INCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define AX_SIZE (AXRAM_AXRAM_CHANNEL_COUNT * AXRAM_AXRAM_CHAN_INCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define AY_SIZE (AYRAM_AYRAM_CHANNEL_COUNT * AYRAM_AYRAM_CHAN_INCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define UC_SIZE (UC_UC_CHANNEL_COUNT * UC_UC_CHAN_INCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define XEXT_SIZE (X_SIZE + AX_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define YEXT_SIZE (Y_SIZE + AY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define U64K 0x10000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define X_END (XRAM_CHIP_OFFSET + X_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define X_EXT (XRAM_CHIP_OFFSET + XEXT_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define AX_END (XRAM_CHIP_OFFSET + U64K*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define Y_END (YRAM_CHIP_OFFSET + Y_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define Y_EXT (YRAM_CHIP_OFFSET + YEXT_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define AY_END (YRAM_CHIP_OFFSET + U64K*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define UC_END (UC_CHIP_OFFSET + UC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define X_RANGE_MAIN(a, s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) (((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < X_END))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define X_RANGE_AUX(a, s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) (((a) >= X_END) && ((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < AX_END))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define X_RANGE_EXT(a, s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) (((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < X_EXT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define X_RANGE_ALL(a, s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) (((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < AX_END))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define Y_RANGE_MAIN(a, s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) (((a) >= YRAM_CHIP_OFFSET) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < Y_END))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define Y_RANGE_AUX(a, s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) (((a) >= Y_END) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < AY_END))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define Y_RANGE_EXT(a, s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) (((a) >= YRAM_CHIP_OFFSET) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < Y_EXT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define Y_RANGE_ALL(a, s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) (((a) >= YRAM_CHIP_OFFSET) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < AY_END))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define UC_RANGE(a, s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) (((a) >= UC_CHIP_OFFSET) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ((a)+((s)-1)*UC_UC_CHAN_INCR < UC_END))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define X_OFF(a) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) (((a) - XRAM_CHIP_OFFSET) / XRAM_XRAM_CHAN_INCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define AX_OFF(a) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) (((a) % (AXRAM_AXRAM_CHANNEL_COUNT * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) AXRAM_AXRAM_CHAN_INCR)) / AXRAM_AXRAM_CHAN_INCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define Y_OFF(a) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) (((a) - YRAM_CHIP_OFFSET) / YRAM_YRAM_CHAN_INCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define AY_OFF(a) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) (((a) % (AYRAM_AYRAM_CHANNEL_COUNT * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) AYRAM_AYRAM_CHAN_INCR)) / AYRAM_AYRAM_CHAN_INCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define UC_OFF(a) (((a) - UC_CHIP_OFFSET) / UC_UC_CHAN_INCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define X_EXT_MAIN_SIZE(a) (XRAM_XRAM_CHANNEL_COUNT - X_OFF(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define X_EXT_AUX_SIZE(a, s) ((s) - X_EXT_MAIN_SIZE(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define Y_EXT_MAIN_SIZE(a) (YRAM_YRAM_CHANNEL_COUNT - Y_OFF(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define Y_EXT_AUX_SIZE(a, s) ((s) - Y_EXT_MAIN_SIZE(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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