^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Thomas Sailer <sailer@ife.ee.ethz.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* Power-Management-Code ( CONFIG_PM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * for ens1371 only ( FIXME )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * derived from cs4281.c, atiixp.c and via82xx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * using http://www.alsa-project.org/~tiwai/writing-an-alsa-driver/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * by Kurt J. Bosch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gameport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/rawmidi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <sound/ak4531_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifndef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #undef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRIVER_NAME "ENS1370"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DRIVER_NAME "ENS1371"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CHIP_NAME "ES1371"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "{Creative Labs,SB PCI64/128 (ES1370)}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "{Ensoniq,AudioPCI ES1373},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "{Creative Labs,Ectiva EV1938},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "{Creative Labs,SB PCI64/128 (ES1371/73)},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "{Creative Labs,Vibra PCI128},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "{Ectiva,EV1938}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #if IS_REACHABLE(CONFIG_GAMEPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int joystick_port[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static bool joystick[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int spdif[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int lineio[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MODULE_PARM_DESC(joystick_port, "Joystick port address.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) module_param_array(joystick, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MODULE_PARM_DESC(joystick, "Enable joystick.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif /* SUPPORT_JOYSTICK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) module_param_array(spdif, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) module_param_array(lineio, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* ES1371 chip ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* This is a little confusing because all ES1371 compatible chips have the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) same DEVICE_ID, the only thing differentiating them is the REV_ID field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) This is only significant if you want to enable features on the later parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) Yes, I know it's stupid and why didn't we use the sub IDs?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ES1371REV_ES1373_A 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ES1371REV_ES1373_B 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ES1371REV_CT5880_A 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CT5880REV_CT5880_C 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CT5880REV_CT5880_D 0x03 /* ??? -jk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CT5880REV_CT5880_E 0x04 /* mw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ES1371REV_ES1371_B 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define EV1938REV_EV1938_A 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ES1371REV_ES1373_8 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Direct registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ES_1371_PDLEVM (0x03<<8) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ES_BREQ (1<<7) /* memory bus request enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ES_ADC_EN (1<<4) /* ADC capture channel enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ES_UART_EN (1<<3) /* UART enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ES_JYSTK_EN (1<<2) /* Joystick module enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ES_INTR (1<<31) /* Interrupt is pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ES_1373_REAR_BIT26 (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ES_1373_REAR_BIT24 (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ES_1371_TEST (1<<16) /* test ASIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ES_1370_CBUSY (1<<9) /* CODEC is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ES_1371_MPWR (1<<5) /* power level interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ES_MCCB (1<<4) /* CCB interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ES_UART (1<<3) /* UART interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ES_ADC (1<<0) /* ADC channel interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ES_RXINT (1<<7) /* RX interrupt occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ES_TXINT (1<<2) /* TX interrupt occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ES_TXRDY (1<<1) /* transmitter ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ES_RXRDY (1<<0) /* receiver ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ES_RXINTEN (1<<7) /* RX interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ES_TXINTENM (0x03<<5) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ES_TXINTENI(i) (((i)>>5)&0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ES_CNTRLM (0x03<<0) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ES_TEST_MODE (1<<0) /* test mode enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ES_1371_CODEC_RDY (1<<31) /* codec ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define EV_1938_CODEC_MAGIC (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define ES_1371_JFAST (1<<31) /* fast joystick timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ES_1371_VMPUM (0x03<<27) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ES_1371_VCDCM (0x03<<25) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ES_1371_FIRQ (1<<24) /* force an interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ES_P2_END_INCM (0x07<<19) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ES_P2_ST_INCM (0x07<<16) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ES_R1_MODEM (0x03<<4) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ES_R1_MODEI(i) (((i)>>4)&0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ES_P2_MODEM (0x03<<2) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ES_P2_MODEI(i) (((i)>>2)&0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ES_P1_MODEM (0x03<<0) /* mask for above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ES_P1_MODEI(i) (((i)>>0)&0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define ES_REG_COUNTM (0xffff<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define ES_REG_FCURR_COUNTM (0xffff<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define ES_REG_FSIZEM (0xffff<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define ES_REG_UF_VALID (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define ES_REG_UF_BYTEM (0xff<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define ES_PAGE_DAC 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define ES_PAGE_ADC 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define ES_PAGE_UART 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define ES_PAGE_UART1 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Sample rate converter addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define ES_SMPREG_DAC1 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define ES_SMPREG_DAC2 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define ES_SMPREG_ADC 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define ES_SMPREG_VOL_ADC 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define ES_SMPREG_VOL_DAC1 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define ES_SMPREG_VOL_DAC2 0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define ES_SMPREG_TRUNC_N 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define ES_SMPREG_INT_REGS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define ES_SMPREG_ACCUM_FRAC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define ES_SMPREG_VFREQ_FRAC 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Some contants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define ES_1370_SRCLOCK 1411200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * Open modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define ES_MODE_PLAY1 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define ES_MODE_PLAY2 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define ES_MODE_CAPTURE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define ES_MODE_OUTPUT 0x0001 /* for MIDI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define ES_MODE_INPUT 0x0002 /* for MIDI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct ensoniq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct mutex src_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned long playback1size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned long playback2size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned long capture3size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int uartm; /* UART mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned int ctrl; /* control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned int sctrl; /* serial control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned int cssr; /* control status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int uartc; /* uart control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int rev; /* chip revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct snd_ac97 *ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) } es1371;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int pclkdiv_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct snd_ak4531 *ak4531;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) } es1370;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct snd_pcm *pcm1; /* DAC1/ADC PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct snd_pcm *pcm2; /* DAC2 PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct snd_pcm_substream *playback1_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct snd_pcm_substream *playback2_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct snd_pcm_substream *capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned int p1_dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int p2_dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned int c_dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned int p1_period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned int p2_period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned int c_period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct snd_rawmidi_substream *midi_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct snd_rawmidi_substream *midi_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int spdif_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int spdif_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct snd_dma_buffer dma_bug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct gameport *gameport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct pci_device_id snd_audiopci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { PCI_VDEVICE(ENSONIQ, 0x5000), 0, }, /* ES1370 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) { PCI_VDEVICE(ENSONIQ, 0x1371), 0, }, /* ES1371 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) { PCI_VDEVICE(ENSONIQ, 0x5880), 0, }, /* ES1373 - CT5880 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) { PCI_VDEVICE(ECTIVA, 0x8938), 0, }, /* Ectiva EV1938 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define POLL_COUNT 0xa000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static const unsigned int snd_es1370_fixed_rates[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {5512, 11025, 22050, 44100};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .count = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .list = snd_es1370_fixed_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct snd_ratnum es1370_clock = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .num = ES_1370_SRCLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .den_min = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .den_max = 353,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .den_step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .nrats = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .rats = &es1370_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const struct snd_ratden es1371_dac_clock = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .num_min = 3000 * (1 << 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .num_max = 48000 * (1 << 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .num_step = 3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .den = 1 << 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .nrats = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .rats = &es1371_dac_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const struct snd_ratnum es1371_adc_clock = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .num = 48000 << 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .den_min = 32768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .den_max = 393216,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .den_step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .nrats = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .rats = &es1371_adc_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const unsigned int snd_ensoniq_sample_shift[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0, 1, 1, 2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * common I/O routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned int t, r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) for (t = 0; t < POLL_COUNT; t++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) r = inl(ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if ((r & ES_1371_SRC_RAM_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_err(ensoniq->card->dev, "wait src ready timeout 0x%lx [0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ES_REG(ensoniq, 1371_SMPRATE), r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned int temp, i, orig, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* wait for ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) temp = orig = snd_es1371_wait_src_ready(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* expose the SRC state bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ES_1371_DIS_P2 | ES_1371_DIS_R1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) outl(r, ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* now, wait for busy and the correct time to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) temp = snd_es1371_wait_src_ready(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if ((temp & 0x00870000) != 0x00010000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* wait for the right state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) for (i = 0; i < POLL_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if ((temp & 0x00870000) == 0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* hide the state bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ES_1371_DIS_P2 | ES_1371_DIS_R1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) r |= ES_1371_SRC_RAM_ADDRO(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) outl(r, ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static void snd_es1371_src_write(struct ensoniq * ensoniq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned short reg, unsigned short data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) r = snd_es1371_wait_src_ready(ensoniq) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ES_1371_DIS_P2 | ES_1371_DIS_R1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #endif /* CHIP1371 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned short reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct ensoniq *ensoniq = ak4531->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned long end_time = jiffies + HZ / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev_dbg(ensoniq->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) } while (time_after(end_time, jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev_err(ensoniq->card->dev, "codec write timeout, status = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) inl(ES_REG(ensoniq, STATUS)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #endif /* CHIP1370 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static inline bool is_ev1938(struct ensoniq *ensoniq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return ensoniq->pci->device == 0x8938;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static void snd_es1371_codec_write(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned short reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct ensoniq *ensoniq = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned int t, x, flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) mutex_lock(&ensoniq->src_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) for (t = 0; t < POLL_COUNT; t++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* save the current state for latter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) x = snd_es1371_wait_src_ready(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* wait for not busy (state 0) first to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) transition states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) for (t = 0; t < POLL_COUNT; t++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* wait for a SAFE time to write addr/data and then do it, dammit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) for (t = 0; t < POLL_COUNT; t++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) outl(ES_1371_CODEC_WRITE(reg, val) | flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ES_REG(ensoniq, 1371_CODEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* restore SRC reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) snd_es1371_wait_src_ready(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) outl(x, ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) mutex_unlock(&ensoniq->src_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) mutex_unlock(&ensoniq->src_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dev_err(ensoniq->card->dev, "codec write timeout at 0x%lx [0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct ensoniq *ensoniq = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) unsigned int t, x, flag, fail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) __again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) mutex_lock(&ensoniq->src_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) for (t = 0; t < POLL_COUNT; t++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* save the current state for latter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) x = snd_es1371_wait_src_ready(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* wait for not busy (state 0) first to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) transition states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) for (t = 0; t < POLL_COUNT; t++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* wait for a SAFE time to write addr/data and then do it, dammit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) for (t = 0; t < POLL_COUNT; t++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) outl(ES_1371_CODEC_READS(reg) | flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ES_REG(ensoniq, 1371_CODEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* restore SRC reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) snd_es1371_wait_src_ready(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) outl(x, ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* wait for WIP again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) for (t = 0; t < POLL_COUNT; t++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* now wait for the stinkin' data (RDY) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) for (t = 0; t < POLL_COUNT; t++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (is_ev1938(ensoniq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) for (t = 0; t < 100; t++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) inl(ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) x = inl(ES_REG(ensoniq, 1371_CODEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) mutex_unlock(&ensoniq->src_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return ES_1371_CODEC_READ(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) mutex_unlock(&ensoniq->src_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (++fail > 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_err(ensoniq->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) "codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ES_REG(ensoniq, 1371_CODEC), reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) inl(ES_REG(ensoniq, 1371_CODEC)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) goto __again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) mutex_unlock(&ensoniq->src_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_err(ensoniq->card->dev, "codec read timeout at 0x%lx [0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) msleep(750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) snd_es1371_codec_read(ac97, AC97_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) unsigned int n, truncm, freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) mutex_lock(&ensoniq->src_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) n = rate / 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) n--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) truncm = (21 * n - 1) | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) freq = ((48000UL << 15) / rate) * n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (rate >= 24000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (truncm > 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) truncm = 239;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) (((239 - truncm) >> 1) << 9) | (n << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (truncm > 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) truncm = 119;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ES_SMPREG_INT_REGS) & 0x00ff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ((freq >> 5) & 0xfc00));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) mutex_unlock(&ensoniq->src_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) unsigned int freq, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) mutex_lock(&ensoniq->src_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) freq = ((rate << 15) + 1500) / 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ES_1371_DIS_P1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) outl(r, ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ES_SMPREG_INT_REGS) & 0x00ff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ((freq >> 5) & 0xfc00));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ES_1371_DIS_P2 | ES_1371_DIS_R1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) outl(r, ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mutex_unlock(&ensoniq->src_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) unsigned int freq, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mutex_lock(&ensoniq->src_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) freq = ((rate << 15) + 1500) / 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ES_1371_DIS_P2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) outl(r, ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ES_SMPREG_INT_REGS) & 0x00ff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ((freq >> 5) & 0xfc00));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) freq & 0x7fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ES_1371_DIS_P1 | ES_1371_DIS_R1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) outl(r, ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) mutex_unlock(&ensoniq->src_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #endif /* CHIP1371 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) unsigned int what = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct snd_pcm_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (s == ensoniq->playback1_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) what |= ES_P1_PAUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) } else if (s == ensoniq->playback2_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) what |= ES_P2_PAUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) } else if (s == ensoniq->capture_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) spin_lock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ensoniq->sctrl |= what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ensoniq->sctrl &= ~what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) spin_unlock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) unsigned int what = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct snd_pcm_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (s == ensoniq->playback1_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) what |= ES_DAC1_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) } else if (s == ensoniq->playback2_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) what |= ES_DAC2_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) } else if (s == ensoniq->capture_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) what |= ES_ADC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) spin_lock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (cmd == SNDRV_PCM_TRIGGER_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ensoniq->ctrl |= what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ensoniq->ctrl &= ~what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) spin_unlock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * PCM part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) unsigned int mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (snd_pcm_format_width(runtime->format) == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) mode |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (runtime->channels > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) mode |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ensoniq->ctrl &= ~ES_DAC1_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* 48k doesn't need SRC (it breaks AC3-passthru) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (runtime->rate == 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ensoniq->ctrl |= ES_1373_BYPASS_P1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ES_REG(ensoniq, DAC1_COUNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ensoniq->ctrl &= ~ES_1370_WTSRSELM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) switch (runtime->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) default: snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #ifndef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) snd_es1371_dac1_rate(ensoniq, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) unsigned int mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (snd_pcm_format_width(runtime->format) == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) mode |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (runtime->channels > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) mode |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ensoniq->ctrl &= ~ES_DAC2_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ES_REG(ensoniq, DAC2_COUNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #ifndef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) snd_es1371_dac2_rate(ensoniq, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) unsigned int mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (snd_pcm_format_width(runtime->format) == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) mode |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (runtime->channels > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) mode |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ensoniq->ctrl &= ~ES_ADC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ES_REG(ensoniq, ADC_COUNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #ifndef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) snd_es1371_adc_rate(ensoniq, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) spin_lock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ptr = bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) spin_unlock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) spin_lock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ptr = bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) spin_unlock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) spin_lock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ptr = bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) spin_unlock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static const struct snd_pcm_hardware snd_ensoniq_playback1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .rates =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #ifndef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) SNDRV_PCM_RATE_44100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .rate_min = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .buffer_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .period_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static const struct snd_pcm_hardware snd_ensoniq_playback2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) SNDRV_PCM_INFO_SYNC_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .rate_min = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .buffer_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .period_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static const struct snd_pcm_hardware snd_ensoniq_capture =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .rate_min = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .buffer_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .period_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ensoniq->mode |= ES_MODE_PLAY1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ensoniq->playback1_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) runtime->hw = snd_ensoniq_playback1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ensoniq->spdif_stream = ensoniq->spdif_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) &snd_es1370_hw_constraints_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) &snd_es1371_hw_constraints_dac_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ensoniq->mode |= ES_MODE_PLAY2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ensoniq->playback2_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) runtime->hw = snd_ensoniq_playback2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ensoniq->spdif_stream = ensoniq->spdif_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) &snd_es1370_hw_constraints_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) &snd_es1371_hw_constraints_dac_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ensoniq->mode |= ES_MODE_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ensoniq->capture_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) runtime->hw = snd_ensoniq_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) &snd_es1370_hw_constraints_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) &snd_es1371_hw_constraints_adc_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) ensoniq->playback1_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ensoniq->mode &= ~ES_MODE_PLAY1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ensoniq->playback2_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ensoniq->mode &= ~ES_MODE_PLAY2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ensoniq->capture_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ensoniq->mode &= ~ES_MODE_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static const struct snd_pcm_ops snd_ensoniq_playback1_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .open = snd_ensoniq_playback1_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .close = snd_ensoniq_playback1_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .prepare = snd_ensoniq_playback1_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .trigger = snd_ensoniq_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .pointer = snd_ensoniq_playback1_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static const struct snd_pcm_ops snd_ensoniq_playback2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .open = snd_ensoniq_playback2_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .close = snd_ensoniq_playback2_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .prepare = snd_ensoniq_playback2_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .trigger = snd_ensoniq_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .pointer = snd_ensoniq_playback2_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static const struct snd_pcm_ops snd_ensoniq_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .open = snd_ensoniq_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .close = snd_ensoniq_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .prepare = snd_ensoniq_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .trigger = snd_ensoniq_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .pointer = snd_ensoniq_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static const struct snd_pcm_chmap_elem surround_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) { .channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .map = { SNDRV_CHMAP_MONO } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) { .channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static int snd_ensoniq_pcm(struct ensoniq *ensoniq, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) err = snd_pcm_new(ensoniq->card, CHIP_NAME "/1", device, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) pcm->private_data = ensoniq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) strcpy(pcm->name, CHIP_NAME " DAC2/ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ensoniq->pcm1 = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) &ensoniq->pci->dev, 64*1024, 128*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) surround_map, 2, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) snd_pcm_std_chmaps, 2, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static int snd_ensoniq_pcm2(struct ensoniq *ensoniq, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) err = snd_pcm_new(ensoniq->card, CHIP_NAME "/2", device, 1, 0, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) pcm->private_data = ensoniq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) strcpy(pcm->name, CHIP_NAME " DAC1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ensoniq->pcm2 = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) &ensoniq->pci->dev, 64*1024, 128*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) snd_pcm_std_chmaps, 2, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) surround_map, 2, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) * Mixer section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * ENS1371 mixer (including SPDIF interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) val = ((u32)ucontrol->value.iec958.status[0] << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ((u32)ucontrol->value.iec958.status[1] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ((u32)ucontrol->value.iec958.status[2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ((u32)ucontrol->value.iec958.status[3] << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) change = ensoniq->spdif_default != val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) ensoniq->spdif_default = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (change && ensoniq->playback1_substream == NULL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ensoniq->playback2_substream == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) ucontrol->value.iec958.status[0] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) ucontrol->value.iec958.status[1] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) ucontrol->value.iec958.status[2] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) ucontrol->value.iec958.status[3] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) val = ((u32)ucontrol->value.iec958.status[0] << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) ((u32)ucontrol->value.iec958.status[1] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) ((u32)ucontrol->value.iec958.status[2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ((u32)ucontrol->value.iec958.status[3] << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) change = ensoniq->spdif_stream != val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) ensoniq->spdif_stream = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (change && (ensoniq->playback1_substream != NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ensoniq->playback2_substream != NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define ES1371_SPDIF(xname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #define snd_es1371_spdif_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) unsigned int nval1, nval2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) ensoniq->ctrl |= nval1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) ensoniq->cssr &= ~ES_1373_SPDIF_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ensoniq->cssr |= nval2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* spdif controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static const struct snd_kcontrol_new snd_es1371_mixer_spdif[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .info = snd_ens1373_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .get = snd_ens1373_spdif_default_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .put = snd_ens1373_spdif_default_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .info = snd_ens1373_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .get = snd_ens1373_spdif_mask_get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .info = snd_ens1373_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .get = snd_ens1373_spdif_stream_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .put = snd_ens1373_spdif_stream_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define snd_es1373_rear_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) ucontrol->value.integer.value[0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) unsigned int nval1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) nval1 = ucontrol->value.integer.value[0] ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ensoniq->cssr |= nval1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static const struct snd_kcontrol_new snd_ens1373_rear =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .name = "AC97 2ch->4ch Copy Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .info = snd_es1373_rear_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .get = snd_es1373_rear_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .put = snd_es1373_rear_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define snd_es1373_line_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (ensoniq->ctrl & ES_1371_GPIO_OUT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) ucontrol->value.integer.value[0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) ctrl = ensoniq->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (ucontrol->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) changed = (ctrl != ensoniq->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static const struct snd_kcontrol_new snd_ens1373_line =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .name = "Line In->Rear Out Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .info = snd_es1373_line_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .get = snd_es1373_line_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .put = snd_es1373_line_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) struct ensoniq *ensoniq = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) ensoniq->u.es1371.ac97 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) struct es1371_quirk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) unsigned short vid; /* vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) unsigned short did; /* device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) unsigned char rev; /* revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static int es1371_quirk_lookup(struct ensoniq *ensoniq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) const struct es1371_quirk *list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) while (list->vid != (unsigned short)PCI_ANY_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (ensoniq->pci->vendor == list->vid &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) ensoniq->pci->device == list->did &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) ensoniq->rev == list->rev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) list++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static const struct es1371_quirk es1371_spdif_present[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static const struct snd_pci_quirk ens1373_line_quirk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) { } /* end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static int snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) int has_spdif, int has_line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct snd_card *card = ensoniq->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) struct snd_ac97_bus *pbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) struct snd_ac97_template ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) static const struct snd_ac97_bus_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .write = snd_es1371_codec_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .read = snd_es1371_codec_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .wait = snd_es1371_codec_wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) ac97.private_data = ensoniq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) ac97.private_free = snd_ensoniq_mixer_free_ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) ac97.pci = ensoniq->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) ac97.scaps = AC97_SCAP_AUDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (has_spdif > 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) int i, is_spdif = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) ensoniq->spdif_default = ensoniq->spdif_stream =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) SNDRV_PCM_DEFAULT_CON_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) is_spdif++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (!kctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) kctl->id.index = is_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) err = snd_ctl_add(card, kctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* mirror rear to front speakers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) ensoniq->cssr |= ES_1373_REAR_BIT26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (has_line > 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ensoniq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) #endif /* CHIP1371 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* generic control callbacks for ens1370 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) #define ENSONIQ_CONTROL(xname, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .private_value = mask }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) #define snd_ensoniq_control_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) int mask = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) int mask = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) unsigned int nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) nval = ucontrol->value.integer.value[0] ? mask : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) change = (ensoniq->ctrl & mask) != nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) ensoniq->ctrl &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) ensoniq->ctrl |= nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) * ENS1370 mixer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) static const struct snd_kcontrol_new snd_es1370_controls[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) struct ensoniq *ensoniq = ak4531->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) ensoniq->u.es1370.ak4531 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static int snd_ensoniq_1370_mixer(struct ensoniq *ensoniq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) struct snd_card *card = ensoniq->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) struct snd_ak4531 ak4531;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* try reset AK4531 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) inw(ES_REG(ensoniq, 1370_CODEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) inw(ES_REG(ensoniq, 1370_CODEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) memset(&ak4531, 0, sizeof(ak4531));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) ak4531.write = snd_es1370_codec_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) ak4531.private_data = ensoniq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) for (idx = 0; idx < ES1370_CONTROLS; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) #endif /* CHIP1370 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) switch (joystick_port[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) case 0: /* disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) case 1: /* auto-detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) case 0x200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) case 0x208:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) case 0x210:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) case 0x218:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) return joystick_port[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) dev_err(ensoniq->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) "invalid joystick port %#x", joystick_port[dev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) return joystick[dev] ? 0x200 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) static int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) struct gameport *gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) int io_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) io_port = snd_ensoniq_get_joystick_port(ensoniq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) switch (io_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) case 1: /* auto_detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) for (io_port = 0x200; io_port <= 0x218; io_port += 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) if (request_region(io_port, 8, "ens137x: gameport"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (io_port > 0x218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) dev_warn(ensoniq->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) "no gameport ports available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) if (!request_region(io_port, 8, "ens137x: gameport")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) dev_warn(ensoniq->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) "gameport io port %#x in use\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) io_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) ensoniq->gameport = gp = gameport_allocate_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) if (!gp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) dev_err(ensoniq->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) "cannot allocate memory for gameport\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) release_region(io_port, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) gameport_set_name(gp, "ES137x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) gameport_set_dev_parent(gp, &ensoniq->pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) gp->io = io_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) ensoniq->ctrl |= ES_JYSTK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) gameport_register_port(ensoniq->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) if (ensoniq->gameport) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) int port = ensoniq->gameport->io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) gameport_unregister_port(ensoniq->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) ensoniq->gameport = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) ensoniq->ctrl &= ~ES_JYSTK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) release_region(port, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) #endif /* SUPPORT_JOYSTICK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) struct ensoniq *ensoniq = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) snd_iprintf(buffer, "Ensoniq AudioPCI " CHIP_NAME "\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) snd_iprintf(buffer, "Joystick enable : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) snd_iprintf(buffer, "MIC +5V bias : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) snd_iprintf(buffer, "Line In to AOUT : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) snd_iprintf(buffer, "Joystick port : 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) static void snd_ensoniq_proc_init(struct ensoniq *ensoniq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) snd_card_ro_proc_new(ensoniq->card, "audiopci", ensoniq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) snd_ensoniq_proc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) static int snd_ensoniq_free(struct ensoniq *ensoniq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) snd_ensoniq_free_gameport(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (ensoniq->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) goto __hw_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) pci_set_power_state(ensoniq->pci, PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) __hw_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if (ensoniq->dma_bug.area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) snd_dma_free_pages(&ensoniq->dma_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) if (ensoniq->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) free_irq(ensoniq->irq, ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) pci_release_regions(ensoniq->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) pci_disable_device(ensoniq->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) kfree(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static int snd_ensoniq_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) struct ensoniq *ensoniq = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) return snd_ensoniq_free(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static const struct snd_pci_quirk es1371_amplifier_hack[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) { } /* end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static const struct es1371_quirk es1371_ac97_reset_hack[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) /* this code was part of snd_ensoniq_create before intruduction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) * of suspend/resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) outl(0, ES_REG(ensoniq, 1371_LEGACY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) /* need to delay around 20ms(bleech) to give
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) some CODECs enough time to wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) /* AC'97 warm reset to start the bitclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) inl(ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) /* Init the sample rate converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) snd_es1371_wait_src_ready(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) for (idx = 0; idx < 0x80; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) snd_es1371_src_write(ensoniq, idx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) snd_es1371_adc_rate(ensoniq, 22050);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) snd_es1371_dac1_rate(ensoniq, 22050);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) snd_es1371_dac2_rate(ensoniq, 22050);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) /* WARNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) * enabling the sample rate converter without properly programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) * its parameters causes the chip to lock up (the SRC busy bit will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) * be stuck high, and I've found no way to rectify this other than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) * power cycle) - Thomas Sailer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) snd_es1371_wait_src_ready(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) outl(0, ES_REG(ensoniq, 1371_SMPRATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) /* try reset codec directly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) outb(0x00, ES_REG(ensoniq, UART_RES));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) static int snd_ensoniq_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) struct ensoniq *ensoniq = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) snd_ac97_suspend(ensoniq->u.es1371.ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) /* try to reset AK4531 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) inw(ES_REG(ensoniq, 1370_CODEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) inw(ES_REG(ensoniq, 1370_CODEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) static int snd_ensoniq_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) struct ensoniq *ensoniq = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) snd_ensoniq_chip_init(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) snd_ac97_resume(ensoniq->u.es1371.ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) snd_ak4531_resume(ensoniq->u.es1370.ak4531);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) static SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) #define SND_ENSONIQ_PM_OPS &snd_ensoniq_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) #define SND_ENSONIQ_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) static int snd_ensoniq_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) struct ensoniq **rensoniq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) struct ensoniq *ensoniq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .dev_free = snd_ensoniq_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) *rensoniq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if ((err = pci_enable_device(pci)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) if (ensoniq == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) spin_lock_init(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) mutex_init(&ensoniq->src_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) ensoniq->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) ensoniq->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) ensoniq->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) kfree(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) ensoniq->port = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) KBUILD_MODNAME, ensoniq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) snd_ensoniq_free(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) ensoniq->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) card->sync_irq = ensoniq->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) 16, &ensoniq->dma_bug) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) dev_err(card->dev, "unable to allocate space for phantom area - dma_bug\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) snd_ensoniq_free(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) ensoniq->rev = pci->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) #else /* get microphone working */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) ensoniq->sctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) ensoniq->ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) ensoniq->sctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) ensoniq->cssr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) ensoniq->cssr |= ES_1371_ST_AC97_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) snd_ensoniq_chip_init(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) snd_ensoniq_free(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) snd_ensoniq_proc_init(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) *rensoniq = ensoniq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) * MIDI section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) struct snd_rawmidi *rmidi = ensoniq->rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) unsigned char status, mask, byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) if (rmidi == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) /* do Rx at first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) spin_lock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) while (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) status = inb(ES_REG(ensoniq, UART_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) if ((status & mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) byte = inb(ES_REG(ensoniq, UART_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) spin_unlock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) /* do Tx at second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) spin_lock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) while (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) status = inb(ES_REG(ensoniq, UART_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if ((status & mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) ensoniq->uartc &= ~ES_TXINTENM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) mask &= ~ES_TXRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) outb(byte, ES_REG(ensoniq, UART_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) spin_unlock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) struct ensoniq *ensoniq = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) ensoniq->uartm |= ES_MODE_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) ensoniq->midi_input = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) struct ensoniq *ensoniq = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) ensoniq->midi_input = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) ensoniq->uartm &= ~ES_MODE_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) struct ensoniq *ensoniq = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) ensoniq->uartm |= ES_MODE_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) ensoniq->midi_output = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if (!(ensoniq->uartm & ES_MODE_INPUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) struct ensoniq *ensoniq = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) spin_lock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) if (!(ensoniq->uartm & ES_MODE_INPUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) ensoniq->midi_output = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) ensoniq->uartm &= ~ES_MODE_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) spin_unlock_irq(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) struct ensoniq *ensoniq = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) spin_lock_irqsave(&ensoniq->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) if (up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) if ((ensoniq->uartc & ES_RXINTEN) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) /* empty input FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) for (idx = 0; idx < 32; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) inb(ES_REG(ensoniq, UART_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) ensoniq->uartc |= ES_RXINTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) if (ensoniq->uartc & ES_RXINTEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) ensoniq->uartc &= ~ES_RXINTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) struct ensoniq *ensoniq = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) unsigned char byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) spin_lock_irqsave(&ensoniq->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) if (up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) if (ES_TXINTENI(ensoniq->uartc) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) ensoniq->uartc |= ES_TXINTENO(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) while (ES_TXINTENI(ensoniq->uartc) == 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) ensoniq->uartc &= ~ES_TXINTENM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) outb(byte, ES_REG(ensoniq, UART_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) if (ES_TXINTENI(ensoniq->uartc) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) ensoniq->uartc &= ~ES_TXINTENM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) static const struct snd_rawmidi_ops snd_ensoniq_midi_output =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .open = snd_ensoniq_midi_output_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .close = snd_ensoniq_midi_output_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .trigger = snd_ensoniq_midi_output_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) static const struct snd_rawmidi_ops snd_ensoniq_midi_input =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .open = snd_ensoniq_midi_input_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .close = snd_ensoniq_midi_input_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .trigger = snd_ensoniq_midi_input_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) static int snd_ensoniq_midi(struct ensoniq *ensoniq, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) strcpy(rmidi->name, CHIP_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) SNDRV_RAWMIDI_INFO_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) rmidi->private_data = ensoniq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) ensoniq->rmidi = rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) * Interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) struct ensoniq *ensoniq = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) unsigned int status, sctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) if (ensoniq == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) status = inl(ES_REG(ensoniq, STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) if (!(status & ES_INTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) spin_lock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) sctrl = ensoniq->sctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) if (status & ES_DAC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) sctrl &= ~ES_P1_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) if (status & ES_DAC2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) sctrl &= ~ES_P2_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) if (status & ES_ADC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) sctrl &= ~ES_R1_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) outl(sctrl, ES_REG(ensoniq, SERIAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) spin_unlock(&ensoniq->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) if (status & ES_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) snd_ensoniq_midi_interrupt(ensoniq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) if ((status & ES_DAC2) && ensoniq->playback2_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) snd_pcm_period_elapsed(ensoniq->playback2_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) if ((status & ES_ADC) && ensoniq->capture_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) snd_pcm_period_elapsed(ensoniq->capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) if ((status & ES_DAC1) && ensoniq->playback1_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) snd_pcm_period_elapsed(ensoniq->playback1_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) static int snd_audiopci_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) struct ensoniq *ensoniq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) card->private_data = ensoniq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) #ifdef CHIP1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) #ifdef CHIP1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) if ((err = snd_ensoniq_pcm(ensoniq, 0)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) if ((err = snd_ensoniq_pcm2(ensoniq, 1)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) if ((err = snd_ensoniq_midi(ensoniq, 0)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) snd_ensoniq_create_gameport(ensoniq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) strcpy(card->driver, DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) strcpy(card->shortname, "Ensoniq AudioPCI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) sprintf(card->longname, "%s %s at 0x%lx, irq %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) card->shortname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) card->driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) ensoniq->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) ensoniq->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) if ((err = snd_card_register(card)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) static void snd_audiopci_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) static struct pci_driver ens137x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .id_table = snd_audiopci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .probe = snd_audiopci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .remove = snd_audiopci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .pm = SND_ENSONIQ_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) module_pci_driver(ens137x_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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