^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Driver p17v chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Version: 0.01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* Audigy2Value Tina (P17V) pointer-offset register set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * accessed through the PTR20 and DATA24 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* 00 - 07: Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define P17V_PLAYBACK_FIFO_PTR 0x08 /* Current playback fifo pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * and number of sound samples in cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* 09 - 12: Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define P17V_CAPTURE_FIFO_PTR 0x13 /* Current capture fifo pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * and number of sound samples in cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* 14 - 17: Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define P17V_PB_CHN_SEL 0x18 /* P17v playback channel select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define P17V_SE_SLOT_SEL_L 0x19 /* Sound Engine slot select low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define P17V_SE_SLOT_SEL_H 0x1a /* Sound Engine slot select high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* 1b - 1f: Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* 20 - 2f: Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* 30 - 3b: Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define P17V_SPI 0x3c /* SPI interface register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define P17V_I2C_ADDR 0x3d /* I2C Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define P17V_I2C_0 0x3e /* I2C Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define P17V_I2C_1 0x3f /* I2C Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* I2C values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define I2C_A_ADC_ADD_MASK 0x000000fe /*The address is a 7 bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define I2C_A_ADC_RW_MASK 0x00000001 /*bit mask for R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define I2C_A_ADC_TRANS_MASK 0x00000010 /*Bit mask for I2c address DAC value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I2C_A_ADC_ABORT_MASK 0x00000020 /*Bit mask for I2C transaction abort flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2C_A_ADC_LAST_MASK 0x00000040 /*Bit mask for Last word transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I2C_A_ADC_BYTE_MASK 0x00000080 /*Bit mask for Byte Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2C_A_ADC_ADD 0x00000034 /*This is the Device address for ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2C_A_ADC_READ 0x00000001 /*To perform a read operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I2C_A_ADC_START 0x00000100 /*Start I2C transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2C_A_ADC_ABORT 0x00000200 /*I2C transaction abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I2C_A_ADC_LAST 0x00000400 /*I2C last transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2C_A_ADC_BYTE 0x00000800 /*I2C one byte mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2C_D_ADC_REG_MASK 0xfe000000 /*ADC address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I2C_D_ADC_DAT_MASK 0x01ff0000 /*ADC data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ADC_TIMEOUT 0x00000007 /*ADC Timeout Clock Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADC_IFC_CTRL 0x0000000b /*ADC Interface Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADC_MASTER 0x0000000c /*ADC Master Mode Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ADC_POWER 0x0000000d /*ADC PowerDown Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADC_ATTEN_ADCL 0x0000000e /*ADC Attenuation ADCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADC_ATTEN_ADCR 0x0000000f /*ADC Attenuation ADCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ADC_ALC_CTRL1 0x00000010 /*ADC ALC Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADC_ALC_CTRL2 0x00000011 /*ADC ALC Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ADC_ALC_CTRL3 0x00000012 /*ADC ALC Control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ADC_NOISE_CTRL 0x00000013 /*ADC Noise Gate Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ADC_LIMIT_CTRL 0x00000014 /*ADC Limiter Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ADC_MUX 0x00000015 /*ADC Mux offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* FIXME: Not tested yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ADC_GAIN_MASK 0x000000ff //Mask for ADC Gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ADC_ZERODB 0x000000cf //Value to set ADC to 0dB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ADC_MUTE_MASK 0x000000c0 //Mask for ADC mute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ADC_MUTE 0x000000c0 //Value to mute ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ADC_OSR 0x00000008 //Mask for ADC oversample rate select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ADC_TIMEOUT_DISABLE 0x00000008 //Value and mask to disable Timeout clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ADC_HPF_DISABLE 0x00000100 //Value and mask to disable High pass filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ADC_TRANWIN_MASK 0x00000070 //Mask for Length of Transient Window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ADC_MUX_MASK 0x0000000f //Mask for ADC Mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ADC_MUX_0 0x00000001 //Value to select Unknown at ADC Mux (Not used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ADC_MUX_1 0x00000002 //Value to select Unknown at ADC Mux (Not used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ADC_MUX_2 0x00000004 //Value to select Mic at ADC Mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ADC_MUX_3 0x00000008 //Value to select Line-In at ADC Mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define P17V_START_AUDIO 0x40 /* Start Audio bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* 41 - 47: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define P17V_START_CAPTURE 0x48 /* Start Capture bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define P17V_CAPTURE_FIFO_BASE 0x49 /* Record FIFO base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define P17V_CAPTURE_FIFO_SIZE 0x4a /* Record FIFO buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define P17V_CAPTURE_FIFO_INDEX 0x4b /* Record FIFO capture index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define P17V_CAPTURE_VOL_H 0x4c /* P17v capture volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define P17V_CAPTURE_VOL_L 0x4d /* P17v capture volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* 4e - 4f: Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* 50 - 5f: Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define P17V_SRCSel 0x60 /* SRC48 and SRCMulti sample rate select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * and output select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define P17V_MIXER_AC97_10K1_VOL_L 0x61 /* 10K to Mixer_AC97 input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define P17V_MIXER_AC97_10K1_VOL_H 0x62 /* 10K to Mixer_AC97 input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define P17V_MIXER_AC97_P17V_VOL_L 0x63 /* P17V to Mixer_AC97 input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define P17V_MIXER_AC97_P17V_VOL_H 0x64 /* P17V to Mixer_AC97 input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define P17V_MIXER_AC97_SRP_REC_VOL_L 0x65 /* SRP Record to Mixer_AC97 input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define P17V_MIXER_AC97_SRP_REC_VOL_H 0x66 /* SRP Record to Mixer_AC97 input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* 67 - 68: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define P17V_MIXER_Spdif_10K1_VOL_L 0x69 /* 10K to Mixer_Spdif input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define P17V_MIXER_Spdif_10K1_VOL_H 0x6A /* 10K to Mixer_Spdif input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define P17V_MIXER_Spdif_P17V_VOL_L 0x6B /* P17V to Mixer_Spdif input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define P17V_MIXER_Spdif_P17V_VOL_H 0x6C /* P17V to Mixer_Spdif input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define P17V_MIXER_Spdif_SRP_REC_VOL_L 0x6D /* SRP Record to Mixer_Spdif input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define P17V_MIXER_Spdif_SRP_REC_VOL_H 0x6E /* SRP Record to Mixer_Spdif input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* 6f - 70: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define P17V_MIXER_I2S_10K1_VOL_L 0x71 /* 10K to Mixer_I2S input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define P17V_MIXER_I2S_10K1_VOL_H 0x72 /* 10K to Mixer_I2S input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define P17V_MIXER_I2S_P17V_VOL_L 0x73 /* P17V to Mixer_I2S input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define P17V_MIXER_I2S_P17V_VOL_H 0x74 /* P17V to Mixer_I2S input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define P17V_MIXER_I2S_SRP_REC_VOL_L 0x75 /* SRP Record to Mixer_I2S input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define P17V_MIXER_I2S_SRP_REC_VOL_H 0x76 /* SRP Record to Mixer_I2S input volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* 77 - 78: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define P17V_MIXER_AC97_ENABLE 0x79 /* Mixer AC97 input audio enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define P17V_MIXER_SPDIF_ENABLE 0x7A /* Mixer SPDIF input audio enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define P17V_MIXER_I2S_ENABLE 0x7B /* Mixer I2S input audio enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define P17V_AUDIO_OUT_ENABLE 0x7C /* Audio out enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define P17V_MIXER_ATT 0x7D /* SRP Mixer Attenuation Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define P17V_SRP_RECORD_SRR 0x7E /* SRP Record channel source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define P17V_SOFT_RESET_SRP_MIXER 0x7F /* SRP and mixer soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define P17V_AC97_OUT_MASTER_VOL_L 0x80 /* AC97 Output master volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define P17V_AC97_OUT_MASTER_VOL_H 0x81 /* AC97 Output master volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define P17V_SPDIF_OUT_MASTER_VOL_L 0x82 /* SPDIF Output master volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define P17V_SPDIF_OUT_MASTER_VOL_H 0x83 /* SPDIF Output master volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define P17V_I2S_OUT_MASTER_VOL_L 0x84 /* I2S Output master volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define P17V_I2S_OUT_MASTER_VOL_H 0x85 /* I2S Output master volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* 86 - 87: Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define P17V_I2S_CHANNEL_SWAP_PHASE_INVERSE 0x88 /* I2S out mono channel swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * and phase inverse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define P17V_SPDIF_CHANNEL_SWAP_PHASE_INVERSE 0x89 /* SPDIF out mono channel swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * and phase inverse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* 8A: Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define P17V_SRP_P17V_ESR 0x8B /* SRP_P17V estimated sample rate and rate lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define P17V_SRP_REC_ESR 0x8C /* SRP_REC estimated sample rate and rate lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define P17V_SRP_BYPASS 0x8D /* srps channel bypass and srps bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* 8E - 92: Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define P17V_I2S_SRC_SEL 0x93 /* I2SIN mode sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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