^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Creative Labs, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Routines for control of EMU10K1 chips / mixer routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Multichannel PCM support Copyright (c) Lee Revell <rlrevell@joe-job.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Added EMU 1010 support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * BUGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/emu10k1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "p17v.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AC97_ID_STAC9758 0x83847658
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const DECLARE_TLV_DB_SCALE(snd_audigy_db_scale2, -10350, 50, 1); /* WM8775 gain scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int snd_emu10k1_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int snd_emu10k1_spdif_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Limit: emu->spdif_bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (idx >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ucontrol->value.iec958.status[0] = (emu->spdif_bits[idx] >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ucontrol->value.iec958.status[1] = (emu->spdif_bits[idx] >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ucontrol->value.iec958.status[2] = (emu->spdif_bits[idx] >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ucontrol->value.iec958.status[3] = (emu->spdif_bits[idx] >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int snd_emu10k1_spdif_get_mask(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ucontrol->value.iec958.status[0] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ucontrol->value.iec958.status[1] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ucontrol->value.iec958.status[2] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ucontrol->value.iec958.status[3] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Items labels in enum mixer controls assigning source data to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * each destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const char * const emu1010_src_texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "Silence",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "Dock Mic A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "Dock Mic B",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "Dock ADC1 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "Dock ADC1 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "Dock ADC2 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "Dock ADC2 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "Dock ADC3 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "Dock ADC3 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "0202 ADC Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "0202 ADC Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "0202 SPDIF Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "0202 SPDIF Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "ADAT 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "ADAT 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "ADAT 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "ADAT 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "ADAT 4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "ADAT 5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "ADAT 6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "ADAT 7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "DSP 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "DSP 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "DSP 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "DSP 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "DSP 4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "DSP 5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "DSP 6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "DSP 7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "DSP 8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "DSP 9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "DSP 10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "DSP 11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "DSP 12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "DSP 13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "DSP 14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "DSP 15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "DSP 16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "DSP 17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "DSP 18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "DSP 19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "DSP 20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "DSP 21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "DSP 22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "DSP 23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "DSP 24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "DSP 25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "DSP 26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "DSP 27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "DSP 28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "DSP 29",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "DSP 30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "DSP 31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* 1616(m) cardbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const char * const emu1616_src_texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "Silence",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "Dock Mic A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "Dock Mic B",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "Dock ADC1 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "Dock ADC1 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "Dock ADC2 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "Dock ADC2 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "Dock SPDIF Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "Dock SPDIF Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "ADAT 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "ADAT 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "ADAT 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "ADAT 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "ADAT 4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "ADAT 5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "ADAT 6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "ADAT 7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "DSP 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "DSP 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "DSP 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "DSP 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "DSP 4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "DSP 5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "DSP 6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "DSP 7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "DSP 8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "DSP 9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "DSP 10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "DSP 11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "DSP 12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "DSP 13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "DSP 14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "DSP 15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "DSP 16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "DSP 17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "DSP 18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "DSP 19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "DSP 20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "DSP 21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "DSP 22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "DSP 23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "DSP 24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "DSP 25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "DSP 26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "DSP 27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "DSP 28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "DSP 29",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "DSP 30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "DSP 31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * List of data sources available for each destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const unsigned int emu1010_src_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) EMU_SRC_SILENCE,/* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) EMU_SRC_DOCK_MIC_A1, /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) EMU_SRC_DOCK_MIC_B1, /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) EMU_SRC_DOCK_ADC1_LEFT1, /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) EMU_SRC_DOCK_ADC1_RIGHT1, /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) EMU_SRC_DOCK_ADC2_LEFT1, /* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) EMU_SRC_DOCK_ADC2_RIGHT1, /* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) EMU_SRC_DOCK_ADC3_LEFT1, /* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) EMU_SRC_DOCK_ADC3_RIGHT1, /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) EMU_SRC_HAMOA_ADC_LEFT1, /* 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) EMU_SRC_HAMOA_ADC_RIGHT1, /* 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) EMU_SRC_HANA_SPDIF_LEFT1, /* 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) EMU_SRC_HANA_SPDIF_RIGHT1, /* 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) EMU_SRC_HANA_ADAT, /* 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) EMU_SRC_HANA_ADAT+1, /* 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) EMU_SRC_HANA_ADAT+2, /* 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) EMU_SRC_HANA_ADAT+3, /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) EMU_SRC_HANA_ADAT+4, /* 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) EMU_SRC_HANA_ADAT+5, /* 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) EMU_SRC_HANA_ADAT+6, /* 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) EMU_SRC_HANA_ADAT+7, /* 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) EMU_SRC_ALICE_EMU32A, /* 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) EMU_SRC_ALICE_EMU32A+1, /* 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) EMU_SRC_ALICE_EMU32A+2, /* 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) EMU_SRC_ALICE_EMU32A+3, /* 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) EMU_SRC_ALICE_EMU32A+4, /* 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) EMU_SRC_ALICE_EMU32A+5, /* 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) EMU_SRC_ALICE_EMU32A+6, /* 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) EMU_SRC_ALICE_EMU32A+7, /* 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) EMU_SRC_ALICE_EMU32A+8, /* 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) EMU_SRC_ALICE_EMU32A+9, /* 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) EMU_SRC_ALICE_EMU32A+0xa, /* 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) EMU_SRC_ALICE_EMU32A+0xb, /* 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) EMU_SRC_ALICE_EMU32A+0xc, /* 33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) EMU_SRC_ALICE_EMU32A+0xd, /* 34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) EMU_SRC_ALICE_EMU32A+0xe, /* 35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) EMU_SRC_ALICE_EMU32A+0xf, /* 36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) EMU_SRC_ALICE_EMU32B, /* 37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) EMU_SRC_ALICE_EMU32B+1, /* 38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) EMU_SRC_ALICE_EMU32B+2, /* 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) EMU_SRC_ALICE_EMU32B+3, /* 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) EMU_SRC_ALICE_EMU32B+4, /* 41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) EMU_SRC_ALICE_EMU32B+5, /* 42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) EMU_SRC_ALICE_EMU32B+6, /* 43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) EMU_SRC_ALICE_EMU32B+7, /* 44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) EMU_SRC_ALICE_EMU32B+8, /* 45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) EMU_SRC_ALICE_EMU32B+9, /* 46 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) EMU_SRC_ALICE_EMU32B+0xa, /* 47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) EMU_SRC_ALICE_EMU32B+0xb, /* 48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) EMU_SRC_ALICE_EMU32B+0xc, /* 49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) EMU_SRC_ALICE_EMU32B+0xd, /* 50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) EMU_SRC_ALICE_EMU32B+0xe, /* 51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) EMU_SRC_ALICE_EMU32B+0xf, /* 52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* 1616(m) cardbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const unsigned int emu1616_src_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) EMU_SRC_SILENCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) EMU_SRC_DOCK_MIC_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) EMU_SRC_DOCK_MIC_B1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) EMU_SRC_DOCK_ADC1_LEFT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) EMU_SRC_DOCK_ADC1_RIGHT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) EMU_SRC_DOCK_ADC2_LEFT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) EMU_SRC_DOCK_ADC2_RIGHT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) EMU_SRC_MDOCK_SPDIF_LEFT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) EMU_SRC_MDOCK_SPDIF_RIGHT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) EMU_SRC_MDOCK_ADAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) EMU_SRC_MDOCK_ADAT+1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) EMU_SRC_MDOCK_ADAT+2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) EMU_SRC_MDOCK_ADAT+3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) EMU_SRC_MDOCK_ADAT+4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) EMU_SRC_MDOCK_ADAT+5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) EMU_SRC_MDOCK_ADAT+6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) EMU_SRC_MDOCK_ADAT+7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) EMU_SRC_ALICE_EMU32A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) EMU_SRC_ALICE_EMU32A+1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) EMU_SRC_ALICE_EMU32A+2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) EMU_SRC_ALICE_EMU32A+3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) EMU_SRC_ALICE_EMU32A+4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) EMU_SRC_ALICE_EMU32A+5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) EMU_SRC_ALICE_EMU32A+6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) EMU_SRC_ALICE_EMU32A+7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) EMU_SRC_ALICE_EMU32A+8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) EMU_SRC_ALICE_EMU32A+9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) EMU_SRC_ALICE_EMU32A+0xa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) EMU_SRC_ALICE_EMU32A+0xb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) EMU_SRC_ALICE_EMU32A+0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) EMU_SRC_ALICE_EMU32A+0xd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) EMU_SRC_ALICE_EMU32A+0xe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) EMU_SRC_ALICE_EMU32A+0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) EMU_SRC_ALICE_EMU32B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) EMU_SRC_ALICE_EMU32B+1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) EMU_SRC_ALICE_EMU32B+2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) EMU_SRC_ALICE_EMU32B+3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) EMU_SRC_ALICE_EMU32B+4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) EMU_SRC_ALICE_EMU32B+5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) EMU_SRC_ALICE_EMU32B+6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) EMU_SRC_ALICE_EMU32B+7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) EMU_SRC_ALICE_EMU32B+8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) EMU_SRC_ALICE_EMU32B+9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) EMU_SRC_ALICE_EMU32B+0xa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) EMU_SRC_ALICE_EMU32B+0xb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) EMU_SRC_ALICE_EMU32B+0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) EMU_SRC_ALICE_EMU32B+0xd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) EMU_SRC_ALICE_EMU32B+0xe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) EMU_SRC_ALICE_EMU32B+0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Data destinations - physical EMU outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * Each destination has an enum mixer control to choose a data source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const unsigned int emu1010_output_dst[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) EMU_DST_DOCK_DAC1_LEFT1, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) EMU_DST_DOCK_DAC1_RIGHT1, /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) EMU_DST_DOCK_DAC2_LEFT1, /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) EMU_DST_DOCK_DAC2_RIGHT1, /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) EMU_DST_DOCK_DAC3_LEFT1, /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) EMU_DST_DOCK_DAC3_RIGHT1, /* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) EMU_DST_DOCK_DAC4_LEFT1, /* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) EMU_DST_DOCK_DAC4_RIGHT1, /* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) EMU_DST_DOCK_PHONES_LEFT1, /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) EMU_DST_DOCK_PHONES_RIGHT1, /* 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) EMU_DST_DOCK_SPDIF_LEFT1, /* 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) EMU_DST_DOCK_SPDIF_RIGHT1, /* 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) EMU_DST_HANA_SPDIF_LEFT1, /* 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) EMU_DST_HANA_SPDIF_RIGHT1, /* 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) EMU_DST_HAMOA_DAC_LEFT1, /* 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) EMU_DST_HAMOA_DAC_RIGHT1, /* 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) EMU_DST_HANA_ADAT, /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) EMU_DST_HANA_ADAT+1, /* 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) EMU_DST_HANA_ADAT+2, /* 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) EMU_DST_HANA_ADAT+3, /* 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) EMU_DST_HANA_ADAT+4, /* 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) EMU_DST_HANA_ADAT+5, /* 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) EMU_DST_HANA_ADAT+6, /* 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) EMU_DST_HANA_ADAT+7, /* 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* 1616(m) cardbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const unsigned int emu1616_output_dst[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) EMU_DST_DOCK_DAC1_LEFT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) EMU_DST_DOCK_DAC1_RIGHT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) EMU_DST_DOCK_DAC2_LEFT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) EMU_DST_DOCK_DAC2_RIGHT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) EMU_DST_DOCK_DAC3_LEFT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) EMU_DST_DOCK_DAC3_RIGHT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) EMU_DST_MDOCK_SPDIF_LEFT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) EMU_DST_MDOCK_SPDIF_RIGHT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) EMU_DST_MDOCK_ADAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) EMU_DST_MDOCK_ADAT+1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) EMU_DST_MDOCK_ADAT+2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) EMU_DST_MDOCK_ADAT+3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) EMU_DST_MDOCK_ADAT+4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) EMU_DST_MDOCK_ADAT+5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) EMU_DST_MDOCK_ADAT+6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) EMU_DST_MDOCK_ADAT+7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) EMU_DST_MANA_DAC_LEFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) EMU_DST_MANA_DAC_RIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Data destinations - HANA outputs going to Alice2 (audigy) for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * capture (EMU32 + I2S links)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * Each destination has an enum mixer control to choose a data source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const unsigned int emu1010_input_dst[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) EMU_DST_ALICE2_EMU32_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) EMU_DST_ALICE2_EMU32_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) EMU_DST_ALICE2_EMU32_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) EMU_DST_ALICE2_EMU32_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) EMU_DST_ALICE2_EMU32_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) EMU_DST_ALICE2_EMU32_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) EMU_DST_ALICE2_EMU32_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) EMU_DST_ALICE2_EMU32_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) EMU_DST_ALICE2_EMU32_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) EMU_DST_ALICE2_EMU32_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) EMU_DST_ALICE2_EMU32_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) EMU_DST_ALICE2_EMU32_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) EMU_DST_ALICE2_EMU32_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) EMU_DST_ALICE2_EMU32_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) EMU_DST_ALICE2_EMU32_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) EMU_DST_ALICE2_EMU32_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) EMU_DST_ALICE_I2S0_LEFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) EMU_DST_ALICE_I2S0_RIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) EMU_DST_ALICE_I2S1_LEFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) EMU_DST_ALICE_I2S1_RIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) EMU_DST_ALICE_I2S2_LEFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) EMU_DST_ALICE_I2S2_RIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int snd_emu1010_input_output_source_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return snd_ctl_enum_info(uinfo, 1, 49, emu1616_src_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return snd_ctl_enum_info(uinfo, 1, 53, emu1010_src_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int snd_emu1010_output_source_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) channel = (kcontrol->private_value) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Limit: emu1010_output_dst, emu->emu1010.output_source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (channel >= 24 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) channel >= 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ucontrol->value.enumerated.item[0] = emu->emu1010.output_source[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int snd_emu1010_output_source_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) val = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (val >= 53 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) val >= 49))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) channel = (kcontrol->private_value) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Limit: emu1010_output_dst, emu->emu1010.output_source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (channel >= 24 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) channel >= 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (emu->emu1010.output_source[channel] == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) emu->emu1010.output_source[channel] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) emu1616_output_dst[channel], emu1616_src_regs[val]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) emu1010_output_dst[channel], emu1010_src_regs[val]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int snd_emu1010_input_source_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) channel = (kcontrol->private_value) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Limit: emu1010_input_dst, emu->emu1010.input_source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (channel >= 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ucontrol->value.enumerated.item[0] = emu->emu1010.input_source[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int snd_emu1010_input_source_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) val = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (val >= 53 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) val >= 49))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) channel = (kcontrol->private_value) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Limit: emu1010_input_dst, emu->emu1010.input_source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (channel >= 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (emu->emu1010.input_source[channel] == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) emu->emu1010.input_source[channel] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) emu1010_input_dst[channel], emu1616_src_regs[val]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) emu1010_input_dst[channel], emu1010_src_regs[val]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define EMU1010_SOURCE_OUTPUT(xname,chid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .info = snd_emu1010_input_output_source_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .get = snd_emu1010_output_source_get, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .put = snd_emu1010_output_source_put, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .private_value = chid \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static const struct snd_kcontrol_new snd_emu1010_output_enum_ctls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) EMU1010_SOURCE_OUTPUT("Dock DAC1 Left Playback Enum", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) EMU1010_SOURCE_OUTPUT("Dock DAC1 Right Playback Enum", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) EMU1010_SOURCE_OUTPUT("Dock DAC2 Left Playback Enum", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) EMU1010_SOURCE_OUTPUT("Dock DAC2 Right Playback Enum", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) EMU1010_SOURCE_OUTPUT("Dock DAC3 Left Playback Enum", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) EMU1010_SOURCE_OUTPUT("Dock DAC3 Right Playback Enum", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) EMU1010_SOURCE_OUTPUT("Dock DAC4 Left Playback Enum", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) EMU1010_SOURCE_OUTPUT("Dock DAC4 Right Playback Enum", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) EMU1010_SOURCE_OUTPUT("Dock Phones Left Playback Enum", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) EMU1010_SOURCE_OUTPUT("Dock Phones Right Playback Enum", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) EMU1010_SOURCE_OUTPUT("Dock SPDIF Left Playback Enum", 0xa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) EMU1010_SOURCE_OUTPUT("Dock SPDIF Right Playback Enum", 0xb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) EMU1010_SOURCE_OUTPUT("1010 SPDIF Left Playback Enum", 0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) EMU1010_SOURCE_OUTPUT("1010 SPDIF Right Playback Enum", 0xd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) EMU1010_SOURCE_OUTPUT("0202 DAC Left Playback Enum", 0xe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) EMU1010_SOURCE_OUTPUT("0202 DAC Right Playback Enum", 0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) EMU1010_SOURCE_OUTPUT("1010 ADAT 0 Playback Enum", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) EMU1010_SOURCE_OUTPUT("1010 ADAT 1 Playback Enum", 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) EMU1010_SOURCE_OUTPUT("1010 ADAT 2 Playback Enum", 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) EMU1010_SOURCE_OUTPUT("1010 ADAT 3 Playback Enum", 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) EMU1010_SOURCE_OUTPUT("1010 ADAT 4 Playback Enum", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) EMU1010_SOURCE_OUTPUT("1010 ADAT 5 Playback Enum", 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) EMU1010_SOURCE_OUTPUT("1010 ADAT 6 Playback Enum", 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) EMU1010_SOURCE_OUTPUT("1010 ADAT 7 Playback Enum", 0x17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* 1616(m) cardbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct snd_kcontrol_new snd_emu1616_output_enum_ctls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) EMU1010_SOURCE_OUTPUT("Dock DAC1 Left Playback Enum", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) EMU1010_SOURCE_OUTPUT("Dock DAC1 Right Playback Enum", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) EMU1010_SOURCE_OUTPUT("Dock DAC2 Left Playback Enum", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) EMU1010_SOURCE_OUTPUT("Dock DAC2 Right Playback Enum", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) EMU1010_SOURCE_OUTPUT("Dock DAC3 Left Playback Enum", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) EMU1010_SOURCE_OUTPUT("Dock DAC3 Right Playback Enum", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) EMU1010_SOURCE_OUTPUT("Dock SPDIF Left Playback Enum", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) EMU1010_SOURCE_OUTPUT("Dock SPDIF Right Playback Enum", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) EMU1010_SOURCE_OUTPUT("Dock ADAT 0 Playback Enum", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) EMU1010_SOURCE_OUTPUT("Dock ADAT 1 Playback Enum", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) EMU1010_SOURCE_OUTPUT("Dock ADAT 2 Playback Enum", 0xa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) EMU1010_SOURCE_OUTPUT("Dock ADAT 3 Playback Enum", 0xb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) EMU1010_SOURCE_OUTPUT("Dock ADAT 4 Playback Enum", 0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) EMU1010_SOURCE_OUTPUT("Dock ADAT 5 Playback Enum", 0xd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) EMU1010_SOURCE_OUTPUT("Dock ADAT 6 Playback Enum", 0xe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) EMU1010_SOURCE_OUTPUT("Dock ADAT 7 Playback Enum", 0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) EMU1010_SOURCE_OUTPUT("Mana DAC Left Playback Enum", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) EMU1010_SOURCE_OUTPUT("Mana DAC Right Playback Enum", 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define EMU1010_SOURCE_INPUT(xname,chid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .info = snd_emu1010_input_output_source_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .get = snd_emu1010_input_source_get, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .put = snd_emu1010_input_source_put, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .private_value = chid \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const struct snd_kcontrol_new snd_emu1010_input_enum_ctls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) EMU1010_SOURCE_INPUT("DSP 0 Capture Enum", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) EMU1010_SOURCE_INPUT("DSP 1 Capture Enum", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) EMU1010_SOURCE_INPUT("DSP 2 Capture Enum", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) EMU1010_SOURCE_INPUT("DSP 3 Capture Enum", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) EMU1010_SOURCE_INPUT("DSP 4 Capture Enum", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) EMU1010_SOURCE_INPUT("DSP 5 Capture Enum", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) EMU1010_SOURCE_INPUT("DSP 6 Capture Enum", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) EMU1010_SOURCE_INPUT("DSP 7 Capture Enum", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) EMU1010_SOURCE_INPUT("DSP 8 Capture Enum", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) EMU1010_SOURCE_INPUT("DSP 9 Capture Enum", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) EMU1010_SOURCE_INPUT("DSP A Capture Enum", 0xa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) EMU1010_SOURCE_INPUT("DSP B Capture Enum", 0xb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) EMU1010_SOURCE_INPUT("DSP C Capture Enum", 0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) EMU1010_SOURCE_INPUT("DSP D Capture Enum", 0xd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) EMU1010_SOURCE_INPUT("DSP E Capture Enum", 0xe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) EMU1010_SOURCE_INPUT("DSP F Capture Enum", 0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) EMU1010_SOURCE_INPUT("DSP 10 Capture Enum", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) EMU1010_SOURCE_INPUT("DSP 11 Capture Enum", 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) EMU1010_SOURCE_INPUT("DSP 12 Capture Enum", 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) EMU1010_SOURCE_INPUT("DSP 13 Capture Enum", 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) EMU1010_SOURCE_INPUT("DSP 14 Capture Enum", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) EMU1010_SOURCE_INPUT("DSP 15 Capture Enum", 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define snd_emu1010_adc_pads_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int snd_emu1010_adc_pads_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned int mask = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ucontrol->value.integer.value[0] = (emu->emu1010.adc_pads & mask) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int snd_emu1010_adc_pads_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned int mask = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned int val, cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) val = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cache = emu->emu1010.adc_pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (val == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) cache = cache | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) cache = cache & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (cache != emu->emu1010.adc_pads) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, cache );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) emu->emu1010.adc_pads = cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define EMU1010_ADC_PADS(xname,chid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .info = snd_emu1010_adc_pads_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .get = snd_emu1010_adc_pads_get, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .put = snd_emu1010_adc_pads_put, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .private_value = chid \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const struct snd_kcontrol_new snd_emu1010_adc_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) EMU1010_ADC_PADS("ADC1 14dB PAD Audio Dock Capture Switch", EMU_HANA_DOCK_ADC_PAD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) EMU1010_ADC_PADS("ADC2 14dB PAD Audio Dock Capture Switch", EMU_HANA_DOCK_ADC_PAD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) EMU1010_ADC_PADS("ADC3 14dB PAD Audio Dock Capture Switch", EMU_HANA_DOCK_ADC_PAD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) EMU1010_ADC_PADS("ADC1 14dB PAD 0202 Capture Switch", EMU_HANA_0202_ADC_PAD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define snd_emu1010_dac_pads_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int snd_emu1010_dac_pads_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned int mask = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ucontrol->value.integer.value[0] = (emu->emu1010.dac_pads & mask) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int snd_emu1010_dac_pads_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) unsigned int mask = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned int val, cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) val = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) cache = emu->emu1010.dac_pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (val == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) cache = cache | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) cache = cache & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (cache != emu->emu1010.dac_pads) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, cache );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) emu->emu1010.dac_pads = cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define EMU1010_DAC_PADS(xname,chid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .info = snd_emu1010_dac_pads_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .get = snd_emu1010_dac_pads_get, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .put = snd_emu1010_dac_pads_put, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .private_value = chid \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static const struct snd_kcontrol_new snd_emu1010_dac_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) EMU1010_DAC_PADS("DAC1 Audio Dock 14dB PAD Playback Switch", EMU_HANA_DOCK_DAC_PAD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) EMU1010_DAC_PADS("DAC2 Audio Dock 14dB PAD Playback Switch", EMU_HANA_DOCK_DAC_PAD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) EMU1010_DAC_PADS("DAC3 Audio Dock 14dB PAD Playback Switch", EMU_HANA_DOCK_DAC_PAD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) EMU1010_DAC_PADS("DAC4 Audio Dock 14dB PAD Playback Switch", EMU_HANA_DOCK_DAC_PAD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) EMU1010_DAC_PADS("DAC1 0202 14dB PAD Playback Switch", EMU_HANA_0202_DAC_PAD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int snd_emu1010_internal_clock_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static const char * const texts[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "44100", "48000", "SPDIF", "ADAT"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return snd_ctl_enum_info(uinfo, 1, 4, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static int snd_emu1010_internal_clock_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ucontrol->value.enumerated.item[0] = emu->emu1010.internal_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static int snd_emu1010_internal_clock_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) val = ucontrol->value.enumerated.item[0] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* Limit: uinfo->value.enumerated.items = 4; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (val >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) change = (emu->emu1010.internal_clock != val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) emu->emu1010.internal_clock = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* 44100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Mute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Default fallback clock 48kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_44_1K );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* Word Clock source, Internal 44.1kHz x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) EMU_HANA_WCLOCK_INT_44_1K | EMU_HANA_WCLOCK_1X );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* Set LEDs on Audio Dock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) EMU_HANA_DOCK_LEDS_2_44K | EMU_HANA_DOCK_LEDS_2_LOCK );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Allow DLL to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Unmute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* 48000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* Mute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* Default fallback clock 48kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* Word Clock source, Internal 48kHz x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_1X );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Set LEDs on Audio Dock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) EMU_HANA_DOCK_LEDS_2_48K | EMU_HANA_DOCK_LEDS_2_LOCK );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* Allow DLL to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Unmute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) case 2: /* Take clock from S/PDIF IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Mute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Default fallback clock 48kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Word Clock source, sync to S/PDIF input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) EMU_HANA_WCLOCK_HANA_SPDIF_IN | EMU_HANA_WCLOCK_1X );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* Set LEDs on Audio Dock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_LOCK );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* FIXME: We should set EMU_HANA_DOCK_LEDS_2_LOCK only when clock signal is present and valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Allow DLL to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Unmute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Take clock from ADAT IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* Mute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* Default fallback clock 48kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* Word Clock source, sync to ADAT input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) EMU_HANA_WCLOCK_HANA_ADAT_IN | EMU_HANA_WCLOCK_1X );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Set LEDs on Audio Dock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_LOCK );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* FIXME: We should set EMU_HANA_DOCK_LEDS_2_LOCK only when clock signal is present and valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Allow DLL to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* Unmute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const struct snd_kcontrol_new snd_emu1010_internal_clock =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .name = "Clock Internal Rate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .info = snd_emu1010_internal_clock_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .get = snd_emu1010_internal_clock_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .put = snd_emu1010_internal_clock_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static int snd_emu1010_optical_out_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static const char * const texts[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) "SPDIF", "ADAT"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return snd_ctl_enum_info(uinfo, 1, 2, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int snd_emu1010_optical_out_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ucontrol->value.enumerated.item[0] = emu->emu1010.optical_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int snd_emu1010_optical_out_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) val = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* Limit: uinfo->value.enumerated.items = 2; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (val >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) change = (emu->emu1010.optical_out != val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) emu->emu1010.optical_out = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const struct snd_kcontrol_new snd_emu1010_optical_out = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .name = "Optical Output Mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .info = snd_emu1010_optical_out_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .get = snd_emu1010_optical_out_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .put = snd_emu1010_optical_out_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static int snd_emu1010_optical_in_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const char * const texts[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) "SPDIF", "ADAT"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return snd_ctl_enum_info(uinfo, 1, 2, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static int snd_emu1010_optical_in_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ucontrol->value.enumerated.item[0] = emu->emu1010.optical_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static int snd_emu1010_optical_in_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) val = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* Limit: uinfo->value.enumerated.items = 2; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (val >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) change = (emu->emu1010.optical_in != val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) emu->emu1010.optical_in = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static const struct snd_kcontrol_new snd_emu1010_optical_in = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .name = "Optical Input Mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .info = snd_emu1010_optical_in_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .get = snd_emu1010_optical_in_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .put = snd_emu1010_optical_in_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int snd_audigy_i2c_capture_source_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static const char * const texts[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) "Unknown1", "Unknown2", "Mic", "Line"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static const char * const texts[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) "Mic", "Line"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return snd_ctl_enum_info(uinfo, 1, 2, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static int snd_audigy_i2c_capture_source_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ucontrol->value.enumerated.item[0] = emu->i2c_capture_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static int snd_audigy_i2c_capture_source_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) unsigned int source_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) unsigned int ngain, ogain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) u32 gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) u32 source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* If the capture source has changed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * update the capture volume from the cached value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * for the particular source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) source_id = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* Limit: uinfo->value.enumerated.items = 2; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* emu->i2c_capture_volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (source_id >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) change = (emu->i2c_capture_source != source_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) snd_emu10k1_i2c_write(emu, ADC_MUX, 0); /* Mute input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) spin_lock_irqsave(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) gpio = inl(emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (source_id==0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) outl(gpio | 0x4, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) outl(gpio & ~0x4, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) spin_unlock_irqrestore(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ngain = emu->i2c_capture_volume[source_id][0]; /* Left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ogain = emu->i2c_capture_volume[emu->i2c_capture_source][0]; /* Left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (ngain != ogain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) snd_emu10k1_i2c_write(emu, ADC_ATTEN_ADCL, ((ngain) & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ngain = emu->i2c_capture_volume[source_id][1]; /* Right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ogain = emu->i2c_capture_volume[emu->i2c_capture_source][1]; /* Right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (ngain != ogain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) snd_emu10k1_i2c_write(emu, ADC_ATTEN_ADCR, ((ngain) & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) source = 1 << (source_id + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) snd_emu10k1_i2c_write(emu, ADC_MUX, source); /* Set source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) emu->i2c_capture_source = source_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static const struct snd_kcontrol_new snd_audigy_i2c_capture_source =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .name = "Capture Source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .info = snd_audigy_i2c_capture_source_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .get = snd_audigy_i2c_capture_source_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .put = snd_audigy_i2c_capture_source_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static int snd_audigy_i2c_volume_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) uinfo->value.integer.max = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int snd_audigy_i2c_volume_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) unsigned int source_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) source_id = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* Limit: emu->i2c_capture_volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* capture_source: uinfo->value.enumerated.items = 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (source_id >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ucontrol->value.integer.value[0] = emu->i2c_capture_volume[source_id][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ucontrol->value.integer.value[1] = emu->i2c_capture_volume[source_id][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static int snd_audigy_i2c_volume_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) unsigned int ogain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) unsigned int ngain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) unsigned int source_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) source_id = kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* Limit: emu->i2c_capture_volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* capture_source: uinfo->value.enumerated.items = 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (source_id >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ogain = emu->i2c_capture_volume[source_id][0]; /* Left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ngain = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (ngain > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (ogain != ngain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (emu->i2c_capture_source == source_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) snd_emu10k1_i2c_write(emu, ADC_ATTEN_ADCL, ((ngain) & 0xff) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) emu->i2c_capture_volume[source_id][0] = ngain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ogain = emu->i2c_capture_volume[source_id][1]; /* Right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ngain = ucontrol->value.integer.value[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (ngain > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (ogain != ngain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (emu->i2c_capture_source == source_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) snd_emu10k1_i2c_write(emu, ADC_ATTEN_ADCR, ((ngain) & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) emu->i2c_capture_volume[source_id][1] = ngain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define I2C_VOLUME(xname,chid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .info = snd_audigy_i2c_volume_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .get = snd_audigy_i2c_volume_get, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .put = snd_audigy_i2c_volume_put, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .tlv = { .p = snd_audigy_db_scale2 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .private_value = chid \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static const struct snd_kcontrol_new snd_audigy_i2c_volume_ctls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) I2C_VOLUME("Mic Capture Volume", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) I2C_VOLUME("Line Capture Volume", 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int snd_audigy_spdif_output_rate_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static const char * const texts[] = {"44100", "48000", "96000"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return snd_ctl_enum_info(uinfo, 1, 3, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static int snd_audigy_spdif_output_rate_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) switch (tmp & A_SPDIF_RATE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) case A_SPDIF_44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ucontrol->value.enumerated.item[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) case A_SPDIF_48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ucontrol->value.enumerated.item[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case A_SPDIF_96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ucontrol->value.enumerated.item[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ucontrol->value.enumerated.item[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static int snd_audigy_spdif_output_rate_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) unsigned int reg, val, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) switch(ucontrol->value.enumerated.item[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) val = A_SPDIF_44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) val = A_SPDIF_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) val = A_SPDIF_96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) val = A_SPDIF_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) reg = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) tmp = reg & ~A_SPDIF_RATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) tmp |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if ((change = (tmp != reg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static const struct snd_kcontrol_new snd_audigy_spdif_output_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .name = "Audigy SPDIF Output Sample Rate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .info = snd_audigy_spdif_output_rate_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .get = snd_audigy_spdif_output_rate_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .put = snd_audigy_spdif_output_rate_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static int snd_emu10k1_spdif_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* Limit: emu->spdif_bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (idx >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) val = (ucontrol->value.iec958.status[0] << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) (ucontrol->value.iec958.status[1] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) (ucontrol->value.iec958.status[2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) (ucontrol->value.iec958.status[3] << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) change = val != emu->spdif_bits[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) snd_emu10k1_ptr_write(emu, SPCS0 + idx, 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) emu->spdif_bits[idx] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static const struct snd_kcontrol_new snd_emu10k1_spdif_mask_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .count = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .info = snd_emu10k1_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .get = snd_emu10k1_spdif_get_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static const struct snd_kcontrol_new snd_emu10k1_spdif_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .count = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .info = snd_emu10k1_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .get = snd_emu10k1_spdif_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .put = snd_emu10k1_spdif_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static void update_emu10k1_fxrt(struct snd_emu10k1 *emu, int voice, unsigned char *route)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) snd_emu10k1_ptr_write(emu, A_FXRT1, voice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) snd_emu10k1_compose_audigy_fxrt1(route));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) snd_emu10k1_ptr_write(emu, A_FXRT2, voice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) snd_emu10k1_compose_audigy_fxrt2(route));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) snd_emu10k1_ptr_write(emu, FXRT, voice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) snd_emu10k1_compose_send_routing(route));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static void update_emu10k1_send_volume(struct snd_emu10k1 *emu, int voice, unsigned char *volume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) snd_emu10k1_ptr_write(emu, PTRX_FXSENDAMOUNT_A, voice, volume[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) snd_emu10k1_ptr_write(emu, PTRX_FXSENDAMOUNT_B, voice, volume[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) snd_emu10k1_ptr_write(emu, PSST_FXSENDAMOUNT_C, voice, volume[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) snd_emu10k1_ptr_write(emu, DSL_FXSENDAMOUNT_D, voice, volume[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) unsigned int val = ((unsigned int)volume[4] << 24) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ((unsigned int)volume[5] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ((unsigned int)volume[6] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) (unsigned int)volume[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, voice, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /* PCM stream controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static int snd_emu10k1_send_routing_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) uinfo->count = emu->audigy ? 3*8 : 3*4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) uinfo->value.integer.max = emu->audigy ? 0x3f : 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static int snd_emu10k1_send_routing_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct snd_emu10k1_pcm_mixer *mix =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) &emu->pcm_mixer[snd_ctl_get_ioffidx(kcontrol, &ucontrol->id)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) int voice, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) int num_efx = emu->audigy ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) int mask = emu->audigy ? 0x3f : 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) for (voice = 0; voice < 3; voice++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) for (idx = 0; idx < num_efx; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) ucontrol->value.integer.value[(voice * num_efx) + idx] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) mix->send_routing[voice][idx] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static int snd_emu10k1_send_routing_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) struct snd_emu10k1_pcm_mixer *mix =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) &emu->pcm_mixer[snd_ctl_get_ioffidx(kcontrol, &ucontrol->id)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) int change = 0, voice, idx, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) int num_efx = emu->audigy ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) int mask = emu->audigy ? 0x3f : 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) for (voice = 0; voice < 3; voice++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) for (idx = 0; idx < num_efx; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) val = ucontrol->value.integer.value[(voice * num_efx) + idx] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (mix->send_routing[voice][idx] != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) mix->send_routing[voice][idx] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (change && mix->epcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (mix->epcm->voices[0] && mix->epcm->voices[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) update_emu10k1_fxrt(emu, mix->epcm->voices[0]->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) &mix->send_routing[1][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) update_emu10k1_fxrt(emu, mix->epcm->voices[1]->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) &mix->send_routing[2][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) } else if (mix->epcm->voices[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) update_emu10k1_fxrt(emu, mix->epcm->voices[0]->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) &mix->send_routing[0][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) static const struct snd_kcontrol_new snd_emu10k1_send_routing_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .name = "EMU10K1 PCM Send Routing",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .count = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .info = snd_emu10k1_send_routing_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .get = snd_emu10k1_send_routing_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .put = snd_emu10k1_send_routing_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static int snd_emu10k1_send_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) uinfo->count = emu->audigy ? 3*8 : 3*4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) uinfo->value.integer.max = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static int snd_emu10k1_send_volume_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct snd_emu10k1_pcm_mixer *mix =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) &emu->pcm_mixer[snd_ctl_get_ioffidx(kcontrol, &ucontrol->id)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) int num_efx = emu->audigy ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) for (idx = 0; idx < 3*num_efx; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) ucontrol->value.integer.value[idx] = mix->send_volume[idx/num_efx][idx%num_efx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static int snd_emu10k1_send_volume_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct snd_emu10k1_pcm_mixer *mix =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) &emu->pcm_mixer[snd_ctl_get_ioffidx(kcontrol, &ucontrol->id)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) int change = 0, idx, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) int num_efx = emu->audigy ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) for (idx = 0; idx < 3*num_efx; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) val = ucontrol->value.integer.value[idx] & 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (mix->send_volume[idx/num_efx][idx%num_efx] != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) mix->send_volume[idx/num_efx][idx%num_efx] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (change && mix->epcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (mix->epcm->voices[0] && mix->epcm->voices[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) update_emu10k1_send_volume(emu, mix->epcm->voices[0]->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) &mix->send_volume[1][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) update_emu10k1_send_volume(emu, mix->epcm->voices[1]->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) &mix->send_volume[2][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) } else if (mix->epcm->voices[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) update_emu10k1_send_volume(emu, mix->epcm->voices[0]->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) &mix->send_volume[0][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static const struct snd_kcontrol_new snd_emu10k1_send_volume_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .name = "EMU10K1 PCM Send Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .count = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .info = snd_emu10k1_send_volume_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .get = snd_emu10k1_send_volume_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .put = snd_emu10k1_send_volume_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static int snd_emu10k1_attn_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) uinfo->count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) uinfo->value.integer.max = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static int snd_emu10k1_attn_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct snd_emu10k1_pcm_mixer *mix =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) &emu->pcm_mixer[snd_ctl_get_ioffidx(kcontrol, &ucontrol->id)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) for (idx = 0; idx < 3; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) ucontrol->value.integer.value[idx] = mix->attn[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static int snd_emu10k1_attn_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct snd_emu10k1_pcm_mixer *mix =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) &emu->pcm_mixer[snd_ctl_get_ioffidx(kcontrol, &ucontrol->id)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) int change = 0, idx, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) for (idx = 0; idx < 3; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) val = ucontrol->value.integer.value[idx] & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (mix->attn[idx] != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) mix->attn[idx] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (change && mix->epcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (mix->epcm->voices[0] && mix->epcm->voices[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) snd_emu10k1_ptr_write(emu, VTFT_VOLUMETARGET, mix->epcm->voices[0]->number, mix->attn[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) snd_emu10k1_ptr_write(emu, VTFT_VOLUMETARGET, mix->epcm->voices[1]->number, mix->attn[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) } else if (mix->epcm->voices[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) snd_emu10k1_ptr_write(emu, VTFT_VOLUMETARGET, mix->epcm->voices[0]->number, mix->attn[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static const struct snd_kcontrol_new snd_emu10k1_attn_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .name = "EMU10K1 PCM Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .count = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .info = snd_emu10k1_attn_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .get = snd_emu10k1_attn_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .put = snd_emu10k1_attn_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* Mutichannel PCM stream controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static int snd_emu10k1_efx_send_routing_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) uinfo->count = emu->audigy ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) uinfo->value.integer.max = emu->audigy ? 0x3f : 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static int snd_emu10k1_efx_send_routing_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) struct snd_emu10k1_pcm_mixer *mix =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) &emu->efx_pcm_mixer[snd_ctl_get_ioffidx(kcontrol, &ucontrol->id)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) int num_efx = emu->audigy ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) int mask = emu->audigy ? 0x3f : 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) for (idx = 0; idx < num_efx; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) ucontrol->value.integer.value[idx] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) mix->send_routing[0][idx] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static int snd_emu10k1_efx_send_routing_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) int ch = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) struct snd_emu10k1_pcm_mixer *mix = &emu->efx_pcm_mixer[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) int change = 0, idx, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) int num_efx = emu->audigy ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) int mask = emu->audigy ? 0x3f : 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) for (idx = 0; idx < num_efx; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) val = ucontrol->value.integer.value[idx] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (mix->send_routing[0][idx] != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) mix->send_routing[0][idx] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (change && mix->epcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (mix->epcm->voices[ch]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) update_emu10k1_fxrt(emu, mix->epcm->voices[ch]->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) &mix->send_routing[0][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static const struct snd_kcontrol_new snd_emu10k1_efx_send_routing_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .name = "Multichannel PCM Send Routing",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .count = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .info = snd_emu10k1_efx_send_routing_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .get = snd_emu10k1_efx_send_routing_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .put = snd_emu10k1_efx_send_routing_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static int snd_emu10k1_efx_send_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) uinfo->count = emu->audigy ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) uinfo->value.integer.max = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static int snd_emu10k1_efx_send_volume_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct snd_emu10k1_pcm_mixer *mix =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) &emu->efx_pcm_mixer[snd_ctl_get_ioffidx(kcontrol, &ucontrol->id)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) int num_efx = emu->audigy ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) for (idx = 0; idx < num_efx; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) ucontrol->value.integer.value[idx] = mix->send_volume[0][idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static int snd_emu10k1_efx_send_volume_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) int ch = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) struct snd_emu10k1_pcm_mixer *mix = &emu->efx_pcm_mixer[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) int change = 0, idx, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) int num_efx = emu->audigy ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) for (idx = 0; idx < num_efx; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) val = ucontrol->value.integer.value[idx] & 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (mix->send_volume[0][idx] != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) mix->send_volume[0][idx] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) if (change && mix->epcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) if (mix->epcm->voices[ch]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) update_emu10k1_send_volume(emu, mix->epcm->voices[ch]->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) &mix->send_volume[0][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static const struct snd_kcontrol_new snd_emu10k1_efx_send_volume_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .name = "Multichannel PCM Send Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .count = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .info = snd_emu10k1_efx_send_volume_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .get = snd_emu10k1_efx_send_volume_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .put = snd_emu10k1_efx_send_volume_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static int snd_emu10k1_efx_attn_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) uinfo->value.integer.max = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static int snd_emu10k1_efx_attn_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) struct snd_emu10k1_pcm_mixer *mix =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) &emu->efx_pcm_mixer[snd_ctl_get_ioffidx(kcontrol, &ucontrol->id)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) ucontrol->value.integer.value[0] = mix->attn[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static int snd_emu10k1_efx_attn_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) int ch = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) struct snd_emu10k1_pcm_mixer *mix = &emu->efx_pcm_mixer[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) int change = 0, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) val = ucontrol->value.integer.value[0] & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (mix->attn[0] != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) mix->attn[0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (change && mix->epcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (mix->epcm->voices[ch]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) snd_emu10k1_ptr_write(emu, VTFT_VOLUMETARGET, mix->epcm->voices[ch]->number, mix->attn[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) static const struct snd_kcontrol_new snd_emu10k1_efx_attn_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .name = "Multichannel PCM Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .count = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .info = snd_emu10k1_efx_attn_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .get = snd_emu10k1_efx_attn_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .put = snd_emu10k1_efx_attn_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define snd_emu10k1_shared_spdif_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) static int snd_emu10k1_shared_spdif_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) ucontrol->value.integer.value[0] = inl(emu->port + A_IOCFG) & A_IOCFG_GPOUT0 ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) ucontrol->value.integer.value[0] = inl(emu->port + HCFG) & HCFG_GPOUT0 ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (emu->card_capabilities->invert_shared_spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) ucontrol->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) !ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) static int snd_emu10k1_shared_spdif_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) unsigned int reg, val, sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) sw = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (emu->card_capabilities->invert_shared_spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) sw = !sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if ( emu->card_capabilities->i2c_adc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /* Do nothing for Audigy 2 ZS Notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) } else if (emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) reg = inl(emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) val = sw ? A_IOCFG_GPOUT0 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) change = (reg & A_IOCFG_GPOUT0) != val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if (change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) reg &= ~A_IOCFG_GPOUT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) reg |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) outl(reg | val, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) reg = inl(emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) val = sw ? HCFG_GPOUT0 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) change |= (reg & HCFG_GPOUT0) != val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) reg &= ~HCFG_GPOUT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) reg |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) outl(reg | val, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) static const struct snd_kcontrol_new snd_emu10k1_shared_spdif =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .name = "SB Live Analog/Digital Output Jack",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .info = snd_emu10k1_shared_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .get = snd_emu10k1_shared_spdif_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .put = snd_emu10k1_shared_spdif_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static const struct snd_kcontrol_new snd_audigy_shared_spdif =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .name = "Audigy Analog/Digital Output Jack",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .info = snd_emu10k1_shared_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .get = snd_emu10k1_shared_spdif_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .put = snd_emu10k1_shared_spdif_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) /* workaround for too low volume on Audigy due to 16bit/24bit conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) #define snd_audigy_capture_boost_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) static int snd_audigy_capture_boost_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /* FIXME: better to use a cached version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) val = snd_ac97_read(emu->ac97, AC97_REC_GAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ucontrol->value.integer.value[0] = !!val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static int snd_audigy_capture_boost_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (ucontrol->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) val = 0x0f0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return snd_ac97_update(emu->ac97, AC97_REC_GAIN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static const struct snd_kcontrol_new snd_audigy_capture_boost =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .name = "Mic Extra Boost",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .info = snd_audigy_capture_boost_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .get = snd_audigy_capture_boost_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .put = snd_audigy_capture_boost_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static void snd_emu10k1_mixer_free_ac97(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) struct snd_emu10k1 *emu = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) emu->ac97 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static int remove_ctl(struct snd_card *card, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) struct snd_ctl_elem_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) memset(&id, 0, sizeof(id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) strcpy(id.name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) return snd_ctl_remove_id(card, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static struct snd_kcontrol *ctl_find(struct snd_card *card, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) struct snd_ctl_elem_id sid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) memset(&sid, 0, sizeof(sid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) strcpy(sid.name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) sid.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) return snd_ctl_find_id(card, &sid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static int rename_ctl(struct snd_card *card, const char *src, const char *dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) struct snd_kcontrol *kctl = ctl_find(card, src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (kctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) strcpy(kctl->id.name, dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) int snd_emu10k1_mixer(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) int pcm_device, int multi_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) int err, pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) struct snd_card *card = emu->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) const char * const *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) static const char * const emu10k1_remove_ctls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /* no AC97 mono, surround, center/lfe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) "Master Mono Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) "Master Mono Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) "PCM Out Path & Mute",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) "Mono Output Select",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) "Surround Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) "Surround Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) "Center Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) "Center Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) "LFE Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) "LFE Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) static const char * const emu10k1_rename_ctls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) "Surround Digital Playback Volume", "Surround Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) "Center Digital Playback Volume", "Center Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) "LFE Digital Playback Volume", "LFE Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static const char * const audigy_remove_ctls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) /* Master/PCM controls on ac97 of Audigy has no effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) /* On the Audigy2 the AC97 playback is piped into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) * the Philips ADC for 24bit capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) "PCM Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) "PCM Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) "Master Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) "Master Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) "PCM Out Path & Mute",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) "Mono Output Select",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) /* remove unused AC97 capture controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) "Capture Source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) "Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) "Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) "Mic Select",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) "Headphone Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) "Headphone Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) "3D Control - Center",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) "3D Control - Depth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) "3D Control - Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) "Video Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) "Video Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) "Mic Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) "Mic Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) "External Amplifier",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) static const char * const audigy_rename_ctls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) /* use conventional names */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) "Wave Playback Volume", "PCM Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) /* "Wave Capture Volume", "PCM Capture Volume", */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) "Wave Master Playback Volume", "Master Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) "AMic Playback Volume", "Mic Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) "Master Mono Playback Switch", "Phone Output Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) "Master Mono Playback Volume", "Phone Output Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) static const char * const audigy_rename_ctls_i2c_adc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) //"Analog Mix Capture Volume","OLD Analog Mix Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) "Line Capture Volume", "Analog Mix Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) "Wave Playback Volume", "OLD PCM Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) "Wave Master Playback Volume", "Master Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) "AMic Playback Volume", "Old Mic Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) "CD Capture Volume", "IEC958 Optical Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) static const char * const audigy_remove_ctls_i2c_adc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) /* On the Audigy2 ZS Notebook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) * Capture via WM8775 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) "Mic Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) "Analog Mix Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) "Aux Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) "IEC958 Optical Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) static const char * const audigy_remove_ctls_1361t_adc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) /* On the Audigy2 the AC97 playback is piped into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) * the Philips ADC for 24bit capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) "PCM Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) "PCM Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) "Capture Source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) "Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) "Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) "Mic Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) "Headphone Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) "Headphone Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) "3D Control - Center",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) "3D Control - Depth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) "3D Control - Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) "Line2 Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) "Line2 Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) static const char * const audigy_rename_ctls_1361t_adc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) "Master Playback Switch", "Master Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) "Master Playback Volume", "Master Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) "Wave Master Playback Volume", "Master Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) "Beep Playback Switch", "Beep Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) "Beep Playback Volume", "Beep Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) "Phone Playback Switch", "Phone Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) "Phone Playback Volume", "Phone Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) "Mic Playback Switch", "Mic Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) "Mic Playback Volume", "Mic Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) "Line Playback Switch", "Line Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) "Line Playback Volume", "Line Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) "CD Playback Switch", "CD Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) "CD Playback Volume", "CD Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) "Aux Playback Switch", "Aux Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) "Aux Playback Volume", "Aux Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) "Video Playback Switch", "Video Capture Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) "Video Playback Volume", "Video Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) "Master Mono Playback Switch", "Phone Output Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) "Master Mono Playback Volume", "Phone Output Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) if (emu->card_capabilities->ac97_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) struct snd_ac97_bus *pbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) struct snd_ac97_template ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static const struct snd_ac97_bus_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .write = snd_emu10k1_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .read = snd_emu10k1_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if ((err = snd_ac97_bus(emu->card, 0, &ops, NULL, &pbus)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) pbus->no_vra = 1; /* we don't need VRA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) ac97.private_data = emu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) ac97.private_free = snd_emu10k1_mixer_free_ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ac97.scaps = AC97_SCAP_NO_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) if ((err = snd_ac97_mixer(pbus, &ac97, &emu->ac97)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (emu->card_capabilities->ac97_chip == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) dev_info(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) "AC97 is optional on this board\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) dev_info(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) "Proceeding without ac97 mixers...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) snd_device_free(emu->card, pbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) goto no_ac97; /* FIXME: get rid of ugly gotos.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) if (emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) /* set master volume to 0 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) snd_ac97_write_cache(emu->ac97, AC97_MASTER, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) /* set capture source to mic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) snd_ac97_write_cache(emu->ac97, AC97_REC_SEL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /* set mono output (TAD) to mic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) snd_ac97_update_bits(emu->ac97, AC97_GENERAL_PURPOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) 0x0200, 0x0200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) if (emu->card_capabilities->adc_1361t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) c = audigy_remove_ctls_1361t_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) c = audigy_remove_ctls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) * Credits for cards based on STAC9758:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) * James Courtier-Dutton <James@superbug.demon.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) * Voluspa <voluspa@comhem.se>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) if (emu->ac97->id == AC97_ID_STAC9758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) emu->rear_ac97 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE|AC97SLOT_REAR_LEFT|AC97SLOT_REAR_RIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) snd_ac97_write_cache(emu->ac97, AC97_HEADPHONE, 0x0202);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) remove_ctl(card,"Front Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) remove_ctl(card,"Front Playback Switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) /* remove unused AC97 controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) snd_ac97_write_cache(emu->ac97, AC97_SURROUND_MASTER, 0x0202);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) snd_ac97_write_cache(emu->ac97, AC97_CENTER_LFE_MASTER, 0x0202);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) c = emu10k1_remove_ctls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) for (; *c; c++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) remove_ctl(card, *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) } else if (emu->card_capabilities->i2c_adc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) c = audigy_remove_ctls_i2c_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) for (; *c; c++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) remove_ctl(card, *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) no_ac97:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (emu->card_capabilities->ecard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) strcpy(emu->card->mixername, "EMU APS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) else if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) strcpy(emu->card->mixername, "SB Audigy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) strcpy(emu->card->mixername, "Emu10k1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) if (emu->card_capabilities->adc_1361t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) c = audigy_rename_ctls_1361t_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) else if (emu->card_capabilities->i2c_adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) c = audigy_rename_ctls_i2c_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) c = audigy_rename_ctls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) c = emu10k1_rename_ctls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) for (; *c; c += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) rename_ctl(card, c[0], c[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (emu->card_capabilities->subsystem == 0x80401102) { /* SB Live! Platinum CT4760P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) remove_ctl(card, "Center Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) remove_ctl(card, "LFE Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) remove_ctl(card, "Wave Center Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) remove_ctl(card, "Wave LFE Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (emu->card_capabilities->subsystem == 0x20071102) { /* Audigy 4 Pro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) rename_ctl(card, "Line2 Capture Volume", "Line1/Mic Capture Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) rename_ctl(card, "Analog Mix Capture Volume", "Line2 Capture Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) rename_ctl(card, "Aux2 Capture Volume", "Line3 Capture Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) rename_ctl(card, "Mic Capture Volume", "Unknown1 Capture Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if ((kctl = emu->ctl_send_routing = snd_ctl_new1(&snd_emu10k1_send_routing_control, emu)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) kctl->id.device = pcm_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) if ((err = snd_ctl_add(card, kctl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) if ((kctl = emu->ctl_send_volume = snd_ctl_new1(&snd_emu10k1_send_volume_control, emu)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) kctl->id.device = pcm_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if ((err = snd_ctl_add(card, kctl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) if ((kctl = emu->ctl_attn = snd_ctl_new1(&snd_emu10k1_attn_control, emu)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) kctl->id.device = pcm_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if ((err = snd_ctl_add(card, kctl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if ((kctl = emu->ctl_efx_send_routing = snd_ctl_new1(&snd_emu10k1_efx_send_routing_control, emu)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) kctl->id.device = multi_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) if ((err = snd_ctl_add(card, kctl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) if ((kctl = emu->ctl_efx_send_volume = snd_ctl_new1(&snd_emu10k1_efx_send_volume_control, emu)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) kctl->id.device = multi_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) if ((err = snd_ctl_add(card, kctl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if ((kctl = emu->ctl_efx_attn = snd_ctl_new1(&snd_emu10k1_efx_attn_control, emu)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) kctl->id.device = multi_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) if ((err = snd_ctl_add(card, kctl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) /* initialize the routing and volume table for each pcm playback stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) for (pcm = 0; pcm < 32; pcm++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) struct snd_emu10k1_pcm_mixer *mix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) mix = &emu->pcm_mixer[pcm];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) mix->epcm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) for (v = 0; v < 4; v++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) mix->send_routing[0][v] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) mix->send_routing[1][v] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) mix->send_routing[2][v] = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) memset(&mix->send_volume, 0, sizeof(mix->send_volume));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) mix->send_volume[0][0] = mix->send_volume[0][1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) mix->send_volume[1][0] = mix->send_volume[2][1] = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) mix->attn[0] = mix->attn[1] = mix->attn[2] = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) /* initialize the routing and volume table for the multichannel playback stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) for (pcm = 0; pcm < NUM_EFX_PLAYBACK; pcm++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) struct snd_emu10k1_pcm_mixer *mix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) mix = &emu->efx_pcm_mixer[pcm];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) mix->epcm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) mix->send_routing[0][0] = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) mix->send_routing[0][1] = (pcm == 0) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) for (v = 0; v < 2; v++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) mix->send_routing[0][2+v] = 13+v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) for (v = 0; v < 4; v++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) mix->send_routing[0][4+v] = 60+v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) memset(&mix->send_volume, 0, sizeof(mix->send_volume));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) mix->send_volume[0][0] = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) mix->attn[0] = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) if (! emu->card_capabilities->ecard) { /* FIXME: APS has these controls? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) /* sb live! and audigy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if ((kctl = snd_ctl_new1(&snd_emu10k1_spdif_mask_control, emu)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (!emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) kctl->id.device = emu->pcm_efx->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if ((err = snd_ctl_add(card, kctl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) if ((kctl = snd_ctl_new1(&snd_emu10k1_spdif_control, emu)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) if (!emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) kctl->id.device = emu->pcm_efx->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) if ((err = snd_ctl_add(card, kctl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) if (emu->card_capabilities->emu_model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) ; /* Disable the snd_audigy_spdif_shared_spdif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) } else if (emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) if ((kctl = snd_ctl_new1(&snd_audigy_shared_spdif, emu)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) if ((err = snd_ctl_add(card, kctl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) if ((kctl = snd_ctl_new1(&snd_audigy_spdif_output_rate, emu)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) if ((err = snd_ctl_add(card, kctl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) } else if (! emu->card_capabilities->ecard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) /* sb live! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) if ((kctl = snd_ctl_new1(&snd_emu10k1_shared_spdif, emu)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) if ((err = snd_ctl_add(card, kctl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if (emu->card_capabilities->ca0151_chip) { /* P16V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if ((err = snd_p16v_mixer(emu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) /* 1616(m) cardbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) for (i = 0; i < ARRAY_SIZE(snd_emu1616_output_enum_ctls); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) snd_ctl_new1(&snd_emu1616_output_enum_ctls[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) for (i = 0; i < ARRAY_SIZE(snd_emu1010_input_enum_ctls); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) snd_ctl_new1(&snd_emu1010_input_enum_ctls[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) for (i = 0; i < ARRAY_SIZE(snd_emu1010_adc_pads) - 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) snd_ctl_new1(&snd_emu1010_adc_pads[i], emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) for (i = 0; i < ARRAY_SIZE(snd_emu1010_dac_pads) - 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) snd_ctl_new1(&snd_emu1010_dac_pads[i], emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) snd_ctl_new1(&snd_emu1010_internal_clock, emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) snd_ctl_new1(&snd_emu1010_optical_out, emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) snd_ctl_new1(&snd_emu1010_optical_in, emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) } else if (emu->card_capabilities->emu_model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) /* all other e-mu cards for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) for (i = 0; i < ARRAY_SIZE(snd_emu1010_output_enum_ctls); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) snd_ctl_new1(&snd_emu1010_output_enum_ctls[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) for (i = 0; i < ARRAY_SIZE(snd_emu1010_input_enum_ctls); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) snd_ctl_new1(&snd_emu1010_input_enum_ctls[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) for (i = 0; i < ARRAY_SIZE(snd_emu1010_adc_pads); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) snd_ctl_new1(&snd_emu1010_adc_pads[i], emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) for (i = 0; i < ARRAY_SIZE(snd_emu1010_dac_pads); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) snd_ctl_new1(&snd_emu1010_dac_pads[i], emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) snd_ctl_new1(&snd_emu1010_internal_clock, emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) snd_ctl_new1(&snd_emu1010_optical_out, emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) snd_ctl_new1(&snd_emu1010_optical_in, emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if ( emu->card_capabilities->i2c_adc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) err = snd_ctl_add(card, snd_ctl_new1(&snd_audigy_i2c_capture_source, emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) for (i = 0; i < ARRAY_SIZE(snd_audigy_i2c_volume_ctls); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) err = snd_ctl_add(card, snd_ctl_new1(&snd_audigy_i2c_volume_ctls[i], emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) if (emu->card_capabilities->ac97_chip && emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) err = snd_ctl_add(card, snd_ctl_new1(&snd_audigy_capture_boost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) emu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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