^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Creative Labs, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Routines for effect processor FX8010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Added EMU 1010 support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * BUGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/capability.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/nospec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <sound/emu10k1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #if 0 /* for testing purposes - digital out -> capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EMU10K1_CAPTURE_DIGITAL_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #if 0 /* for testing purposes - set S/PDIF to AC3 output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EMU10K1_SET_AC3_IEC958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EMU10K1_CENTER_LFE_FROM_FRONT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static bool high_res_gpr_volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) module_param(high_res_gpr_volume, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const char * const fxbuses[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* 0x00 */ "PCM Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* 0x01 */ "PCM Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* 0x02 */ "PCM Surround Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* 0x03 */ "PCM Surround Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* 0x04 */ "MIDI Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* 0x05 */ "MIDI Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* 0x06 */ "Center",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* 0x07 */ "LFE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* 0x08 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* 0x09 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* 0x0a */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* 0x0b */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* 0x0c */ "MIDI Reverb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* 0x0d */ "MIDI Chorus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* 0x0e */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* 0x0f */ NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const char * const creative_ins[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* 0x00 */ "AC97 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* 0x01 */ "AC97 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* 0x02 */ "TTL IEC958 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* 0x03 */ "TTL IEC958 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* 0x04 */ "Zoom Video Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* 0x05 */ "Zoom Video Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* 0x06 */ "Optical IEC958 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* 0x07 */ "Optical IEC958 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* 0x08 */ "Line/Mic 1 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* 0x09 */ "Line/Mic 1 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* 0x0a */ "Coaxial IEC958 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* 0x0b */ "Coaxial IEC958 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* 0x0c */ "Line/Mic 2 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* 0x0d */ "Line/Mic 2 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* 0x0e */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* 0x0f */ NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const char * const audigy_ins[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* 0x00 */ "AC97 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* 0x01 */ "AC97 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* 0x02 */ "Audigy CD Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* 0x03 */ "Audigy CD Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* 0x04 */ "Optical IEC958 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* 0x05 */ "Optical IEC958 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* 0x06 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* 0x07 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* 0x08 */ "Line/Mic 2 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* 0x09 */ "Line/Mic 2 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* 0x0a */ "SPDIF Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* 0x0b */ "SPDIF Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* 0x0c */ "Aux2 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* 0x0d */ "Aux2 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* 0x0e */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* 0x0f */ NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const char * const creative_outs[32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* 0x00 */ "AC97 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* 0x01 */ "AC97 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* 0x02 */ "Optical IEC958 Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* 0x03 */ "Optical IEC958 Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* 0x04 */ "Center",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* 0x05 */ "LFE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* 0x06 */ "Headphone Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* 0x07 */ "Headphone Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* 0x08 */ "Surround Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* 0x09 */ "Surround Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* 0x0a */ "PCM Capture Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* 0x0b */ "PCM Capture Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* 0x0c */ "MIC Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* 0x0d */ "AC97 Surround Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* 0x0e */ "AC97 Surround Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* 0x0f */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* 0x10 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* 0x11 */ "Analog Center",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* 0x12 */ "Analog LFE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* 0x13 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* 0x14 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* 0x15 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* 0x16 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* 0x17 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* 0x18 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* 0x19 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* 0x1a */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* 0x1b */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* 0x1c */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* 0x1d */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* 0x1e */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* 0x1f */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const char * const audigy_outs[32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* 0x00 */ "Digital Front Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* 0x01 */ "Digital Front Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* 0x02 */ "Digital Center",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* 0x03 */ "Digital LEF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* 0x04 */ "Headphone Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* 0x05 */ "Headphone Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* 0x06 */ "Digital Rear Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* 0x07 */ "Digital Rear Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* 0x08 */ "Front Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* 0x09 */ "Front Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* 0x0a */ "Center",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* 0x0b */ "LFE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* 0x0c */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* 0x0d */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* 0x0e */ "Rear Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* 0x0f */ "Rear Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* 0x10 */ "AC97 Front Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* 0x11 */ "AC97 Front Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* 0x12 */ "ADC Capture Left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* 0x13 */ "ADC Capture Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* 0x14 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* 0x15 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* 0x16 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* 0x17 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* 0x18 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* 0x19 */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* 0x1a */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* 0x1b */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* 0x1c */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* 0x1d */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* 0x1e */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* 0x1f */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const u32 bass_table[41][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const u32 treble_table[41][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const u32 db_table[101] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0x7fffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* EMU10k1/EMU10k2 DSP control db gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* EMU10K1 bass/treble db gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const u32 onoff_table[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0x00000000, 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct snd_emu10k1_fx8010_ctl *ctl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ctl->min == 0 && ctl->max == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) uinfo->count = ctl->vcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) uinfo->value.integer.min = ctl->min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) uinfo->value.integer.max = ctl->max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct snd_emu10k1_fx8010_ctl *ctl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) for (i = 0; i < ctl->vcount; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ucontrol->value.integer.value[i] = ctl->value[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct snd_emu10k1_fx8010_ctl *ctl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned int nval, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) spin_lock_irqsave(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) for (i = 0; i < ctl->vcount; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) nval = ucontrol->value.integer.value[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (nval < ctl->min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) nval = ctl->min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (nval > ctl->max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) nval = ctl->max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (nval != ctl->value[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) val = ctl->value[i] = nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) switch (ctl->translation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case EMU10K1_GPR_TRANSLATION_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case EMU10K1_GPR_TRANSLATION_TABLE100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case EMU10K1_GPR_TRANSLATION_BASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) change = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) for (j = 0; j < 5; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case EMU10K1_GPR_TRANSLATION_TREBLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) change = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) for (j = 0; j < 5; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case EMU10K1_GPR_TRANSLATION_ONOFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) __error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) spin_unlock_irqrestore(&emu->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct snd_emu10k1_fx8010_irq *irq, *nirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) irq = emu->fx8010.irq_handlers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) while (irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) nirq = irq->next; /* irq ptr can be removed from list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (irq->handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) irq->handler(emu, irq->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) irq = nirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) snd_fx8010_irq_handler_t *handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned char gpr_running,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) void *private_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct snd_emu10k1_fx8010_irq *irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) irq->handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) irq->gpr_running = gpr_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) irq->private_data = private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) irq->next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (emu->fx8010.irq_handlers == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) emu->fx8010.irq_handlers = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) irq->next = emu->fx8010.irq_handlers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) emu->fx8010.irq_handlers = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct snd_emu10k1_fx8010_irq *irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct snd_emu10k1_fx8010_irq *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if ((tmp = emu->fx8010.irq_handlers) == irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) emu->fx8010.irq_handlers = tmp->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (emu->fx8010.irq_handlers == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) emu->dsp_interrupt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) while (tmp && tmp->next != irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) tmp = tmp->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) tmp->next = tmp->next->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * EMU10K1 effect manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned int *ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 op, u32 r, u32 a, u32 x, u32 y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u_int32_t *code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (snd_BUG_ON(*ptr >= 512))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) code = icode->code + (*ptr) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) set_bit(*ptr, icode->code_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) (*ptr)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define OP(icode, ptr, op, r, a, x, y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) snd_emu10k1_write_op(icode, ptr, op, r, a, x, y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unsigned int *ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 op, u32 r, u32 a, u32 x, u32 y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u_int32_t *code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (snd_BUG_ON(*ptr >= 1024))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) code = icode->code + (*ptr) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) set_bit(*ptr, icode->code_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) (*ptr)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define A_OP(icode, ptr, op, r, a, x, y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) snd_emu10k1_ptr_write(emu, pc, 0, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return snd_emu10k1_ptr_read(emu, pc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct snd_emu10k1_fx8010_code *icode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) bool in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (!test_bit(gpr, icode->gpr_valid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) val = icode->gpr_map[gpr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) else if (get_user(val, (__user u32 *)&icode->gpr_map[gpr]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct snd_emu10k1_fx8010_code *icode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) set_bit(gpr, icode->gpr_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (put_user(val, (__user u32 *)&icode->gpr_map[gpr]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct snd_emu10k1_fx8010_code *icode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) bool in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int tram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 addr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (!test_bit(tram, icode->tram_valid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (in_kernel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) val = icode->tram_data_map[tram];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) addr = icode->tram_addr_map[tram];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (get_user(val, (__user __u32 *)&icode->tram_data_map[tram]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) get_user(addr, (__user __u32 *)&icode->tram_addr_map[tram]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (!emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct snd_emu10k1_fx8010_code *icode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int tram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 val, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) memset(icode->tram_valid, 0, sizeof(icode->tram_valid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) set_bit(tram, icode->tram_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (!emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (put_user(val, (__user u32 *)&icode->tram_data_map[tram]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) put_user(addr, (__user u32 *)&icode->tram_addr_map[tram]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct snd_emu10k1_fx8010_code *icode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) bool in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 pc, lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (!test_bit(pc / 2, icode->code_valid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (in_kernel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) lo = icode->code[pc + 0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) hi = icode->code[pc + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (get_user(lo, (__user u32 *)&icode->code[pc + 0]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) get_user(hi, (__user u32 *)&icode->code[pc + 1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) snd_emu10k1_efx_write(emu, pc + 0, lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) snd_emu10k1_efx_write(emu, pc + 1, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct snd_emu10k1_fx8010_code *icode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) memset(icode->code_valid, 0, sizeof(icode->code_valid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) set_bit(pc / 2, icode->code_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (put_user(snd_emu10k1_efx_read(emu, pc + 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) (__user u32 *)&icode->code[pc + 0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (put_user(snd_emu10k1_efx_read(emu, pc + 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) (__user u32 *)&icode->code[pc + 1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static struct snd_emu10k1_fx8010_ctl *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct emu10k1_ctl_elem_id *_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct snd_ctl_elem_id *id = (struct snd_ctl_elem_id *)_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct snd_emu10k1_fx8010_ctl *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct snd_kcontrol *kcontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) kcontrol = ctl->kcontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (kcontrol->id.iface == id->iface &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) !strcmp(kcontrol->id.name, id->name) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) kcontrol->id.index == id->index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define MAX_TLV_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static unsigned int *copy_tlv(const unsigned int __user *_tlv, bool in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) unsigned int data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) unsigned int *tlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (!_tlv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) memcpy(data, (__force void *)_tlv, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) else if (copy_from_user(data, _tlv, sizeof(data)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (data[1] >= MAX_TLV_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (!tlv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) memcpy(tlv, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (in_kernel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) memcpy(tlv + 2, (__force void *)(_tlv + 2), data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) } else if (copy_from_user(tlv + 2, _tlv + 2, data[1])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) kfree(tlv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return tlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int copy_gctl(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct snd_emu10k1_fx8010_control_gpr *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct snd_emu10k1_fx8010_control_gpr *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int idx, bool in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct snd_emu10k1_fx8010_control_gpr __user *_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct snd_emu10k1_fx8010_control_old_gpr *octl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct snd_emu10k1_fx8010_control_old_gpr __user *_octl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) _src = (struct snd_emu10k1_fx8010_control_gpr __user *)src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (emu->support_tlv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) *dst = src[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) else if (copy_from_user(dst, &_src[idx], sizeof(*src)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) octl = (struct snd_emu10k1_fx8010_control_old_gpr *)src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) _octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)octl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) memcpy(dst, &octl[idx], sizeof(*octl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) else if (copy_from_user(dst, &_octl[idx], sizeof(*octl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dst->tlv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int copy_gctl_to_user(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct snd_emu10k1_fx8010_control_gpr *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct snd_emu10k1_fx8010_control_gpr *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct snd_emu10k1_fx8010_control_gpr __user *_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) _dst = (struct snd_emu10k1_fx8010_control_gpr __user *)dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (emu->support_tlv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return copy_to_user(&_dst[idx], src, sizeof(*src));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return copy_to_user(&octl[idx], src, sizeof(*octl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int copy_ctl_elem_id(const struct emu10k1_ctl_elem_id *list, int i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct emu10k1_ctl_elem_id *ret, bool in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct emu10k1_ctl_elem_id __user *_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) (struct emu10k1_ctl_elem_id __user *)&list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) *ret = list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) else if (copy_from_user(ret, _id, sizeof(*ret)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct snd_emu10k1_fx8010_code *icode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) bool in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct emu10k1_ctl_elem_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct snd_emu10k1_fx8010_control_gpr *gctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct snd_ctl_elem_id *gctl_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) for (i = 0; i < icode->gpr_del_control_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) in_kernel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (snd_emu10k1_look_for_ctl(emu, &id) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (! gctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) for (i = 0; i < icode->gpr_add_control_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) in_kernel)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) err = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (snd_emu10k1_look_for_ctl(emu, &gctl->id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) gctl_id = (struct snd_ctl_elem_id *)&gctl->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) down_read(&emu->card->controls_rwsem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (snd_ctl_find_id(emu->card, gctl_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) up_read(&emu->card->controls_rwsem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) err = -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) up_read(&emu->card->controls_rwsem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) for (i = 0; i < icode->gpr_list_control_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* FIXME: we need to check the WRITE access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (copy_gctl(emu, gctl, icode->gpr_list_controls, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) in_kernel)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) err = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) __error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) kfree(gctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct snd_emu10k1_fx8010_ctl *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) kctl->private_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) list_del(&ctl->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) kfree(ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) kfree(kctl->tlv.p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct snd_emu10k1_fx8010_code *icode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) bool in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct snd_emu10k1_fx8010_control_gpr *gctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct snd_ctl_elem_id *gctl_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct snd_emu10k1_fx8010_ctl *ctl, *nctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct snd_kcontrol_new knew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct snd_ctl_elem_value *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) val = kmalloc(sizeof(*val), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) nctl = kmalloc(sizeof(*nctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (!val || !gctl || !nctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) for (i = 0; i < icode->gpr_add_control_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) in_kernel)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) err = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) gctl_id = (struct snd_ctl_elem_id *)&gctl->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (!*gctl_id->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) memset(&knew, 0, sizeof(knew));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) knew.iface = gctl_id->iface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) knew.name = gctl_id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) knew.index = gctl_id->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) knew.device = gctl_id->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) knew.subdevice = gctl_id->subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) knew.info = snd_emu10k1_gpr_ctl_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) knew.tlv.p = copy_tlv((const unsigned int __user *)gctl->tlv, in_kernel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (knew.tlv.p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) SNDRV_CTL_ELEM_ACCESS_TLV_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) knew.get = snd_emu10k1_gpr_ctl_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) knew.put = snd_emu10k1_gpr_ctl_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) memset(nctl, 0, sizeof(*nctl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) nctl->vcount = gctl->vcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) nctl->count = gctl->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) for (j = 0; j < 32; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) nctl->gpr[j] = gctl->gpr[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) val->value.integer.value[j] = gctl->value[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) nctl->min = gctl->min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) nctl->max = gctl->max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) nctl->translation = gctl->translation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (ctl == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ctl = kmalloc(sizeof(*ctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (ctl == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) kfree(knew.tlv.p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) knew.private_value = (unsigned long)ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) *ctl = *nctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if ((err = snd_ctl_add(emu->card, kctl = snd_ctl_new1(&knew, emu))) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) kfree(ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) kfree(knew.tlv.p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) kctl->private_free = snd_emu10k1_ctl_private_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ctl->kcontrol = kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* overwrite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) nctl->list = ctl->list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) nctl->kcontrol = ctl->kcontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) *ctl = *nctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) __error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) kfree(nctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) kfree(gctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) kfree(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct snd_emu10k1_fx8010_code *icode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) bool in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct emu10k1_ctl_elem_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct snd_emu10k1_fx8010_ctl *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct snd_card *card = emu->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) for (i = 0; i < icode->gpr_del_control_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) in_kernel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) down_write(&card->controls_rwsem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ctl = snd_emu10k1_look_for_ctl(emu, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) snd_ctl_remove(card, ctl->kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) up_write(&card->controls_rwsem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct snd_emu10k1_fx8010_code *icode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) unsigned int i = 0, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) unsigned int total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct snd_emu10k1_fx8010_control_gpr *gctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct snd_emu10k1_fx8010_ctl *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct snd_ctl_elem_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (! gctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) total++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (icode->gpr_list_controls &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) i < icode->gpr_list_control_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) memset(gctl, 0, sizeof(*gctl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) id = &ctl->kcontrol->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) gctl->id.iface = (__force int)id->iface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) strlcpy(gctl->id.name, id->name, sizeof(gctl->id.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) gctl->id.index = id->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) gctl->id.device = id->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) gctl->id.subdevice = id->subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) gctl->vcount = ctl->vcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) gctl->count = ctl->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) for (j = 0; j < 32; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) gctl->gpr[j] = ctl->gpr[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) gctl->value[j] = ctl->value[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) gctl->min = ctl->min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) gctl->max = ctl->max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) gctl->translation = ctl->translation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (copy_gctl_to_user(emu, icode->gpr_list_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) gctl, i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) kfree(gctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) icode->gpr_list_control_total = total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) kfree(gctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct snd_emu10k1_fx8010_code *icode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) bool in_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) mutex_lock(&emu->fx8010.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) err = snd_emu10k1_verify_controls(emu, icode, in_kernel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) strlcpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* stop FX processor - this may be dangerous, but it's better to miss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) some samples than generate wrong ones - [jk] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* ok, do the main job */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) err = snd_emu10k1_del_controls(emu, icode, in_kernel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) err = snd_emu10k1_gpr_poke(emu, icode, in_kernel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) err = snd_emu10k1_tram_poke(emu, icode, in_kernel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) err = snd_emu10k1_code_poke(emu, icode, in_kernel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) err = snd_emu10k1_add_controls(emu, icode, in_kernel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* start FX processor when the DSP code is updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) __error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) mutex_unlock(&emu->fx8010.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct snd_emu10k1_fx8010_code *icode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) mutex_lock(&emu->fx8010.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) strlcpy(icode->name, emu->fx8010.name, sizeof(icode->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* ok, do the main job */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) err = snd_emu10k1_gpr_peek(emu, icode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (err >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) err = snd_emu10k1_tram_peek(emu, icode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (err >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) err = snd_emu10k1_code_peek(emu, icode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (err >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) err = snd_emu10k1_list_controls(emu, icode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) mutex_unlock(&emu->fx8010.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct snd_emu10k1_fx8010_pcm_rec *ipcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct snd_emu10k1_fx8010_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ipcm->substream = array_index_nospec(ipcm->substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) EMU10K1_FX8010_PCM_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (ipcm->channels > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) pcm = &emu->fx8010.pcm[ipcm->substream];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) mutex_lock(&emu->fx8010.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) spin_lock_irq(&emu->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (pcm->opened) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (ipcm->channels == 0) { /* remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) pcm->valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* FIXME: we need to add universal code to the PCM transfer routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (ipcm->channels != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) goto __error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) pcm->valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) pcm->opened = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) pcm->channels = ipcm->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) pcm->tram_start = ipcm->tram_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) pcm->buffer_size = ipcm->buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) pcm->gpr_size = ipcm->gpr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) pcm->gpr_count = ipcm->gpr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) pcm->gpr_tmpcount = ipcm->gpr_tmpcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) pcm->gpr_ptr = ipcm->gpr_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) pcm->gpr_trigger = ipcm->gpr_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) pcm->gpr_running = ipcm->gpr_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) for (i = 0; i < pcm->channels; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) pcm->etram[i] = ipcm->etram[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) __error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) spin_unlock_irq(&emu->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) mutex_unlock(&emu->fx8010.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct snd_emu10k1_fx8010_pcm_rec *ipcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct snd_emu10k1_fx8010_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ipcm->substream = array_index_nospec(ipcm->substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) EMU10K1_FX8010_PCM_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) pcm = &emu->fx8010.pcm[ipcm->substream];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) mutex_lock(&emu->fx8010.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) spin_lock_irq(&emu->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ipcm->channels = pcm->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ipcm->tram_start = pcm->tram_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ipcm->buffer_size = pcm->buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ipcm->gpr_size = pcm->gpr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ipcm->gpr_ptr = pcm->gpr_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ipcm->gpr_count = pcm->gpr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ipcm->gpr_tmpcount = pcm->gpr_tmpcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ipcm->gpr_trigger = pcm->gpr_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ipcm->gpr_running = pcm->gpr_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) for (i = 0; i < pcm->channels; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) ipcm->etram[i] = pcm->etram[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ipcm->res1 = ipcm->res2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) ipcm->pad = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) spin_unlock_irq(&emu->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) mutex_unlock(&emu->fx8010.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define SND_EMU10K1_GPR_CONTROLS 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define SND_EMU10K1_INPUTS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define SND_EMU10K1_PLAYBACK_CHANNELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define SND_EMU10K1_CAPTURE_CHANNELS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) snd_emu10k1_init_mono_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) const char *name, int gpr, int defval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) strcpy(ctl->id.name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ctl->vcount = ctl->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (high_res_gpr_volume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ctl->min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ctl->max = 0x7fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ctl->tlv = snd_emu10k1_db_linear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ctl->min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ctl->max = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ctl->tlv = snd_emu10k1_db_scale1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) snd_emu10k1_init_stereo_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) const char *name, int gpr, int defval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) strcpy(ctl->id.name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ctl->vcount = ctl->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (high_res_gpr_volume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ctl->min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ctl->max = 0x7fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ctl->tlv = snd_emu10k1_db_linear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) ctl->min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ctl->max = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ctl->tlv = snd_emu10k1_db_scale1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) const char *name, int gpr, int defval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) strcpy(ctl->id.name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ctl->vcount = ctl->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ctl->min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ctl->max = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) const char *name, int gpr, int defval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) strcpy(ctl->id.name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ctl->vcount = ctl->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ctl->min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ctl->max = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * Used for emu1010 - conversion from 32-bit capture inputs from HANA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * to 2 x 16-bit registers in audigy - their values are read via DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * Conversion is performed by Audigy DSP instructions of FX8010.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static int snd_emu10k1_audigy_dsp_convert_32_to_2x16(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct snd_emu10k1_fx8010_code *icode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) u32 *ptr, int tmp, int bit_shifter16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) int reg_in, int reg_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) A_OP(icode, ptr, iACC3, A_GPR(tmp + 1), reg_in, A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp + 1), A_GPR(bit_shifter16 - 1), A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) A_OP(icode, ptr, iTSTNEG, A_GPR(tmp + 2), A_GPR(tmp), A_C_80000000, A_GPR(bit_shifter16 - 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) A_OP(icode, ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_C_80000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp), A_GPR(bit_shifter16 - 3), A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) A_OP(icode, ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A_GPR(tmp), A_C_00010000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) A_OP(icode, ptr, iANDXOR, reg_out, A_GPR(tmp), A_C_ffffffff, A_GPR(tmp + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) A_OP(icode, ptr, iACC3, reg_out + 1, A_GPR(tmp + 1), A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * initial DSP configuration for Audigy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) int err, i, z, gpr, nctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) int bit_shifter16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) const int playback = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) const int capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); /* we reserve 10 voices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) const int stereo_mix = capture + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) const int tmp = 0x88;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) u32 ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct snd_emu10k1_fx8010_code *icode = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) u32 *gpr_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) icode = kzalloc(sizeof(*icode), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (!icode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) icode->gpr_map = kcalloc(512 + 256 + 256 + 2 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) sizeof(u_int32_t), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (!icode->gpr_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) goto __err_gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) sizeof(*controls), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (!controls)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) goto __err_ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) gpr_map = icode->gpr_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) icode->tram_data_map = icode->gpr_map + 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) icode->tram_addr_map = icode->tram_data_map + 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) icode->code = icode->tram_addr_map + 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /* clear free GPRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) for (i = 0; i < 512; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) set_bit(i, icode->gpr_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /* clear TRAM data & address lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) for (i = 0; i < 256; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) set_bit(i, icode->tram_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) strcpy(icode->name, "Audigy DSP code for ALSA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) nctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) gpr = stereo_mix + 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) gpr_map[gpr++] = 0x00007fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) gpr_map[gpr++] = 0x00008000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) gpr_map[gpr++] = 0x0000ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) bit_shifter16 = gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* stop FX processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) snd_emu10k1_ptr_write(emu, A_DBG, 0, (emu->fx8010.dbg = 0) | A_DBG_SINGLE_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* PCM front Playback Volume (independent from stereo mix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * playback = 0 + ( gpr * FXBUS_PCM_LEFT_FRONT >> 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * where gpr contains attenuation from corresponding mixer control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * (snd_emu10k1_init_stereo_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* PCM Surround Playback (independent from stereo mix) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* PCM Side Playback (independent from stereo mix) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (emu->card_capabilities->spk71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* PCM Center Playback (independent from stereo mix) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) gpr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /* PCM LFE Playback (independent from stereo mix) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) gpr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * Stereo Mix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /* Wave (PCM) Playback Volume (will be renamed later) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* Synth Playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /* Wave (PCM) Capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* Synth Capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define A_ADD_VOLUME_IN(var,vol,input) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* emu1212 DSP 0 and DSP 1 Capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (emu->card_capabilities->emu_model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (emu->card_capabilities->ca0108_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* Note:JCD:No longer bit shift lower 16bits to upper 16bits of 32bit value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x0), A_C_00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_GPR(tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x1), A_C_00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr), A_GPR(tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_P16VIN(0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_P16VIN(0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* AC'97 Playback Volume - used only for mic (renamed later) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* AC'97 Capture Volume - used only for mic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* mic capture buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), 0xcd, A_EXTIN(A_EXTIN_AC97_R));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /* Audigy CD Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) snd_emu10k1_init_stereo_control(&controls[nctl++],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* Audigy CD Capture Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) snd_emu10k1_init_stereo_control(&controls[nctl++],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* Optical SPDIF Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /* Optical SPDIF Capture Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* Line2 Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) snd_emu10k1_init_stereo_control(&controls[nctl++],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /* Line2 Capture Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) snd_emu10k1_init_stereo_control(&controls[nctl++],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /* Philips ADC Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /* Philips ADC Capture Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* Aux2 Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) snd_emu10k1_init_stereo_control(&controls[nctl++],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* Aux2 Capture Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) snd_emu10k1_init_stereo_control(&controls[nctl++],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /* Stereo Mix Front Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /* Stereo Mix Surround Playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /* Stereo Mix Center Playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* Center = sub = Left/2 + Right/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), 0xcd, A_GPR(stereo_mix+1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) gpr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /* Stereo Mix LFE Playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) gpr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (emu->card_capabilities->spk71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* Stereo Mix Side Playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #define A_PUT_STEREO_OUTPUT(out1,out2,src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define _A_SWITCH(icode, ptr, dst, src, sw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #define A_SWITCH(icode, ptr, dst, src, sw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #define _A_SWITCH_NEG(icode, ptr, dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define A_SWITCH_NEG(icode, ptr, dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) * Process tone control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), A_GPR(playback + 0), A_C_00000000, A_C_00000000); /* left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), A_GPR(playback + 1), A_C_00000000, A_C_00000000); /* right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), A_GPR(playback + 2), A_C_00000000, A_C_00000000); /* rear left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), A_GPR(playback + 3), A_C_00000000, A_C_00000000); /* rear right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), A_GPR(playback + 4), A_C_00000000, A_C_00000000); /* center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), A_GPR(playback + 5), A_C_00000000, A_C_00000000); /* LFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (emu->card_capabilities->spk71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 6), A_GPR(playback + 6), A_C_00000000, A_C_00000000); /* side left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 7), A_GPR(playback + 7), A_C_00000000, A_C_00000000); /* side right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ctl = &controls[nctl + 0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) strcpy(ctl->id.name, "Tone Control - Bass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) ctl->vcount = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) ctl->count = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) ctl->min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) ctl->max = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) ctl->value[0] = ctl->value[1] = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) ctl = &controls[nctl + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) strcpy(ctl->id.name, "Tone Control - Treble");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) ctl->vcount = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) ctl->count = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) ctl->min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) ctl->max = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) ctl->value[0] = ctl->value[1] = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define BASS_GPR 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define TREBLE_GPR 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) for (z = 0; z < 5; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) for (j = 0; j < 2; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) controls[nctl + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) controls[nctl + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) int j, k, l, d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) for (j = 0; j < 2; j++) { /* left/right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) k = 0xb0 + (z * 8) + (j * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) l = 0xe0 + (z * 8) + (j * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(BASS_GPR + 0 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(BASS_GPR + 4 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(BASS_GPR + 2 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(BASS_GPR + 8 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(BASS_GPR + 6 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(TREBLE_GPR + 0 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(TREBLE_GPR + 4 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(TREBLE_GPR + 2 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(TREBLE_GPR + 8 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(TREBLE_GPR + 6 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (z == 2) /* center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) nctl += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #undef BASS_GPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #undef TREBLE_GPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) for (z = 0; z < 8; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) A_SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) snd_emu10k1_init_stereo_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* Master volume (will be renamed later) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) A_OP(icode, &ptr, iMAC0, A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) A_OP(icode, &ptr, iMAC0, A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) A_OP(icode, &ptr, iMAC0, A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) A_OP(icode, &ptr, iMAC0, A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) A_OP(icode, &ptr, iMAC0, A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) A_OP(icode, &ptr, iMAC0, A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) A_OP(icode, &ptr, iMAC0, A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) A_OP(icode, &ptr, iMAC0, A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /* analog speakers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) if (emu->card_capabilities->spk71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6 + SND_EMU10K1_PLAYBACK_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) /* headphone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) /* digital outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* A_PUT_STEREO_OUTPUT(A_EXTOUT_FRONT_L, A_EXTOUT_FRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (emu->card_capabilities->emu_model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) dev_info(emu->card->dev, "EMU outputs on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) for (z = 0; z < 8; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (emu->card_capabilities->ca0108_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) /* IEC958 Optical Raw Playback Switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) gpr_map[gpr++] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) gpr_map[gpr++] = 0x1008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) gpr_map[gpr++] = 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) for (z = 0; z < 2; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) A_SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if ((z==1) && (emu->card_capabilities->spdif_bug)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) dev_info(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) "Installing spdif_bug patch: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) emu->card_capabilities->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /* ADC buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (emu->card_capabilities->emu_model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (emu->card_capabilities->ca0108_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) dev_info(emu->card->dev, "EMU2 inputs on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) for (z = 0; z < 0x10; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) bit_shifter16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) A3_EMU32IN(z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) A_FXBUS2(z*2) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) dev_info(emu->card->dev, "EMU inputs on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /* Capture 16 (originally 8) channels of S32_LE sound */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) gpr, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) /* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) /* A_P16VIN(0) is delayed by one sample,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) * so all other A_P16VIN channels will need to also be delayed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* Left ADC in. 1 of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) /* Right ADC in 1 of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) /* Delaying by one sample: instead of copying the input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * value A_P16VIN to output A_FXBUS2 as in the first channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * we use an auxiliary register, delaying the value by one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) * sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(4) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x2), A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(6) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x3), A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) /* For 96kHz mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /* Left ADC in. 2 of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0x8) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x4), A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) /* Right ADC in 2 of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xa) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x5), A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xc) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x6), A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /* Pavel Hofman - we still have voices, A_FXBUS2s, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) * A_P16VINs available -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) * let's add 8 more capture channels - total of 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) bit_shifter16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) A_GPR(gpr - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) A_FXBUS2(0x10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) bit_shifter16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) A_GPR(gpr - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) A_FXBUS2(0x12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) bit_shifter16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) A_GPR(gpr - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) A_FXBUS2(0x14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) bit_shifter16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) A_GPR(gpr - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) A_FXBUS2(0x16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) bit_shifter16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) A_GPR(gpr - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) A_FXBUS2(0x18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) bit_shifter16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) A_GPR(gpr - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) A_FXBUS2(0x1a));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) bit_shifter16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) A_GPR(gpr - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) A_FXBUS2(0x1c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) gpr_map[gpr++] = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) bit_shifter16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) A_GPR(gpr - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) A_FXBUS2(0x1e));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) for (z = 4; z < 8; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) for (z = 0xc; z < 0x10; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* EFX capture - capture the 16 EXTINs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) /* Capture 16 channels of S16_LE sound */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) for (z = 0; z < 16; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) #endif /* JCD test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) * ok, set up done..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) if (gpr > tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) goto __err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) /* clear remaining instruction memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) while (ptr < 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) icode->gpr_add_control_count = nctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) icode->gpr_add_controls = controls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) emu->support_tlv = 1; /* support TLV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) err = snd_emu10k1_icode_poke(emu, icode, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) emu->support_tlv = 0; /* clear again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) __err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) kfree(controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) __err_ctrls:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) kfree(icode->gpr_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) __err_gpr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) kfree(icode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) * initial DSP configuration for Emu10k1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) /* when volume = max, then copy only to avoid volume modification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) /* with iMAC0 (negative values) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) OP(icode, ptr, iMACINT0, dst, dst, src, C_00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) OP(icode, ptr, iMAC0, dst, dst, src, vol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) static void _volume_out(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) #define VOLUME(icode, ptr, dst, src, vol) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) #define VOLUME_IN(icode, ptr, dst, src, vol) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) #define VOLUME_ADD(icode, ptr, dst, src, vol) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) #define VOLUME_OUT(icode, ptr, dst, src, vol) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) _volume_out(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) #define _SWITCH(icode, ptr, dst, src, sw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #define SWITCH(icode, ptr, dst, src, sw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #define SWITCH_IN(icode, ptr, dst, src, sw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) #define _SWITCH_NEG(icode, ptr, dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #define SWITCH_NEG(icode, ptr, dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) int err, i, z, gpr, tmp, playback, capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) u32 ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) struct snd_emu10k1_fx8010_code *icode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) u32 *gpr_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) icode = kzalloc(sizeof(*icode), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if (!icode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) icode->gpr_map = kcalloc(256 + 160 + 160 + 2 * 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) sizeof(u_int32_t), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (!icode->gpr_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) goto __err_gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) sizeof(struct snd_emu10k1_fx8010_control_gpr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (!controls)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) goto __err_ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (!ipcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) goto __err_ipcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) gpr_map = icode->gpr_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) icode->tram_data_map = icode->gpr_map + 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) icode->tram_addr_map = icode->tram_data_map + 160;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) icode->code = icode->tram_addr_map + 160;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) /* clear free GPRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) for (i = 0; i < 256; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) set_bit(i, icode->gpr_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) /* clear TRAM data & address lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) for (i = 0; i < 160; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) set_bit(i, icode->tram_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) ptr = 0; i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) /* we have 12 inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) playback = SND_EMU10K1_INPUTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) /* we have 6 playback channels and tone control doubles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) tmp = 0x88; /* we need 4 temporary GPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) /* from 0x8c to 0xff is the area for tone control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) /* stop FX processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) snd_emu10k1_ptr_write(emu, DBG, 0, (emu->fx8010.dbg = 0) | EMU10K1_DBG_SINGLE_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) * Process FX Buses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) /* Raw S/PDIF PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ipcm->substream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) ipcm->channels = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) ipcm->tram_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) ipcm->buffer_size = (64 * 1024) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) ipcm->gpr_size = gpr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) ipcm->gpr_ptr = gpr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) ipcm->gpr_count = gpr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) ipcm->gpr_tmpcount = gpr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) ipcm->gpr_trigger = gpr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) ipcm->gpr_running = gpr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) ipcm->etram[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) ipcm->etram[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) gpr_map[gpr + 0] = 0xfffff000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) gpr_map[gpr + 1] = 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) gpr_map[gpr + 2] = 0x70000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) gpr_map[gpr + 3] = 0x00000007;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) gpr_map[gpr + 4] = 0x001f << 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) gpr_map[gpr + 5] = 0x001c << 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) gpr_map[gpr + 8] = 0x2000000 + (2<<11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) gpr_map[gpr + 9] = 0x4000000 + (2<<11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) gpr_map[gpr + 10] = 1<<11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) gpr_map[gpr + 12] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) /* if the trigger flag is not set, skip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) /* if the running flag is set, we're running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) /* 24: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) gpr += 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) /* Wave Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) VOLUME(icode, &ptr, playback + z, z, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) /* Wave Surround Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) /* Wave Center/LFE Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) /* Wave Capture Volume + Switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) for (z = 0; z < 2; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) gpr += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) /* Synth Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) /* Synth Capture Volume + Switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) for (z = 0; z < 2; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) gpr += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) /* Surround Digital Playback Volume (renamed later without Digital) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) /* Surround Capture Volume + Switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) for (z = 0; z < 2; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) gpr += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) /* Center Playback Volume (renamed later without Digital) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) /* LFE Playback Volume + Switch (renamed later without Digital) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) /* Front Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) /* Front Capture Volume + Switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) for (z = 0; z < 2; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) gpr += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) * Process inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) /* AC'97 Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) /* AC'97 Capture Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) /* IEC958 TTL Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) /* IEC958 TTL Capture Volume + Switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) for (z = 0; z < 2; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) gpr += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) /* Zoom Video Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) /* Zoom Video Capture Volume + Switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) for (z = 0; z < 2; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) gpr += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) /* IEC958 Optical Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) /* IEC958 Optical Capture Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) for (z = 0; z < 2; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) gpr += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) /* Line LiveDrive Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) /* Line LiveDrive Capture Volume + Switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) for (z = 0; z < 2; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) gpr += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) /* IEC958 Coax Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) /* IEC958 Coax Capture Volume + Switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) for (z = 0; z < 2; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) gpr += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) /* Line LiveDrive Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) controls[i-1].id.index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) /* Line LiveDrive Capture Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) for (z = 0; z < 2; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) controls[i-1].id.index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) controls[i-1].id.index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) gpr += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) * Process tone control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), GPR(playback + 0), C_00000000, C_00000000); /* left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), GPR(playback + 1), C_00000000, C_00000000); /* right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), GPR(playback + 2), C_00000000, C_00000000); /* rear left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), GPR(playback + 3), C_00000000, C_00000000); /* rear right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), GPR(playback + 4), C_00000000, C_00000000); /* center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), GPR(playback + 5), C_00000000, C_00000000); /* LFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) ctl = &controls[i + 0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) strcpy(ctl->id.name, "Tone Control - Bass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) ctl->vcount = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) ctl->count = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) ctl->min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) ctl->max = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) ctl->value[0] = ctl->value[1] = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) ctl->tlv = snd_emu10k1_bass_treble_db_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) ctl = &controls[i + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) strcpy(ctl->id.name, "Tone Control - Treble");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) ctl->vcount = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) ctl->count = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) ctl->min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) ctl->max = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) ctl->value[0] = ctl->value[1] = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) ctl->tlv = snd_emu10k1_bass_treble_db_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) #define BASS_GPR 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) #define TREBLE_GPR 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) for (z = 0; z < 5; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) for (j = 0; j < 2; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) for (z = 0; z < 3; z++) { /* front/rear/center-lfe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) int j, k, l, d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) for (j = 0; j < 2; j++) { /* left/right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) k = 0xa0 + (z * 8) + (j * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) l = 0xd0 + (z * 8) + (j * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) if (z == 2) /* center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) i += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) #undef BASS_GPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) #undef TREBLE_GPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) for (z = 0; z < 6; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) snd_emu10k1_init_stereo_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) * Process outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) /* AC'97 Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) /* IEC958 Optical Raw Playback Switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) for (z = 0; z < 2; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) gpr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) /* Headphone Playback Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) for (z = 0; z < 2; z++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4 + z, gpr + 2 + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) controls[i-1].id.index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) controls[i-1].id.index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) gpr += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) #ifndef EMU10K1_CAPTURE_DIGITAL_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) for (z = 0; z < 2; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) /* EFX capture - capture the 16 EXTINS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) if (emu->card_capabilities->sblive51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) /* On the Live! 5.1, FXBUS2(1) and FXBUS(2) are shared with EXTOUT_ACENTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) * and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) * Since only 14 of the 16 EXTINs are used, this is not a big problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) * We route AC97L and R to FX capture 14 and 15, SPDIF CD in to FX capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) * 0 and 3, then the rest of the EXTINs to the corresponding FX capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) * channel. Multitrack recorders will still see the center/lfe output signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) * on the second and third channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) OP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) OP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) OP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) OP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) for (z = 4; z < 14; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) for (z = 0; z < 16; z++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) if (gpr > tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) goto __err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) if (i > SND_EMU10K1_GPR_CONTROLS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) goto __err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) /* clear remaining instruction memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) while (ptr < 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) if ((err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) goto __err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) icode->gpr_add_control_count = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) icode->gpr_add_controls = controls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) emu->support_tlv = 1; /* support TLV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) err = snd_emu10k1_icode_poke(emu, icode, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) emu->support_tlv = 0; /* clear again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) if (err >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) err = snd_emu10k1_ipcm_poke(emu, ipcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) __err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) kfree(ipcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) __err_ipcm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) kfree(controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) __err_ctrls:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) kfree(icode->gpr_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) __err_gpr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) kfree(icode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) int snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) spin_lock_init(&emu->fx8010.irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) INIT_LIST_HEAD(&emu->fx8010.gpr_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) return _snd_emu10k1_audigy_init_efx(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) return _snd_emu10k1_init_efx(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) void snd_emu10k1_free_efx(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) /* stop processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) #if 0 /* FIXME: who use them? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) if (output < 0 || output >= 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) if (output < 0 || output >= 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) u8 size_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) /* size is in samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) if (size != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) size = (size - 1) >> 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) while (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) size >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) size_reg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) size = 0x2000 << size_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) if ((emu->fx8010.etram_pages.bytes / 2) == size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) spin_lock_irq(&emu->emu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) spin_unlock_irq(&emu->emu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) snd_emu10k1_ptr_write(emu, TCB, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) snd_emu10k1_ptr_write(emu, TCBS, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) if (emu->fx8010.etram_pages.area != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) snd_dma_free_pages(&emu->fx8010.etram_pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) emu->fx8010.etram_pages.area = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) emu->fx8010.etram_pages.bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) if (size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &emu->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) size * 2, &emu->fx8010.etram_pages) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) memset(emu->fx8010.etram_pages.area, 0, size * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) spin_lock_irq(&emu->emu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) spin_unlock_irq(&emu->emu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) static void copy_string(char *dst, const char *src, const char *null, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) if (src == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) sprintf(dst, "%s %02X", null, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) strcpy(dst, src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) struct snd_emu10k1_fx8010_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) const char * const *fxbus, * const *extin, * const *extout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) unsigned short fxbus_mask, extin_mask, extout_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) info->internal_tram_size = emu->fx8010.itram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) info->external_tram_size = emu->fx8010.etram_pages.bytes / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) fxbus = fxbuses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) extin = emu->audigy ? audigy_ins : creative_ins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) extout = emu->audigy ? audigy_outs : creative_outs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) fxbus_mask = emu->fx8010.fxbus_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) extin_mask = emu->fx8010.extin_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) extout_mask = emu->fx8010.extout_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) for (res = 0; res < 16; res++, fxbus++, extin++, extout++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) copy_string(info->fxbus_names[res], fxbus_mask & (1 << res) ? *fxbus : NULL, "FXBUS", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) for (res = 16; res < 32; res++, extout++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) info->gpr_controls = emu->fx8010.gpr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) struct snd_emu10k1 *emu = hw->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) struct snd_emu10k1_fx8010_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) struct snd_emu10k1_fx8010_code *icode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) struct snd_emu10k1_fx8010_pcm_rec *ipcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) void __user *argp = (void __user *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) case SNDRV_EMU10K1_IOCTL_PVERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) emu->support_tlv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) case SNDRV_EMU10K1_IOCTL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) info = kzalloc(sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) snd_emu10k1_fx8010_info(emu, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) if (copy_to_user(argp, info, sizeof(*info))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) case SNDRV_EMU10K1_IOCTL_CODE_POKE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) if (!capable(CAP_SYS_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) icode = memdup_user(argp, sizeof(*icode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) if (IS_ERR(icode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) return PTR_ERR(icode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) res = snd_emu10k1_icode_poke(emu, icode, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) kfree(icode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) case SNDRV_EMU10K1_IOCTL_CODE_PEEK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) icode = memdup_user(argp, sizeof(*icode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) if (IS_ERR(icode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) return PTR_ERR(icode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) res = snd_emu10k1_icode_peek(emu, icode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) kfree(icode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) kfree(icode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) case SNDRV_EMU10K1_IOCTL_PCM_POKE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) ipcm = memdup_user(argp, sizeof(*ipcm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) if (IS_ERR(ipcm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) return PTR_ERR(ipcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) res = snd_emu10k1_ipcm_poke(emu, ipcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) kfree(ipcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) case SNDRV_EMU10K1_IOCTL_PCM_PEEK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) ipcm = memdup_user(argp, sizeof(*ipcm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) if (IS_ERR(ipcm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) return PTR_ERR(ipcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) res = snd_emu10k1_ipcm_peek(emu, ipcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) kfree(ipcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) kfree(ipcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) case SNDRV_EMU10K1_IOCTL_TRAM_SETUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) if (!capable(CAP_SYS_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) if (get_user(addr, (unsigned int __user *)argp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) mutex_lock(&emu->fx8010.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) res = snd_emu10k1_fx8010_tram_setup(emu, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) mutex_unlock(&emu->fx8010.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) case SNDRV_EMU10K1_IOCTL_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) if (!capable(CAP_SYS_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) case SNDRV_EMU10K1_IOCTL_CONTINUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) if (!capable(CAP_SYS_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) if (!capable(CAP_SYS_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) case SNDRV_EMU10K1_IOCTL_SINGLE_STEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) if (!capable(CAP_SYS_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) if (get_user(addr, (unsigned int __user *)argp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) if (addr > 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | A_DBG_STEP_ADDR | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | EMU10K1_DBG_STEP | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) case SNDRV_EMU10K1_IOCTL_DBG_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) addr = snd_emu10k1_ptr_read(emu, A_DBG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) addr = snd_emu10k1_ptr_read(emu, DBG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) if (put_user(addr, (unsigned int __user *)argp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) struct snd_hwdep *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) if ((err = snd_hwdep_new(emu->card, "FX8010", device, &hw)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) strcpy(hw->name, "EMU10K1 (FX8010)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) hw->iface = SNDRV_HWDEP_IFACE_EMU10K1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) hw->ops.open = snd_emu10k1_fx8010_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) hw->ops.ioctl = snd_emu10k1_fx8010_ioctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) hw->ops.release = snd_emu10k1_fx8010_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) hw->private_data = emu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) len = emu->audigy ? 0x200 : 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) emu->saved_gpr = kmalloc_array(len, 4, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) if (! emu->saved_gpr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) len = emu->audigy ? 0x100 : 0xa0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) emu->tram_val_saved = kmalloc_array(len, 4, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) emu->tram_addr_saved = kmalloc_array(len, 4, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) if (! emu->tram_val_saved || ! emu->tram_addr_saved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) len = emu->audigy ? 2 * 1024 : 2 * 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) emu->saved_icode = vmalloc(array_size(len, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) if (! emu->saved_icode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) kfree(emu->saved_gpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) kfree(emu->tram_val_saved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) kfree(emu->tram_addr_saved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) vfree(emu->saved_icode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) * save/restore GPR, TRAM and codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) int i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) len = emu->audigy ? 0x200 : 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) len = emu->audigy ? 0x100 : 0xa0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) if (emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) emu->tram_addr_saved[i] >>= 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) emu->tram_addr_saved[i] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) len = emu->audigy ? 2 * 1024 : 2 * 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) int i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) /* set up TRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) if (emu->fx8010.etram_pages.bytes > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) unsigned size, size_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) size = emu->fx8010.etram_pages.bytes / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) size = (size - 1) >> 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) while (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) size >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) size_reg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) len = emu->audigy ? 0x200 : 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) len = emu->audigy ? 0x100 : 0xa0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) emu->tram_val_saved[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) if (! emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) emu->tram_addr_saved[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) emu->tram_addr_saved[i] << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) emu->tram_addr_saved[i] >> 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) len = emu->audigy ? 2 * 1024 : 2 * 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) /* start FX processor when the DSP code is updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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