^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Creative Labs, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Routines for control of EMU10K1 chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Added support for Audigy 2 Value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Added EMU 1010 support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * General bug fixes and enhancements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * BUGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <sound/emu10k1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "p16v.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "tina2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "p17v.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HANA_FILENAME "emu/hana.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DOCK_FILENAME "emu/audio_dock.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EMU1010B_FILENAME "emu/emu1010b.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MICRO_DOCK_FILENAME "emu/micro_dock.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EMU0404_FILENAME "emu/emu0404.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EMU1010_NOTEBOOK_FILENAME "emu/emu1010_notebook.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MODULE_FIRMWARE(HANA_FILENAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MODULE_FIRMWARE(DOCK_FILENAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MODULE_FIRMWARE(EMU1010B_FILENAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MODULE_FIRMWARE(MICRO_DOCK_FILENAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MODULE_FIRMWARE(EMU0404_FILENAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MODULE_FIRMWARE(EMU1010_NOTEBOOK_FILENAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * EMU10K1 init / done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void snd_emu10k1_voice_init(struct snd_emu10k1 *emu, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) snd_emu10k1_ptr_write(emu, IP, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) snd_emu10k1_ptr_write(emu, CPF, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) snd_emu10k1_ptr_write(emu, CCR, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) snd_emu10k1_ptr_write(emu, PSST, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) snd_emu10k1_ptr_write(emu, DSL, ch, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) snd_emu10k1_ptr_write(emu, CCCA, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) snd_emu10k1_ptr_write(emu, Z1, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) snd_emu10k1_ptr_write(emu, Z2, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) snd_emu10k1_ptr_write(emu, PEFE, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) snd_emu10k1_ptr_write(emu, FMMOD, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24); /* 1 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*** these are last so OFF prevents writing ***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Audigy extra stuffs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const unsigned int spi_dac_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0x00ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0x02ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0x0520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0x08ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 0x0aff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 0x0cff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0x0eff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 0x10ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0x1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0x1400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 0x1480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 0x1800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 0x1aff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0x1cff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0x1e00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x0530,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0x0602,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0x0622,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x1400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const unsigned int i2c_adc_init[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { 0x17, 0x00 }, /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { 0x07, 0x00 }, /* Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 0x0b, 0x22 }, /* Interface control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { 0x0c, 0x22 }, /* Master mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { 0x0d, 0x08 }, /* Powerdown control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { 0x0e, 0xcf }, /* Attenuation Left 0x01 = -103dB, 0xff = 24dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 0x0f, 0xcf }, /* Attenuation Right 0.5dB steps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 0x10, 0x7b }, /* ALC Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 0x11, 0x00 }, /* ALC Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { 0x12, 0x32 }, /* ALC Control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { 0x13, 0x00 }, /* Noise gate control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { 0x14, 0xa6 }, /* Limiter control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { 0x15, ADC_MUX_2 }, /* ADC Mixer control. Mic for A2ZS Notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir, int resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int silent_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* disable audio and lock cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* reset recording buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* disable channel interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) outl(0, emu->port + INTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* set SPDIF bypass mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) snd_emu10k1_ptr_write(emu, SPBYPASS, 0, SPBYPASS_FORMAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* enable rear left + rear right AC97 slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_REAR_RIGHT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) AC97SLOT_REAR_LEFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* init envelope engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) for (ch = 0; ch < NUM_G; ch++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) snd_emu10k1_voice_init(emu, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) snd_emu10k1_ptr_write(emu, SPCS0, 0, emu->spdif_bits[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) snd_emu10k1_ptr_write(emu, SPCS1, 0, emu->spdif_bits[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) snd_emu10k1_ptr_write(emu, SPCS2, 0, emu->spdif_bits[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Hacks for Alice3 to work independent of haP16V driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Setup SRCMulti_I2S SamplingRate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) tmp &= 0xfffff1ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) tmp |= (0x2<<9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) snd_emu10k1_ptr20_write(emu, SRCSel, 0, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Setup SRCMulti Input Audio Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Use 0xFFFFFFFF to enable P16V sounds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) snd_emu10k1_ptr20_write(emu, SRCMULTI_ENABLE, 0, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Enabled Phased (8-channel) P16V playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) outl(0x0201, emu->port + HCFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Set playback routing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, 0x78e4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (emu->card_capabilities->ca0108_chip) { /* audigy2 Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Hacks for Alice3 to work independent of haP16V driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_info(emu->card->dev, "Audigy2 value: Special config.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Setup SRCMulti_I2S SamplingRate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) tmp &= 0xfffff1ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) tmp |= (0x2<<9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) outl(0x600000, emu->port + 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) outl(0x14, emu->port + 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Setup SRCMulti Input Audio Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) outl(0x7b0000, emu->port + 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) outl(0xFF000000, emu->port + 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Setup SPDIF Out Audio Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* The Audigy 2 Value has a separate SPDIF out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * so no need for a mixer switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) outl(0x7a0000, emu->port + 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) outl(0xFF000000, emu->port + 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tmp = inl(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) outl(tmp, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (emu->card_capabilities->spi_dac) { /* Audigy 2 ZS Notebook with DAC Wolfson WM8768/WM8568 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int size, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) size = ARRAY_SIZE(spi_dac_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) for (n = 0; n < size; n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) snd_emu10k1_spi_write(emu, spi_dac_init[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) snd_emu10k1_ptr20_write(emu, 0x60, 0, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Enable GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * GPIO0: Unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * GPIO1: Speakers-enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * GPIO2: Unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * GPIO3: Unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * GPIO4: IEC958 Output on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * GPIO5: Unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * GPIO6: Unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * GPIO7: Unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) outl(0x76, emu->port + A_IOCFG); /* Windows uses 0x3f76 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (emu->card_capabilities->i2c_adc) { /* Audigy 2 ZS Notebook with ADC Wolfson WM8775 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int size, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) snd_emu10k1_ptr20_write(emu, P17V_I2S_SRC_SEL, 0, 0x2020205f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) tmp = inl(emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) outl(tmp | 0x4, emu->port + A_IOCFG); /* Set bit 2 for mic input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) tmp = inl(emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) size = ARRAY_SIZE(i2c_adc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) for (n = 0; n < size; n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) snd_emu10k1_i2c_write(emu, i2c_adc_init[n][0], i2c_adc_init[n][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for (n = 0; n < 4; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) emu->i2c_capture_volume[n][0] = 0xcf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) emu->i2c_capture_volume[n][1] = 0xcf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) silent_page = (emu->silent_page.addr << emu->address_mode) | (emu->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) for (ch = 0; ch < NUM_G; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (emu->card_capabilities->emu_model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) outl(HCFG_AUTOMUTE_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) HCFG_EMU32_SLAVE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) HCFG_AUDIOENABLE, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Hokay, setup HCFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * Mute Disable Audio = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Lock Tank Memory = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Lock Sound Memory = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * Auto Mute = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) } else if (emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (emu->revision == 4) /* audigy2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) outl(HCFG_AUDIOENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) HCFG_AC3ENABLE_CDSPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) HCFG_AC3ENABLE_GPSPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* FIXME: Remove all these emu->model and replace it with a card recognition parameter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * e.g. card_capabilities->joystick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) } else if (emu->model == 0x20 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) emu->model == 0xc400 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (emu->model == 0x21 && emu->revision < 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* With on-chip joystick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (enable_ir) { /* enable IR for SB Live */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (emu->card_capabilities->emu_model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ; /* Disable all access to A_IOCFG for the emu1010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) } else if (emu->card_capabilities->i2c_adc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) } else if (emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int reg = inl(emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) outl(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) udelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) outl(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) outl(reg, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int reg = inl(emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) outl(reg | HCFG_GPOUT2, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) udelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) outl(reg, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (emu->card_capabilities->emu_model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ; /* Disable all access to A_IOCFG for the emu1010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) } else if (emu->card_capabilities->i2c_adc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } else if (emu->audigy) { /* enable analog output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int reg = inl(emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) outl(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (emu->address_mode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* use 16M in 4G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) outl(inl(emu->port + HCFG) | HCFG_EXPANDED_MEM, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void snd_emu10k1_audio_enable(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Enable the audio bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Enable analog/digital outs on audigy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (emu->card_capabilities->emu_model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ; /* Disable all access to A_IOCFG for the emu1010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) } else if (emu->card_capabilities->i2c_adc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) } else if (emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Unmute Analog now. Set GPO6 to 1 for Apollo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * This has to be done after init ALice3 I2SOut beyond 48KHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * So, sequence is important. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Unmute Analog now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) outl(inl(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Disable routing from AC97 line out to Front speakers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) outl(inl(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* FIXME: the following routine disables LiveDrive-II !! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* TOSLink detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) emu->tos_link = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) tmp = inl(emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) outl(tmp|0x800, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (tmp != (inl(emu->port + HCFG) & ~0x800)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) emu->tos_link = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) outl(tmp, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int snd_emu10k1_done(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) outl(0, emu->port + INTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * Shutdown the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) for (ch = 0; ch < NUM_G; ch++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) for (ch = 0; ch < NUM_G; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) snd_emu10k1_ptr_write(emu, VTFT, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) snd_emu10k1_ptr_write(emu, CVCF, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) snd_emu10k1_ptr_write(emu, CPF, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* reset recording buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) snd_emu10k1_ptr_write(emu, MICBS, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) snd_emu10k1_ptr_write(emu, FXBS, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) snd_emu10k1_ptr_write(emu, FXWC, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) snd_emu10k1_ptr_write(emu, TCB, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) snd_emu10k1_ptr_write(emu, DBG, 0, EMU10K1_DBG_SINGLE_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* disable channel interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* disable audio and lock cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) snd_emu10k1_ptr_write(emu, PTB, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * ECARD functional implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* In A1 Silicon, these bits are in the HC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define HOOKN_BIT (1L << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define HANDN_BIT (1L << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define PULSEN_BIT (1L << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define EC_GDI1 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define EC_GDI0 (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define EC_NUM_CONTROL_BITS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define EC_AC3_DATA_SELN 0x0001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define EC_EE_DATA_SEL 0x0002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define EC_EE_CNTRL_SELN 0x0004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define EC_EECLK 0x0008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define EC_EECS 0x0010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define EC_EESDO 0x0020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define EC_TRIM_CSN 0x0040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define EC_TRIM_SCLK 0x0080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define EC_TRIM_SDATA 0x0100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define EC_TRIM_MUTEN 0x0200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define EC_ADCCAL 0x0400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define EC_ADCRSTN 0x0800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define EC_DACCAL 0x1000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define EC_DACMUTEN 0x2000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define EC_LEDN 0x4000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define EC_SPDIF0_SEL_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define EC_SPDIF1_SEL_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define EC_SPDIF0_SEL_MASK (0x3L << EC_SPDIF0_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define EC_SPDIF1_SEL_MASK (0x7L << EC_SPDIF1_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define EC_SPDIF0_SELECT(_x) (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define EC_SPDIF1_SELECT(_x) (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define EC_CURRENT_PROM_VERSION 0x01 /* Self-explanatory. This should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * be incremented any time the EEPROM's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * format is changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define EC_EEPROM_SIZE 0x40 /* ECARD EEPROM has 64 16-bit words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Addresses for special values stored in to EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define EC_PROM_VERSION_ADDR 0x20 /* Address of the current prom version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define EC_BOARDREV0_ADDR 0x21 /* LSW of board rev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define EC_BOARDREV1_ADDR 0x22 /* MSW of board rev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define EC_LAST_PROMFILE_ADDR 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define EC_SERIALNUM_ADDR 0x30 /* First word of serial number. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * can be up to 30 characters in length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * and is stored as a NULL-terminated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * ASCII string. Any unused bytes must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * filled with zeros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define EC_CHECKSUM_ADDR 0x3f /* Location at which checksum is stored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Most of this stuff is pretty self-evident. According to the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * dudes, we need to leave the ADCCAL bit low in order to avoid a DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * offset problem. Weird.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define EC_RAW_RUN_MODE (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) EC_TRIM_CSN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define EC_DEFAULT_ADC_GAIN 0xC4C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define EC_DEFAULT_SPDIF0_SEL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define EC_DEFAULT_SPDIF1_SEL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * @func Clock bits into the Ecard's control latch. The Ecard uses a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * control latch will is loaded bit-serially by toggling the Modem control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * lines from function 2 on the E8010. This function hides these details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * and presents the illusion that we are actually writing to a distinct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static void snd_emu10k1_ecard_write(struct snd_emu10k1 *emu, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned short count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned long hc_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned int hc_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) hc_port = emu->port + HCFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) outl(hc_value, hc_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) for (count = 0; count < EC_NUM_CONTROL_BITS; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* Set up the value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) data = ((value & 0x1) ? PULSEN_BIT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) value >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) outl(hc_value | data, hc_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Clock the shift register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) outl(hc_value | data | HANDN_BIT, hc_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) outl(hc_value | data, hc_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Latch the bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) outl(hc_value | HOOKN_BIT, hc_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) outl(hc_value, hc_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * @func Set the gain of the ECARD's CS3310 Trim/gain controller. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * trim value consists of a 16bit value which is composed of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * 8 bit gain/trim values, one for the left channel and one for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * right channel. The following table maps from the Gain/Attenuation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * value in decibels into the corresponding bit pattern for a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static void snd_emu10k1_ecard_setadcgain(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned short gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Enable writing to the TRIM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Do it again to insure that we meet hold time requirements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) for (bit = (1 << 15); bit; bit >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (gain & bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) value |= EC_TRIM_SDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Clock the bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) snd_emu10k1_ecard_write(emu, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) snd_emu10k1_ecard_write(emu, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int snd_emu10k1_ecard_init(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned int hc_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Set up the initial settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) emu->ecard_ctrl = EC_RAW_RUN_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Step 0: Set the codec type in the hardware control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * and enable audio output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) hc_value = inl(emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) inl(emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Step 1: Turn off the led and deassert TRIM_CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* Step 2: Calibrate the ADC and DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* Step 3: Wait for awhile; XXX We can't get away with this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * under a real operating system; we'll need to block and wait that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * way. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) snd_emu10k1_wait(emu, 48000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* Step 4: Switch off the DAC and ADC calibration. Note
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * That ADC_CAL is actually an inverted signal, so we assert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * it here to stop calibration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Step 4: Switch into run mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Step 5: Set the analog input gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static int snd_emu10k1_cardbus_init(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) unsigned long special_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) __always_unused unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Special initialisation routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * before the rest of the IO-Ports become active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) special_port = emu->port + 0x38;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) value = inl(special_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) outl(0x00d00000, special_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) value = inl(special_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) outl(0x00d00001, special_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) value = inl(special_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) outl(0x00d0005f, special_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) value = inl(special_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) outl(0x00d0007f, special_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) value = inl(special_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) outl(0x0090007f, special_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) value = inl(special_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) snd_emu10k1_ptr20_write(emu, TINA2_VOLUME, 0, 0xfefefefe); /* Defaults to 0x30303030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Delay to give time for ADC chip to switch on. It needs 113ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) const struct firmware *fw_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int n, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) __always_unused unsigned int write_post;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (!fw_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* The FPGA is a Xilinx Spartan IIE XC2S50E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* GPIO7 -> FPGA PGMN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * GPIO6 -> FPGA CCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * GPIO5 -> FPGA DIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * FPGA CONFIG OFF -> FPGA PGMN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) spin_lock_irqsave(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) outl(0x00, emu->port + A_IOCFG); /* Set PGMN low for 1uS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) write_post = inl(emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) outl(0x80, emu->port + A_IOCFG); /* Leave bit 7 set during netlist setup. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) write_post = inl(emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) udelay(100); /* Allow FPGA memory to clean */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) for (n = 0; n < fw_entry->size; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) value = fw_entry->data[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (value & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) reg = reg | 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) value = value >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) outl(reg, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) write_post = inl(emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) outl(reg | 0x40, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) write_post = inl(emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* After programming, set GPIO bit 4 high again. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) outl(0x10, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) write_post = inl(emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) spin_unlock_irqrestore(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* firmware file names, per model, init-fw and dock-fw (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const char * const firmware_names[5][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) [EMU_MODEL_EMU1010] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) HANA_FILENAME, DOCK_FILENAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) [EMU_MODEL_EMU1010B] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) EMU1010B_FILENAME, MICRO_DOCK_FILENAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) [EMU_MODEL_EMU1616] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) EMU1010_NOTEBOOK_FILENAME, MICRO_DOCK_FILENAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) [EMU_MODEL_EMU0404] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) EMU0404_FILENAME, NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int snd_emu1010_load_firmware(struct snd_emu10k1 *emu, int dock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) const struct firmware **fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) const char *filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (!*fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) filename = firmware_names[emu->card_capabilities->emu_model][dock];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (!filename)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) err = request_firmware(fw, filename, &emu->pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return snd_emu1010_load_firmware_entry(emu, *fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static void emu1010_firmware_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct snd_emu10k1 *emu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u32 tmp, tmp2, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) emu = container_of(work, struct snd_emu10k1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) emu1010.firmware_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (emu->card->shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (emu->suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp); /* IRQ Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); /* OPTIONS: Which cards are attached to the EMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Audio Dock attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Return to Audio Dock programming mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dev_info(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) "emu1010: Loading Audio Dock Firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) EMU_HANA_FPGA_CONFIG_AUDIODOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) err = snd_emu1010_load_firmware(emu, 1, &emu->dock_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dev_info(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "emu1010: EMU_HANA+DOCK_IRQ_STATUS = 0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* ID, should read & 0x7f = 0x55 when FPGA programmed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) snd_emu1010_fpga_read(emu, EMU_HANA_ID, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_info(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) "emu1010: EMU_HANA+DOCK_ID = 0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if ((tmp & 0x1f) != 0x15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* FPGA failed to be programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dev_info(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) "emu1010: Loading Audio Dock Firmware file failed, reg = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_info(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) "emu1010: Audio Dock Firmware loaded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) snd_emu1010_fpga_read(emu, EMU_DOCK_MAJOR_REV, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) snd_emu1010_fpga_read(emu, EMU_DOCK_MINOR_REV, &tmp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_info(emu->card->dev, "Audio Dock ver: %u.%u\n", tmp, tmp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Sync clocking between 1010 and Dock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* Allow DLL to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* Unmute all. Default is muted after a firmware load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) } else if (!reg && emu->emu1010.last_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* Audio Dock removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dev_info(emu->card->dev, "emu1010: Audio Dock detached\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* Unmute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) emu->emu1010.last_reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!emu->card->shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) schedule_delayed_work(&emu->emu1010.firmware_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * EMU-1010 - details found out from this driver, official MS Win drivers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * testing the card:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * Audigy2 (aka Alice2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * * communication over PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * * conversion of 32-bit data coming over EMU32 links from HANA FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * to 2 x 16-bit, using internal DSP instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * * slave mode, clock supplied by HANA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * * linked to HANA using:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * 32 x 32-bit serial EMU32 output channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * 16 x EMU32 input channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * (?) x I2S I/O channels (?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * FPGA (aka HANA):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * ---------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * * provides all (?) physical inputs and outputs of the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * (ADC, DAC, SPDIF I/O, ADAT I/O, etc.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * * provides clock signal for the card and Alice2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * * two crystals - for 44.1kHz and 48kHz multiples
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * * provides internal routing of signal sources to signal destinations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * * inputs/outputs to Alice2 - see above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * Current status of the driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * ----------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * * only 44.1/48kHz supported (the MS Win driver supports up to 192 kHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * * PCM device nb. 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * 16 x 16-bit playback - snd_emu10k1_fx8010_playback_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * 16 x 32-bit capture - snd_emu10k1_capture_efx_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static int snd_emu10k1_emu1010_init(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u32 tmp, tmp2, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dev_info(emu->card->dev, "emu1010: Special config.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * Lock Sound Memory Cache, Lock Tank Memory Cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * Mute all codecs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) outl(0x0005a00c, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * Lock Tank Memory Cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * Mute all codecs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) outl(0x0005a004, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * Mute all codecs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) outl(0x0005a000, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * Mute all codecs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) outl(0x0005a000, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* Disable 48Volt power to Audio Dock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* ID, should read & 0x7f = 0x55. (Bit 7 is the IRQ bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev_dbg(emu->card->dev, "reg1 = 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if ((reg & 0x3f) == 0x15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* FPGA netlist already present so clear it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* Return to programming mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev_dbg(emu->card->dev, "reg2 = 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if ((reg & 0x3f) == 0x15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* FPGA failed to return to programming mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) dev_info(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) "emu1010: FPGA failed to return to programming mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dev_info(emu->card->dev, "emu1010: EMU_HANA_ID = 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) err = snd_emu1010_load_firmware(emu, 0, &emu->firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dev_info(emu->card->dev, "emu1010: Loading Firmware failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* ID, should read & 0x7f = 0x55 when FPGA programmed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if ((reg & 0x3f) != 0x15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* FPGA failed to be programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dev_info(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) "emu1010: Loading Hana Firmware file failed, reg = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dev_info(emu->card->dev, "emu1010: Hana Firmware loaded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) snd_emu1010_fpga_read(emu, EMU_HANA_MAJOR_REV, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) snd_emu1010_fpga_read(emu, EMU_HANA_MINOR_REV, &tmp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) dev_info(emu->card->dev, "emu1010: Hana version: %u.%u\n", tmp, tmp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* Enable 48Volt power to Audio Dock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, EMU_HANA_DOCK_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) snd_emu1010_fpga_read(emu, EMU_HANA_OPTICAL_TYPE, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* Optical -> ADAT I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* 0 : SPDIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * 1 : ADAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) emu->emu1010.optical_in = 1; /* IN_ADAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) emu->emu1010.optical_out = 1; /* IN_ADAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) snd_emu1010_fpga_read(emu, EMU_HANA_ADC_PADS, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* Set no attenuation on Audio Dock pads. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) emu->emu1010.adc_pads = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* Unmute Audio dock DACs, Headphone source DAC-4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) snd_emu1010_fpga_read(emu, EMU_HANA_DAC_PADS, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* DAC PADs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) emu->emu1010.dac_pads = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* SPDIF Format. Set Consumer mode, 24bit, copy enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* MIDI routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* Unknown. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* IRQ Enable: All on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* snd_emu1010_fpga_write(emu, 0x09, 0x0f ); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* IRQ Enable: All off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) dev_info(emu->card->dev, "emu1010: Card options3 = 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* Default WCLK set to 48kHz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* Word Clock source, Internal 48kHz x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* Audio Dock LEDs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* For 96kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* For 192kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_RIGHT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) EMU_DST_ALICE2_EMU32_6, EMU_SRC_HAMOA_ADC_LEFT4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) EMU_DST_ALICE2_EMU32_7, EMU_SRC_HAMOA_ADC_RIGHT4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* For 48kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) EMU_DST_ALICE2_EMU32_0, EMU_SRC_DOCK_MIC_A1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) EMU_DST_ALICE2_EMU32_1, EMU_SRC_DOCK_MIC_B1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_LEFT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) EMU_DST_ALICE2_EMU32_4, EMU_SRC_DOCK_ADC1_LEFT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) EMU_DST_ALICE2_EMU32_5, EMU_SRC_DOCK_ADC1_RIGHT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) EMU_DST_ALICE2_EMU32_6, EMU_SRC_DOCK_ADC2_LEFT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) EMU_DST_ALICE2_EMU32_7, EMU_SRC_DOCK_ADC2_RIGHT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /* Pavel Hofman - setting defaults for 8 more capture channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * Defaults only, users will set their own values anyways, let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * just copy/paste.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) EMU_DST_ALICE2_EMU32_8, EMU_SRC_DOCK_MIC_A1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) EMU_DST_ALICE2_EMU32_9, EMU_SRC_DOCK_MIC_B1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) EMU_DST_ALICE2_EMU32_A, EMU_SRC_HAMOA_ADC_LEFT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) EMU_DST_ALICE2_EMU32_B, EMU_SRC_HAMOA_ADC_LEFT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_ADC1_LEFT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_ADC1_RIGHT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) EMU_DST_ALICE2_EMU32_E, EMU_SRC_DOCK_ADC2_LEFT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) EMU_DST_ALICE2_EMU32_F, EMU_SRC_DOCK_ADC2_RIGHT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* Original */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) EMU_DST_ALICE2_EMU32_4, EMU_SRC_HANA_ADAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) EMU_DST_ALICE2_EMU32_5, EMU_SRC_HANA_ADAT + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) EMU_DST_ALICE2_EMU32_6, EMU_SRC_HANA_ADAT + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) EMU_DST_ALICE2_EMU32_7, EMU_SRC_HANA_ADAT + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) EMU_DST_ALICE2_EMU32_8, EMU_SRC_HANA_ADAT + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) EMU_DST_ALICE2_EMU32_9, EMU_SRC_HANA_ADAT + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) EMU_DST_ALICE2_EMU32_A, EMU_SRC_HANA_ADAT + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) EMU_DST_ALICE2_EMU32_B, EMU_SRC_HANA_ADAT + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_MIC_A1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_MIC_B1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) EMU_DST_ALICE2_EMU32_E, EMU_SRC_HAMOA_ADC_LEFT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) EMU_DST_ALICE2_EMU32_F, EMU_SRC_HAMOA_ADC_LEFT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) for (i = 0; i < 0x20; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* AudioDock Elink <- Silence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) snd_emu1010_fpga_link_dst_src_write(emu, 0x0100 + i, EMU_SRC_SILENCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Hana SPDIF Out <- Silence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) snd_emu1010_fpga_link_dst_src_write(emu, 0x0200 + i, EMU_SRC_SILENCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) for (i = 0; i < 7; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* Hamoa DAC <- Silence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) snd_emu1010_fpga_link_dst_src_write(emu, 0x0300 + i, EMU_SRC_SILENCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) for (i = 0; i < 7; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* Hana ADAT Out <- Silence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) snd_emu1010_fpga_link_dst_src_write(emu, EMU_DST_HANA_ADAT + i, EMU_SRC_SILENCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) EMU_DST_ALICE_I2S0_LEFT, EMU_SRC_DOCK_ADC1_LEFT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) EMU_DST_ALICE_I2S0_RIGHT, EMU_SRC_DOCK_ADC1_RIGHT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) EMU_DST_ALICE_I2S1_LEFT, EMU_SRC_DOCK_ADC2_LEFT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) EMU_DST_ALICE_I2S1_RIGHT, EMU_SRC_DOCK_ADC2_RIGHT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) EMU_DST_ALICE_I2S2_LEFT, EMU_SRC_DOCK_ADC3_LEFT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) EMU_DST_ALICE_I2S2_RIGHT, EMU_SRC_DOCK_ADC3_RIGHT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x01); /* Unmute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * Lock Sound Memory Cache, Lock Tank Memory Cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * Mute all codecs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) outl(0x0000a000, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * Lock Sound Memory Cache, Lock Tank Memory Cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * Un-Mute all codecs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) outl(0x0000a001, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* Initial boot complete. Now patches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); /* MIDI Route */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); /* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); /* MIDI Route */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); /* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10); /* SPDIF Format spdif (or 0x11 for aes/ebu) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32B + 2); /* ALICE2 bus 0xa2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32B + 3); /* ALICE2 bus 0xa3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 2); /* ALICE2 bus 0xb2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); /* ALICE2 bus 0xb3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /* Default outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /* 1616(M) cardbus default outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* ALICE2 bus 0xa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) emu->emu1010.output_source[0] = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) emu->emu1010.output_source[1] = 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) emu->emu1010.output_source[2] = 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) emu->emu1010.output_source[3] = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) emu->emu1010.output_source[4] = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) emu->emu1010.output_source[5] = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* ALICE2 bus 0xa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) EMU_DST_MANA_DAC_LEFT, EMU_SRC_ALICE_EMU32A + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) emu->emu1010.output_source[16] = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) EMU_DST_MANA_DAC_RIGHT, EMU_SRC_ALICE_EMU32A + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) emu->emu1010.output_source[17] = 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* ALICE2 bus 0xa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) emu->emu1010.output_source[0] = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) emu->emu1010.output_source[1] = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) emu->emu1010.output_source[2] = 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) emu->emu1010.output_source[3] = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) emu->emu1010.output_source[4] = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) emu->emu1010.output_source[5] = 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) EMU_DST_DOCK_DAC4_LEFT1, EMU_SRC_ALICE_EMU32A + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) emu->emu1010.output_source[6] = 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) EMU_DST_DOCK_DAC4_RIGHT1, EMU_SRC_ALICE_EMU32A + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) emu->emu1010.output_source[7] = 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* ALICE2 bus 0xa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) EMU_DST_DOCK_PHONES_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) emu->emu1010.output_source[8] = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) EMU_DST_DOCK_PHONES_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) emu->emu1010.output_source[9] = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* ALICE2 bus 0xa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) EMU_DST_DOCK_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) emu->emu1010.output_source[10] = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) EMU_DST_DOCK_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) emu->emu1010.output_source[11] = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* ALICE2 bus 0xa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) emu->emu1010.output_source[12] = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) emu->emu1010.output_source[13] = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* ALICE2 bus 0xa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) emu->emu1010.output_source[14] = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) emu->emu1010.output_source[15] = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /* ALICE2 bus 0xa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) EMU_DST_HANA_ADAT, EMU_SRC_ALICE_EMU32A + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) emu->emu1010.output_source[16] = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) EMU_DST_HANA_ADAT + 1, EMU_SRC_ALICE_EMU32A + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) emu->emu1010.output_source[17] = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) EMU_DST_HANA_ADAT + 2, EMU_SRC_ALICE_EMU32A + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) emu->emu1010.output_source[18] = 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) EMU_DST_HANA_ADAT + 3, EMU_SRC_ALICE_EMU32A + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) emu->emu1010.output_source[19] = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) EMU_DST_HANA_ADAT + 4, EMU_SRC_ALICE_EMU32A + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) emu->emu1010.output_source[20] = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) EMU_DST_HANA_ADAT + 5, EMU_SRC_ALICE_EMU32A + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) emu->emu1010.output_source[21] = 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) EMU_DST_HANA_ADAT + 6, EMU_SRC_ALICE_EMU32A + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) emu->emu1010.output_source[22] = 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) snd_emu1010_fpga_link_dst_src_write(emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) EMU_DST_HANA_ADAT + 7, EMU_SRC_ALICE_EMU32A + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) emu->emu1010.output_source[23] = 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /* TEMP: Select SPDIF in/out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, 0x0); */ /* Output spdif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* TEMP: Select 48kHz SPDIF out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x0); /* Mute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x0); /* Default fallback clock 48kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /* Word Clock source, Internal 48kHz x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) emu->emu1010.internal_clock = 1; /* 48000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12); /* Set LEDs on Audio Dock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x1); /* Unmute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* snd_emu1010_fpga_write(emu, 0x7, 0x0); */ /* Mute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* snd_emu1010_fpga_write(emu, 0x7, 0x1); */ /* Unmute all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /* snd_emu1010_fpga_write(emu, 0xe, 0x12); */ /* Set LEDs on Audio Dock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * Create the EMU10K1 instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) static int alloc_pm_buffer(struct snd_emu10k1 *emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static void free_pm_buffer(struct snd_emu10k1 *emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static int snd_emu10k1_free(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (emu->port) { /* avoid access to already used hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) snd_emu10k1_fx8010_tram_setup(emu, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) snd_emu10k1_done(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) snd_emu10k1_free_efx(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /* Disable 48Volt power to Audio Dock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) cancel_delayed_work_sync(&emu->emu1010.firmware_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) release_firmware(emu->firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) release_firmware(emu->dock_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (emu->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) free_irq(emu->irq, emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) snd_util_memhdr_free(emu->memhdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (emu->silent_page.area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) snd_dma_free_pages(&emu->silent_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (emu->ptb_pages.area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) snd_dma_free_pages(&emu->ptb_pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) vfree(emu->page_ptr_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) vfree(emu->page_addr_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) free_pm_buffer(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (emu->port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) pci_release_regions(emu->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (emu->card_capabilities->ca0151_chip) /* P16V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) snd_p16v_free(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) pci_disable_device(emu->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) kfree(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static int snd_emu10k1_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct snd_emu10k1 *emu = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return snd_emu10k1_free(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static const struct snd_emu_chip_details emu_chip_details[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* Audigy 5/Rx SB1550 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /* Tested by michael@gernoth.net 28 Mar 2015 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* DSP: CA10300-IAT LF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * DAC: Cirrus Logic CS4382-KQZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * ADC: Philips 1361T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * AC97: Sigmatel STAC9750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * CA0151: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10241102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .driver = "Audigy2", .name = "SB Audigy 5/Rx [SB1550]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .ca0108_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .adc_1361t = 1, /* 24 bit capture instead of 16bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .ac97_chip = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* Audigy4 (Not PRO) SB0610 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /* Tested by James@superbug.co.uk 4th April 2006 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /* A_IOCFG bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) * Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * 0: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * 1: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * 2: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) * 3: 0 - Digital Out, 1 - Line in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * 4: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * 5: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * 6: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * 7: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * Input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * 8: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * 9: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * A: Green jack sense (Front)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * B: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * C: Black jack sense (Rear/Side Right)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * D: Yellow jack sense (Center/LFE/Side Left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * E: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * F: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * Digital Out/Line in switch using A_IOCFG bit 3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * 0 - Digital Out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * 1 - Line in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /* Mic input not tested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * Analog CD input not tested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * Digital Out not tested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * Line in working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * Audio output 5.1 working. Side outputs not working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* DSP: CA10300-IAT LF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * DAC: Cirrus Logic CS4382-KQZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * ADC: Philips 1361T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * AC97: Sigmatel STAC9750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * CA0151: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10211102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .driver = "Audigy2", .name = "SB Audigy 4 [SB0610]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .ca0108_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .adc_1361t = 1, /* 24 bit capture instead of 16bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /* Audigy 2 Value AC3 out does not work yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * Need to find out how to turn off interpolators.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* Tested by James@superbug.co.uk 3rd July 2005 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) /* DSP: CA0108-IAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * DAC: CS4382-KQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * ADC: Philips 1361T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) * AC97: STAC9750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) * CA0151: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .driver = "Audigy2", .name = "SB Audigy 2 Value [SB0400]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .ca0108_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /* Audigy 2 ZS Notebook Cardbus card.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /* Tested by James@superbug.co.uk 6th November 2006 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* Audio output 7.1/Headphones working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * Digital output working. (AC3 not checked, only PCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * Audio Mic/Line inputs working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * Digital input not tested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /* DSP: Tina2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * DAC: Wolfson WM8768/WM8568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * ADC: Wolfson WM8775
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * AC97: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * CA0151: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* Tested by James@superbug.co.uk 4th April 2006 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /* A_IOCFG bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * 0: Not Used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * 1: 0 = Mute all the 7.1 channel out. 1 = unmute.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * 2: Analog input 0 = line in, 1 = mic in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * 3: Not Used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * 4: Digital output 0 = off, 1 = on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * 5: Not Used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) * 6: Not Used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * 7: Not Used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * Input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * All bits 1 (0x3fxx) means nothing plugged in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * 8-9: 0 = Line in/Mic, 2 = Optical in, 3 = Nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * A-B: 0 = Headphones, 2 = Optical out, 3 = Nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * C-D: 2 = Front/Rear/etc, 3 = nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * E-F: Always 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x20011102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .driver = "Audigy2", .name = "Audigy 2 ZS Notebook [SB0530]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .ca0108_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .ca_cardbus_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .spi_dac = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .i2c_adc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .spk71 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /* Tested by James@superbug.co.uk 4th Nov 2007. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x42011102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .driver = "Audigy2", .name = "E-mu 1010 Notebook [MAEM8950]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .id = "EMU1010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .ca0108_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .ca_cardbus_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .spk71 = 1 ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .emu_model = EMU_MODEL_EMU1616},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /* Tested by James@superbug.co.uk 4th Nov 2007. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* This is MAEM8960, 0202 is MAEM 8980 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40041102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .driver = "Audigy2", .name = "E-mu 1010b PCI [MAEM8960]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .id = "EMU1010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .ca0108_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 new revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /* Tested by Maxim Kachur <mcdebugger@duganet.ru> 17th Oct 2012. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* This is MAEM8986, 0202 is MAEM8980 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40071102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .driver = "Audigy2", .name = "E-mu 1010 PCIe [MAEM8986]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .id = "EMU1010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .ca0108_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 PCIe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /* Tested by James@superbug.co.uk 8th July 2005. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* This is MAEM8810, 0202 is MAEM8820 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40011102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .driver = "Audigy2", .name = "E-mu 1010 [MAEM8810]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .id = "EMU1010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .emu_model = EMU_MODEL_EMU1010}, /* EMU 1010 old revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) /* EMU0404b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40021102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .driver = "Audigy2", .name = "E-mu 0404b PCI [MAEM8852]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .id = "EMU0404",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .ca0108_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 new revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /* Tested by James@superbug.co.uk 20-3-2007. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40021102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .driver = "Audigy2", .name = "E-mu 0404 [MAEM8850]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .id = "EMU0404",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /* EMU0404 PCIe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40051102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .driver = "Audigy2", .name = "E-mu 0404 PCIe [MAEM8984]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .id = "EMU0404",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .ca0108_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 PCIe ver_03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* Note that all E-mu cards require kernel 2.6 or newer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) {.vendor = 0x1102, .device = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .driver = "Audigy2", .name = "SB Audigy 2 Value [Unknown]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .ca0108_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /* Tested by James@superbug.co.uk 3rd July 2005 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20071102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .driver = "Audigy2", .name = "SB Audigy 4 PRO [SB0380]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .ca0151_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .spdif_bug = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) /* Tested by shane-alsa@cm.nu 5th Nov 2005 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /* The 0x20061102 does have SB0350 written on it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) * Just like 0x20021102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20061102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .driver = "Audigy2", .name = "SB Audigy 2 [SB0350b]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .ca0151_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .spdif_bug = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .invert_shared_spdif = 1, /* digital/analog switch swapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* 0x20051102 also has SB0350 written on it, treated as Audigy 2 ZS by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) Creative's Windows driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20051102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350a]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .ca0151_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .spdif_bug = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .invert_shared_spdif = 1, /* digital/analog switch swapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20021102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .ca0151_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .spdif_bug = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .invert_shared_spdif = 1, /* digital/analog switch swapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20011102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0360]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .ca0151_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .spdif_bug = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .invert_shared_spdif = 1, /* digital/analog switch swapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /* Audigy 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) /* Tested by James@superbug.co.uk 3rd July 2005 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /* DSP: CA0102-IAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) * DAC: CS4382-KQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) * ADC: Philips 1361T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) * AC97: STAC9721
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * CA0151: Yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10071102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .driver = "Audigy2", .name = "SB Audigy 2 [SB0240]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .ca0151_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .spdif_bug = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .adc_1361t = 1, /* 24 bit capture instead of 16bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10051102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .driver = "Audigy2", .name = "Audigy 2 Platinum EX [SB0280]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .ca0151_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .spdif_bug = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) /* Dell OEM/Creative Labs Audigy 2 ZS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /* See ALSA bug#1365 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10031102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0353]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .ca0151_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .spdif_bug = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .invert_shared_spdif = 1, /* digital/analog switch swapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10021102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .driver = "Audigy2", .name = "SB Audigy 2 Platinum [SB0240P]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .ca0151_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .spk71 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .spdif_bug = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .invert_shared_spdif = 1, /* digital/analog switch swapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .adc_1361t = 1, /* 24 bit capture instead of 16bit. Fixes ALSA bug#324 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) {.vendor = 0x1102, .device = 0x0004, .revision = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .driver = "Audigy2", .name = "SB Audigy 2 [Unknown]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .id = "Audigy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .ca0151_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .spdif_bug = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00531102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .driver = "Audigy", .name = "SB Audigy 1 [SB0092]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .id = "Audigy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00521102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .driver = "Audigy", .name = "SB Audigy 1 ES [SB0160]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .id = "Audigy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .spdif_bug = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00511102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .driver = "Audigy", .name = "SB Audigy 1 [SB0090]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .id = "Audigy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) {.vendor = 0x1102, .device = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .driver = "Audigy", .name = "Audigy 1 [Unknown]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .id = "Audigy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .emu10k2_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .ca0102_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x100a1102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806b1102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .driver = "EMU10K1", .name = "SB Live! [SB0105]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806a1102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .driver = "EMU10K1", .name = "SB Live! Value [SB0103]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80691102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .driver = "EMU10K1", .name = "SB Live! Value [SB0101]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /* Tested by ALSA bug#1680 26th December 2005 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /* note: It really has SB0220 written on the card, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* but it's SB0228 according to kx.inf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80661102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .driver = "EMU10K1", .name = "SB Live! 5.1 Dell OEM [SB0228]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) /* Tested by Thomas Zehetbauer 27th Aug 2005 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80651102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .driver = "EMU10K1", .name = "SB Live! 5.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* Tested by alsa bugtrack user "hus" bug #1297 12th Aug 2005 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0060]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .ac97_chip = 2, /* ac97 is optional; both SBLive 5.1 and platinum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * share the same IDs!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80511102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .driver = "EMU10K1", .name = "SB Live! Value [CT4850]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .driver = "EMU10K1", .name = "SB Live! Platinum [CT4760P]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .ac97_chip = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80321102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .driver = "EMU10K1", .name = "SB Live! Value [CT4871]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80311102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .driver = "EMU10K1", .name = "SB Live! Value [CT4831]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80281102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .driver = "EMU10K1", .name = "SB Live! Value [CT4870]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) /* Tested by James@superbug.co.uk 3rd July 2005 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .driver = "EMU10K1", .name = "SB Live! Value [CT4832]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80261102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .driver = "EMU10K1", .name = "SB Live! Value [CT4830]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80231102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .driver = "EMU10K1", .name = "SB PCI512 [CT4790]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80221102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .driver = "EMU10K1", .name = "SB Live! Value [CT4780]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .driver = "EMU10K1", .name = "E-mu APS [PC545]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .id = "APS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .ecard = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00211102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .driver = "EMU10K1", .name = "SB Live! [CT4620]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00201102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .driver = "EMU10K1", .name = "SB Live! Value [CT4670]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) {.vendor = 0x1102, .device = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .driver = "EMU10K1", .name = "SB Live! [Unknown]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .id = "Live",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .emu10k1_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .ac97_chip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .sblive51 = 1} ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) { } /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) * The chip (at least the Audigy 2 CA0102 chip, but most likely others, too)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) * has a problem that from time to time it likes to do few DMA reads a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) * beyond its normal allocation and gets very confused if these reads get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * blocked by a IOMMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * This behaviour has been observed for the first (reserved) page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * (for which it happens multiple times at every playback), often for various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * synth pages and sometimes for PCM playback buffers and the page table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * memory itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) * As a workaround let's widen these DMA allocations by an extra page if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) * detect that the device is behind a non-passthrough IOMMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static void snd_emu10k1_detect_iommu(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) struct iommu_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) emu->iommu_workaround = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (!iommu_present(emu->card->dev->bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) domain = iommu_get_domain_for_dev(emu->card->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) if (domain && domain->type == IOMMU_DOMAIN_IDENTITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) dev_notice(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) "non-passthrough IOMMU detected, widening DMA allocations");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) emu->iommu_workaround = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) int snd_emu10k1_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) unsigned short extin_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) unsigned short extout_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) long max_cache_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) int enable_ir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) uint subsystem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) struct snd_emu10k1 **remu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) struct snd_emu10k1 *emu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) int idx, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) int is_audigy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) size_t page_table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) __le32 *pgtbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) unsigned int silent_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) const struct snd_emu_chip_details *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .dev_free = snd_emu10k1_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) *remu = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) /* enable PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) err = pci_enable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) emu = kzalloc(sizeof(*emu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (emu == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) emu->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) spin_lock_init(&emu->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) spin_lock_init(&emu->emu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) spin_lock_init(&emu->spi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) spin_lock_init(&emu->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) spin_lock_init(&emu->voice_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) spin_lock_init(&emu->synth_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) spin_lock_init(&emu->memblk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) mutex_init(&emu->fx8010.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) INIT_LIST_HEAD(&emu->mapped_link_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) INIT_LIST_HEAD(&emu->mapped_order_link_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) emu->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) emu->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) emu->synth = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) emu->get_synth_voice = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) INIT_DELAYED_WORK(&emu->emu1010.firmware_work, emu1010_firmware_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) /* read revision & serial */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) emu->revision = pci->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) dev_dbg(card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) "vendor = 0x%x, device = 0x%x, subsystem_vendor_id = 0x%x, subsystem_id = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) pci->vendor, pci->device, emu->serial, emu->model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) for (c = emu_chip_details; c->vendor; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (c->vendor == pci->vendor && c->device == pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) if (subsystem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if (c->subsystem && (c->subsystem == subsystem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) if (c->subsystem && (c->subsystem != emu->serial))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (c->revision && c->revision != emu->revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (c->vendor == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) dev_err(card->dev, "emu10k1: Card not recognised\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) kfree(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) emu->card_capabilities = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (c->subsystem && !subsystem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) dev_dbg(card->dev, "Sound card name = %s\n", c->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) else if (subsystem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) dev_dbg(card->dev, "Sound card name = %s, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) "vendor = 0x%x, device = 0x%x, subsystem = 0x%x. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) "Forced to subsystem = 0x%x\n", c->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) pci->vendor, pci->device, emu->serial, c->subsystem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) dev_dbg(card->dev, "Sound card name = %s, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) "vendor = 0x%x, device = 0x%x, subsystem = 0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) c->name, pci->vendor, pci->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) emu->serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (!*card->id && c->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) strlcpy(card->id, c->id, sizeof(card->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) is_audigy = emu->audigy = c->emu10k2_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) snd_emu10k1_detect_iommu(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) /* set addressing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) emu->address_mode = is_audigy ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) /* set the DMA transfer mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) emu->dma_mask = emu->address_mode ? EMU10K1_DMA_MASK : AUDIGY_DMA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (dma_set_mask_and_coherent(&pci->dev, emu->dma_mask) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) dev_err(card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) "architecture does not support PCI busmaster DMA with mask 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) emu->dma_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) kfree(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (is_audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) emu->gpr_base = A_FXGPREGBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) emu->gpr_base = FXGPREGBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) err = pci_request_regions(pci, "EMU10K1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) kfree(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) emu->port = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) page_table_size = sizeof(u32) * (emu->address_mode ? MAXPAGES1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) MAXPAGES0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (snd_emu10k1_alloc_pages_maybe_wider(emu, page_table_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) &emu->ptb_pages) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) dev_dbg(card->dev, "page table address range is %.8lx:%.8lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) (unsigned long)emu->ptb_pages.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) (unsigned long)(emu->ptb_pages.addr + emu->ptb_pages.bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) emu->page_ptr_table = vmalloc(array_size(sizeof(void *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) emu->max_cache_pages));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) emu->page_addr_table = vmalloc(array_size(sizeof(unsigned long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) emu->max_cache_pages));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) if (emu->page_ptr_table == NULL || emu->page_addr_table == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (snd_emu10k1_alloc_pages_maybe_wider(emu, EMUPAGESIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) &emu->silent_page) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) dev_dbg(card->dev, "silent page range is %.8lx:%.8lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) (unsigned long)emu->silent_page.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) (unsigned long)(emu->silent_page.addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) emu->silent_page.bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) if (emu->memhdr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) emu->memhdr->block_extra_size = sizeof(struct snd_emu10k1_memblk) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) sizeof(struct snd_util_memblk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) emu->fx8010.fxbus_mask = 0x303f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) if (extin_mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) extin_mask = 0x3fcf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (extout_mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) extout_mask = 0x7fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) emu->fx8010.extin_mask = extin_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) emu->fx8010.extout_mask = extout_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) emu->enable_ir = enable_ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if (emu->card_capabilities->ca_cardbus_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) err = snd_emu10k1_cardbus_init(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) if (emu->card_capabilities->ecard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) err = snd_emu10k1_ecard_init(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) } else if (emu->card_capabilities->emu_model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) err = snd_emu10k1_emu1010_init(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) snd_emu10k1_free(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) does not support this, it shouldn't do any harm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) snd_emu10k1_ptr_write(emu, AC97SLOT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) AC97SLOT_CNTR|AC97SLOT_LFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) /* initialize TRAM setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) emu->fx8010.itram_size = (16 * 1024)/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) emu->fx8010.etram_pages.area = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) emu->fx8010.etram_pages.bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) /* irq handler must be registered after I/O ports are activated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (request_irq(pci->irq, snd_emu10k1_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) KBUILD_MODNAME, emu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) emu->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) card->sync_irq = emu->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) * Init to 0x02109204 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) * Clock accuracy = 0 (1000ppm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) * Sample Rate = 2 (48kHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) * Audio Channel = 1 (Left of 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) * Source Number = 0 (Unspecified)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) * Generation Status = 1 (Original for Cat Code 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) * Cat Code = 12 (Digital Signal Mixer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) * Mode = 0 (Mode 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) * Emphasis = 0 (None)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) * CP = 1 (Copyright unasserted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) * AN = 0 (Audio data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) * P = 0 (Consumer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) emu->spdif_bits[0] = emu->spdif_bits[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) emu->spdif_bits[2] = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) SPCS_GENERATIONSTATUS | 0x00001200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) /* Clear silent pages and set up pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) memset(emu->silent_page.area, 0, emu->silent_page.bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) silent_page = emu->silent_page.addr << emu->address_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) pgtbl = (__le32 *)emu->ptb_pages.area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) for (idx = 0; idx < (emu->address_mode ? MAXPAGES1 : MAXPAGES0); idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) pgtbl[idx] = cpu_to_le32(silent_page | idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) /* set up voice indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) for (idx = 0; idx < NUM_G; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) emu->voices[idx].emu = emu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) emu->voices[idx].number = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) err = snd_emu10k1_init(emu, enable_ir, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) err = alloc_pm_buffer(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) /* Initialize the effect engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) err = snd_emu10k1_init_efx(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) snd_emu10k1_audio_enable(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, emu, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) #ifdef CONFIG_SND_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) snd_emu10k1_proc_init(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) *remu = emu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) snd_emu10k1_free(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) static const unsigned char saved_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) FXRT, MAPA, MAPB, ENVVOL, ATKHLDV, DCYSUSV, LFOVAL1, ENVVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) ATKHLDM, DCYSUSM, LFOVAL2, IP, IFATN, PEFE, FMMOD, TREMFRQ, FM2FRQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) TEMPENV, ADCCR, FXWC, MICBA, ADCBA, FXBA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) MICBS, ADCBS, FXBS, CDCS, GPSCS, SPCS0, SPCS1, SPCS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) SPBYPASS, AC97SLOT, CDSRCS, GPSRCS, ZVSRCS, MICIDX, ADCIDX, FXIDX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) 0xff /* end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) static const unsigned char saved_regs_audigy[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) A_ADCIDX, A_MICIDX, A_FXWC1, A_FXWC2, A_SAMPLE_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) A_FXRT2, A_SENDAMOUNTS, A_FXRT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) 0xff /* end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) static int alloc_pm_buffer(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) size = ARRAY_SIZE(saved_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) size += ARRAY_SIZE(saved_regs_audigy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) emu->saved_ptr = vmalloc(array3_size(4, NUM_G, size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) if (!emu->saved_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) if (snd_emu10k1_efx_alloc_pm_buffer(emu) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) if (emu->card_capabilities->ca0151_chip &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) snd_p16v_alloc_pm_buffer(emu) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) static void free_pm_buffer(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) vfree(emu->saved_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) snd_emu10k1_efx_free_pm_buffer(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (emu->card_capabilities->ca0151_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) snd_p16v_free_pm_buffer(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) const unsigned char *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) unsigned int *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) val = emu->saved_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) for (reg = saved_regs; *reg != 0xff; reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) for (i = 0; i < NUM_G; i++, val++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) *val = snd_emu10k1_ptr_read(emu, *reg, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if (emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) for (reg = saved_regs_audigy; *reg != 0xff; reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) for (i = 0; i < NUM_G; i++, val++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) *val = snd_emu10k1_ptr_read(emu, *reg, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) emu->saved_a_iocfg = inl(emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) emu->saved_hcfg = inl(emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) void snd_emu10k1_resume_init(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) if (emu->card_capabilities->ca_cardbus_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) snd_emu10k1_cardbus_init(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) if (emu->card_capabilities->ecard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) snd_emu10k1_ecard_init(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) else if (emu->card_capabilities->emu_model)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) snd_emu10k1_emu1010_init(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) snd_emu10k1_init(emu, emu->enable_ir, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) const unsigned char *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) unsigned int *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) snd_emu10k1_audio_enable(emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) /* resore for spdif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (emu->audigy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) outl(emu->saved_a_iocfg, emu->port + A_IOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) outl(emu->saved_hcfg, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) val = emu->saved_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) for (reg = saved_regs; *reg != 0xff; reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) for (i = 0; i < NUM_G; i++, val++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) snd_emu10k1_ptr_write(emu, *reg, i, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) if (emu->audigy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) for (reg = saved_regs_audigy; *reg != 0xff; reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) for (i = 0; i < NUM_G; i++, val++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) snd_emu10k1_ptr_write(emu, *reg, i, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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