^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Copyright Echo Digital Audio Corporation (c) 1998 - 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) www.echoaudio.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) This file is part of Echo Digital Audio's generic driver library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Echo Digital Audio's generic driver library is free software;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) you can redistribute it and/or modify it under the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) the GNU General Public License as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Foundation, Inc., 59 Temple Place - Suite 330, Boston,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MA 02111-1307, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Translation from C++ and adaptation for use in ALSA-Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) were made by Giuliano Pochini <pochini@shiny.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int write_control_reg(struct echoaudio *chip, u32 value, char force);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int set_input_clock(struct echoaudio *chip, u16 clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int set_professional_spdif(struct echoaudio *chip, char prof);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int set_digital_mode(struct echoaudio *chip, u8 mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int check_asic_status(struct echoaudio *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (snd_BUG_ON((subdevice_id & 0xfff0) != MONA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if ((err = init_dsp_comm_page(chip))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "init_hw - could not initialize DSP comm page\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) chip->device_id = device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) chip->subdevice_id = subdevice_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) chip->bad_board = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) chip->input_clock_types =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_ADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) chip->digital_modes =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ECHOCAPS_HAS_DIGITAL_MODE_ADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Mona comes in both '301 and '361 flavors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (chip->device_id == DEVICE_ID_56361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) chip->dsp_code_to_load = FW_MONA_361_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) chip->dsp_code_to_load = FW_MONA_301_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if ((err = load_firmware(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) chip->bad_board = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int set_mixer_defaults(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) chip->professional_spdif = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) chip->digital_in_automute = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return init_line_levels(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static u32 detect_input_clocks(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 clocks_from_dsp, clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Map the DSP clock detect bits to the generic driver clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) detect bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) clock_bits = ECHO_CLOCK_BIT_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clock_bits |= ECHO_CLOCK_BIT_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clock_bits |= ECHO_CLOCK_BIT_ADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clock_bits |= ECHO_CLOCK_BIT_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Mona has an ASIC on the PCI card and another ASIC in the external box;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) both need to be loaded. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int load_asic(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) short asic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (chip->asic_loaded)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (chip->device_id == DEVICE_ID_56361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) asic = FW_MONA_361_1_ASIC48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) asic = FW_MONA_301_1_ASIC48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC, asic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) chip->asic_code = asic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Do the external one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_EXTERNAL_ASIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FW_MONA_2_ASIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) err = check_asic_status(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Set up the control register if the load succeeded -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 48 kHz, internal clock, S/PDIF RCA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) err = write_control_reg(chip, control_reg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Depending on what digital mode you want, Mona needs different ASICs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) loaded. This function checks the ASIC needed for the new mode and sees
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if it matches the one already loaded. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int switch_asic(struct echoaudio *chip, char double_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) short asic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Check the clock detect bits to see if this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) a single-speed clock or a double-speed clock; load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) a new ASIC if necessary. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (chip->device_id == DEVICE_ID_56361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (double_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) asic = FW_MONA_361_1_ASIC96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) asic = FW_MONA_361_1_ASIC48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (double_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) asic = FW_MONA_301_1_ASIC96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) asic = FW_MONA_301_1_ASIC48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (asic != chip->asic_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Load the desired ASIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) asic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) chip->asic_code = asic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int set_sample_rate(struct echoaudio *chip, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 control_reg, clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) short asic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) char force_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Only set the clock for internal mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Save the rate anyhow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) chip->comm_page->sample_rate = cpu_to_le32(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) chip->sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Now, check to see if the required ASIC is loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (rate >= 88200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (chip->digital_mode == DIGITAL_MODE_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (chip->device_id == DEVICE_ID_56361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) asic = FW_MONA_361_1_ASIC96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) asic = FW_MONA_301_1_ASIC96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (chip->device_id == DEVICE_ID_56361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) asic = FW_MONA_361_1_ASIC48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) asic = FW_MONA_301_1_ASIC48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) force_write = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (asic != chip->asic_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Load the desired ASIC (load_asic_generic() can sleep) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) asic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) chip->asic_code = asic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) force_write = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Compute the new control register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) control_reg = le32_to_cpu(chip->comm_page->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) control_reg &= GML_CLOCK_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) control_reg &= GML_SPDIF_RATE_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) clock = GML_96KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) clock = GML_88KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) clock = GML_44KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Professional mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (control_reg & GML_SPDIF_PRO_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clock |= GML_SPDIF_SAMPLE_RATE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) GML_SPDIF_SAMPLE_RATE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) clock = GML_22KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clock = GML_16KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case 11025:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) clock = GML_11KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) clock = GML_8KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "set_sample_rate: %d invalid!\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) control_reg |= clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) chip->sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "set_sample_rate: %d clock %d\n", rate, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return write_control_reg(chip, control_reg, force_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int set_input_clock(struct echoaudio *chip, u16 clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 control_reg, clocks_from_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Mask off the clock select bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) control_reg = le32_to_cpu(chip->comm_page->control_register) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) GML_CLOCK_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case ECHO_CLOCK_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) chip->input_clock = ECHO_CLOCK_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return set_sample_rate(chip, chip->sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case ECHO_CLOCK_SPDIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (chip->digital_mode == DIGITAL_MODE_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) err = switch_asic(chip, clocks_from_dsp &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) GML_CLOCK_DETECT_BIT_SPDIF96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) control_reg |= GML_SPDIF_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) control_reg |= GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) control_reg &= ~GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case ECHO_CLOCK_WORD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) err = switch_asic(chip, clocks_from_dsp &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) GML_CLOCK_DETECT_BIT_WORD96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) control_reg |= GML_WORD_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) control_reg |= GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) control_reg &= ~GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case ECHO_CLOCK_ADAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_dbg(chip->card->dev, "Set Mona clock to ADAT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (chip->digital_mode != DIGITAL_MODE_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) control_reg |= GML_ADAT_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) control_reg &= ~GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "Input clock 0x%x not supported for Mona\n", clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) chip->input_clock = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return write_control_reg(chip, control_reg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int err, incompatible_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Set clock to "internal" if it's not compatible with the new mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) incompatible_clock = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case DIGITAL_MODE_SPDIF_OPTICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) case DIGITAL_MODE_SPDIF_RCA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (chip->input_clock == ECHO_CLOCK_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) incompatible_clock = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case DIGITAL_MODE_ADAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (chip->input_clock == ECHO_CLOCK_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) incompatible_clock = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "Digital mode not supported: %d\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (incompatible_clock) { /* Switch to 48KHz, internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) chip->sample_rate = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) set_input_clock(chip, ECHO_CLOCK_INTERNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Clear the current digital mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) control_reg = le32_to_cpu(chip->comm_page->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Tweak the control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case DIGITAL_MODE_SPDIF_OPTICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) control_reg |= GML_SPDIF_OPTICAL_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case DIGITAL_MODE_SPDIF_RCA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* GML_SPDIF_OPTICAL_MODE bit cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case DIGITAL_MODE_ADAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* If the current ASIC is the 96KHz ASIC, switch the ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) and set to 48 KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (chip->asic_code == FW_MONA_361_1_ASIC96 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) chip->asic_code == FW_MONA_301_1_ASIC96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) set_sample_rate(chip, 48000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) control_reg |= GML_ADAT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) control_reg &= ~GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) err = write_control_reg(chip, control_reg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) chip->digital_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_dbg(chip->card->dev, "set_digital_mode to %d\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return incompatible_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags