^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for Echoaudio soundcards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2003-2004 Giuliano Pochini <pochini@shiny.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define ECHO24_FAMILY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define ECHOCARD_MONA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define ECHOCARD_NAME "Mona"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ECHOCARD_HAS_MONITOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ECHOCARD_HAS_ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ECHOCARD_HAS_SUPER_INTERLEAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ECHOCARD_HAS_DIGITAL_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ECHOCARD_HAS_DIGITAL_IN_AUTOMUTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ECHOCARD_HAS_DIGITAL_MODE_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ECHOCARD_HAS_EXTERNAL_CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ECHOCARD_HAS_ADAT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ECHOCARD_HAS_STEREO_BIG_ENDIAN32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Pipe indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PX_ANALOG_OUT 0 /* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PX_DIGITAL_OUT 6 /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PX_ANALOG_IN 14 /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PX_DIGITAL_IN 18 /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PX_NUM 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Bus indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BX_ANALOG_OUT 0 /* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BX_DIGITAL_OUT 6 /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BX_ANALOG_IN 14 /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BX_DIGITAL_IN 18 /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BX_NUM 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "echoaudio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MODULE_FIRMWARE("ea/loader_dsp.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MODULE_FIRMWARE("ea/mona_301_dsp.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MODULE_FIRMWARE("ea/mona_361_dsp.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MODULE_FIRMWARE("ea/mona_301_1_asic_48.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_FIRMWARE("ea/mona_301_1_asic_96.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_FIRMWARE("ea/mona_361_1_asic_48.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MODULE_FIRMWARE("ea/mona_361_1_asic_96.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_FIRMWARE("ea/mona_2_asic.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FW_361_LOADER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FW_MONA_301_DSP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FW_MONA_361_DSP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define FW_MONA_301_1_ASIC48 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FW_MONA_301_1_ASIC96 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FW_MONA_361_1_ASIC48 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FW_MONA_361_1_ASIC96 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FW_MONA_2_ASIC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct firmware card_fw[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {0, "loader_dsp.fw"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {0, "mona_301_dsp.fw"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {0, "mona_361_dsp.fw"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {0, "mona_301_1_asic_48.fw"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {0, "mona_301_1_asic_96.fw"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {0, "mona_361_1_asic_48.fw"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {0, "mona_361_1_asic_96.fw"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {0, "mona_2_asic.fw"}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct pci_device_id snd_echo_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {0x1057, 0x1801, 0xECC0, 0x0070, 0, 0, 0}, /* DSP 56301 Mona rev.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {0x1057, 0x1801, 0xECC0, 0x0071, 0, 0, 0}, /* DSP 56301 Mona rev.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {0x1057, 0x1801, 0xECC0, 0x0072, 0, 0, 0}, /* DSP 56301 Mona rev.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {0x1057, 0x3410, 0xECC0, 0x0070, 0, 0, 0}, /* DSP 56361 Mona rev.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {0x1057, 0x3410, 0xECC0, 0x0071, 0, 0, 0}, /* DSP 56361 Mona rev.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {0x1057, 0x3410, 0xECC0, 0x0072, 0, 0, 0}, /* DSP 56361 Mona rev.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const struct snd_pcm_hardware pcm_hardware_skel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SNDRV_PCM_INFO_SYNC_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .formats = SNDRV_PCM_FMTBIT_U8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SNDRV_PCM_FMTBIT_S24_3LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SNDRV_PCM_FMTBIT_S32_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) SNDRV_PCM_FMTBIT_S32_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .rates = SNDRV_PCM_RATE_8000_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SNDRV_PCM_RATE_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .buffer_bytes_max = 262144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .period_bytes_min = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .period_bytes_max = 131072,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .periods_max = 220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* One page (4k) contains 512 instructions. I don't know if the hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) supports lists longer than this. In this case periods_max=220 is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) safe limit to make sure the list never exceeds 512 instructions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #include "mona_dsp.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #include "echoaudio_dsp.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #include "echoaudio_gml.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #include "echoaudio.c"
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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