^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Copyright Echo Digital Audio Corporation (c) 1998 - 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) www.echoaudio.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) This file is part of Echo Digital Audio's generic driver library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Echo Digital Audio's generic driver library is free software;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) you can redistribute it and/or modify it under the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) the GNU General Public License as published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Foundation, Inc., 59 Temple Place - Suite 330, Boston,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MA 02111-1307, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Translation from C++ and adaptation for use in ALSA-Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) were made by Giuliano Pochini <pochini@shiny.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int write_control_reg(struct echoaudio *chip, u32 value, char force);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int set_input_clock(struct echoaudio *chip, u16 clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int set_professional_spdif(struct echoaudio *chip, char prof);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int set_digital_mode(struct echoaudio *chip, u8 mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int check_asic_status(struct echoaudio *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (snd_BUG_ON((subdevice_id & 0xfff0) != LAYLA24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if ((err = init_dsp_comm_page(chip))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "init_hw - could not initialize DSP comm page\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) chip->device_id = device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) chip->subdevice_id = subdevice_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) chip->bad_board = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) chip->has_midi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) chip->dsp_code_to_load = FW_LAYLA24_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) chip->input_clock_types =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_ADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) chip->digital_modes =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ECHOCAPS_HAS_DIGITAL_MODE_ADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if ((err = load_firmware(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) chip->bad_board = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if ((err = init_line_levels(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int set_mixer_defaults(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) chip->professional_spdif = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) chip->digital_in_automute = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return init_line_levels(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static u32 detect_input_clocks(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 clocks_from_dsp, clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Map the DSP clock detect bits to the generic driver clock detect bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clock_bits = ECHO_CLOCK_BIT_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) clock_bits |= ECHO_CLOCK_BIT_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clock_bits |= ECHO_CLOCK_BIT_ADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clock_bits |= ECHO_CLOCK_BIT_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Layla24 has an ASIC on the PCI card and another ASIC in the external box;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) both need to be loaded. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int load_asic(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (chip->asic_loaded)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Give the DSP a few milliseconds to settle down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Load the ASIC for the PCI card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) err = load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_PCI_CARD_ASIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) FW_LAYLA24_1_ASIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) chip->asic_code = FW_LAYLA24_2S_ASIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Now give the new ASIC a little time to set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Do the external one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) err = load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) FW_LAYLA24_2S_ASIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Now give the external ASIC a little time to set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* See if it worked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) err = check_asic_status(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Set up the control register if the load succeeded -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 48 kHz, internal clock, S/PDIF RCA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) err = write_control_reg(chip, GML_CONVERTER_ENABLE | GML_48KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int set_sample_rate(struct echoaudio *chip, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 control_reg, clock, base_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (snd_BUG_ON(rate >= 50000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) chip->digital_mode == DIGITAL_MODE_ADAT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Only set the clock for internal mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_warn(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Save the rate anyhow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) chip->comm_page->sample_rate = cpu_to_le32(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) chip->sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Get the control register & clear the appropriate bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) control_reg = le32_to_cpu(chip->comm_page->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) clock = GML_96KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) clock = GML_88KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) clock = GML_44KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Professional mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (control_reg & GML_SPDIF_PRO_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clock |= GML_SPDIF_SAMPLE_RATE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) GML_SPDIF_SAMPLE_RATE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) clock = GML_22KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) clock = GML_16KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case 11025:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) clock = GML_11KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) clock = GML_8KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* If this is a non-standard rate, then the driver needs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) use Layla24's special "continuous frequency" mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) clock = LAYLA24_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (rate > 50000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) base_rate = rate >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) control_reg |= GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) base_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (base_rate < 25000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) base_rate = 25000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) chip->comm_page->sample_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) cpu_to_le32(LAYLA24_MAGIC_NUMBER / base_rate - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) send_vector(chip, DSP_VC_SET_LAYLA24_FREQUENCY_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) control_reg |= clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) chip->sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "set_sample_rate: %d clock %d\n", rate, control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return write_control_reg(chip, control_reg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int set_input_clock(struct echoaudio *chip, u16 clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 control_reg, clocks_from_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Mask off the clock select bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) control_reg = le32_to_cpu(chip->comm_page->control_register) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) GML_CLOCK_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Pick the new clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case ECHO_CLOCK_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) chip->input_clock = ECHO_CLOCK_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return set_sample_rate(chip, chip->sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case ECHO_CLOCK_SPDIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (chip->digital_mode == DIGITAL_MODE_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) control_reg |= GML_SPDIF_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Layla24 doesn't support 96KHz S/PDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) control_reg &= ~GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case ECHO_CLOCK_WORD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) control_reg |= GML_WORD_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) control_reg |= GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) control_reg &= ~GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case ECHO_CLOCK_ADAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (chip->digital_mode != DIGITAL_MODE_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) control_reg |= GML_ADAT_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) control_reg &= ~GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "Input clock 0x%x not supported for Layla24\n", clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) chip->input_clock = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return write_control_reg(chip, control_reg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Depending on what digital mode you want, Layla24 needs different ASICs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) loaded. This function checks the ASIC needed for the new mode and sees
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if it matches the one already loaded. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int switch_asic(struct echoaudio *chip, short asic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) s8 *monitors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Check to see if this is already loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (asic != chip->asic_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) monitors = kmemdup(chip->comm_page->monitors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MONITOR_ARRAY_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (! monitors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) memset(chip->comm_page->monitors, ECHOGAIN_MUTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MONITOR_ARRAY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Load the desired ASIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) asic) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) memcpy(chip->comm_page->monitors, monitors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MONITOR_ARRAY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) kfree(monitors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) chip->asic_code = asic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) memcpy(chip->comm_page->monitors, monitors, MONITOR_ARRAY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) kfree(monitors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int err, incompatible_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) short asic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Set clock to "internal" if it's not compatible with the new mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) incompatible_clock = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case DIGITAL_MODE_SPDIF_OPTICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case DIGITAL_MODE_SPDIF_RCA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (chip->input_clock == ECHO_CLOCK_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) incompatible_clock = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) asic = FW_LAYLA24_2S_ASIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case DIGITAL_MODE_ADAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (chip->input_clock == ECHO_CLOCK_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) incompatible_clock = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) asic = FW_LAYLA24_2A_ASIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "Digital mode not supported: %d\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (incompatible_clock) { /* Switch to 48KHz, internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) chip->sample_rate = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) set_input_clock(chip, ECHO_CLOCK_INTERNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* switch_asic() can sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (switch_asic(chip, asic) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Tweak the control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) control_reg = le32_to_cpu(chip->comm_page->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case DIGITAL_MODE_SPDIF_OPTICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) control_reg |= GML_SPDIF_OPTICAL_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case DIGITAL_MODE_SPDIF_RCA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* GML_SPDIF_OPTICAL_MODE bit cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case DIGITAL_MODE_ADAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) control_reg |= GML_ADAT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) control_reg &= ~GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) err = write_control_reg(chip, control_reg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) chip->digital_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_dbg(chip->card->dev, "set_digital_mode to %d\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return incompatible_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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