^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Copyright Echo Digital Audio Corporation (c) 1998 - 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) www.echoaudio.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) This file is part of Echo Digital Audio's generic driver library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Echo Digital Audio's generic driver library is free software;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) you can redistribute it and/or modify it under the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) the GNU General Public License as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Foundation, Inc., 59 Temple Place - Suite 330, Boston,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MA 02111-1307, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Translation from C++ and adaptation for use in ALSA-Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) were made by Giuliano Pochini <pochini@shiny.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int read_dsp(struct echoaudio *chip, u32 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int set_professional_spdif(struct echoaudio *chip, char prof);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int check_asic_status(struct echoaudio *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int update_flags(struct echoaudio *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (snd_BUG_ON((subdevice_id & 0xfff0) != LAYLA20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if ((err = init_dsp_comm_page(chip))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "init_hw - could not initialize DSP comm page\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) chip->device_id = device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) chip->subdevice_id = subdevice_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) chip->bad_board = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) chip->has_midi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) chip->dsp_code_to_load = FW_LAYLA20_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) chip->input_clock_types =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_SUPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) chip->output_clock_types =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_SUPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if ((err = load_firmware(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) chip->bad_board = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int set_mixer_defaults(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) chip->professional_spdif = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return init_line_levels(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static u32 detect_input_clocks(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 clocks_from_dsp, clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Map the DSP clock detect bits to the generic driver clock detect bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clock_bits = ECHO_CLOCK_BIT_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (clocks_from_dsp & GLDM_CLOCK_DETECT_BIT_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) clock_bits |= ECHO_CLOCK_BIT_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (clocks_from_dsp & GLDM_CLOCK_DETECT_BIT_WORD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (clocks_from_dsp & GLDM_CLOCK_DETECT_BIT_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clock_bits |= ECHO_CLOCK_BIT_SUPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) clock_bits |= ECHO_CLOCK_BIT_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* ASIC status check - some cards have one or two ASICs that need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) loaded. Once that load is complete, this function is called to see if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) the load was successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) If this load fails, it does not necessarily mean that the hardware is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) defective - the external box may be disconnected or turned off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) This routine sometimes fails for Layla20; for Layla20, the loop runs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 5 times and succeeds if it wins on three of the loops. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int check_asic_status(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 asic_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int goodcnt, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) chip->asic_loaded = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) for (i = goodcnt = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) send_vector(chip, DSP_VC_TEST_ASIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* The DSP will return a value to indicate whether or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) the ASIC is currently loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (read_dsp(chip, &asic_status) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "check_asic_status: failed on read_dsp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (asic_status == ASIC_ALREADY_LOADED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (++goodcnt == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) chip->asic_loaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Layla20 has an ASIC in the external box */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int load_asic(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (chip->asic_loaded)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) err = load_asic_generic(chip, DSP_FNC_LOAD_LAYLA_ASIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FW_LAYLA20_ASIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Check if ASIC is alive and well. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return check_asic_status(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int set_sample_rate(struct echoaudio *chip, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (snd_BUG_ON(rate < 8000 || rate > 50000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Only set the clock for internal mode. Do not return failure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) simply treat it as a non-event. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_warn(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) chip->comm_page->sample_rate = cpu_to_le32(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) chip->sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_dbg(chip->card->dev, "set_sample_rate(%d)\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) chip->sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) chip->comm_page->sample_rate = cpu_to_le32(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return send_vector(chip, DSP_VC_SET_LAYLA_SAMPLE_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int set_input_clock(struct echoaudio *chip, u16 clock_source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u16 clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) switch (clock_source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case ECHO_CLOCK_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rate = chip->sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clock = LAYLA20_CLOCK_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case ECHO_CLOCK_SPDIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) clock = LAYLA20_CLOCK_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case ECHO_CLOCK_WORD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clock = LAYLA20_CLOCK_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case ECHO_CLOCK_SUPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) clock = LAYLA20_CLOCK_SUPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "Input clock 0x%x not supported for Layla24\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) clock_source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) chip->input_clock = clock_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) chip->comm_page->input_clock = cpu_to_le16(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) send_vector(chip, DSP_VC_UPDATE_CLOCKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) set_sample_rate(chip, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int set_output_clock(struct echoaudio *chip, u16 clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case ECHO_CLOCK_SUPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) clock = LAYLA20_OUTPUT_CLOCK_SUPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case ECHO_CLOCK_WORD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) clock = LAYLA20_OUTPUT_CLOCK_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_err(chip->card->dev, "set_output_clock wrong clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) chip->comm_page->output_clock = cpu_to_le16(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) chip->output_clock = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return send_vector(chip, DSP_VC_UPDATE_CLOCKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Set input bus gain (one unit is 0.5dB !) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int set_input_gain(struct echoaudio *chip, u16 input, int gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (snd_BUG_ON(input >= num_busses_in(chip)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) chip->input_gain[input] = gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) gain += GL20_INPUT_GAIN_MAGIC_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) chip->comm_page->line_in_level[input] = gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Tell the DSP to reread the flags from the comm page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int update_flags(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return send_vector(chip, DSP_VC_UPDATE_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int set_professional_spdif(struct echoaudio *chip, char prof)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (prof)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) chip->comm_page->flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) cpu_to_le32(DSP_FLAG_PROFESSIONAL_SPDIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) chip->comm_page->flags &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ~cpu_to_le32(DSP_FLAG_PROFESSIONAL_SPDIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) chip->professional_spdif = prof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return update_flags(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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