Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)    All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)    www.echoaudio.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)    This file is part of Echo Digital Audio's generic driver library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)    Echo Digital Audio's generic driver library is free software;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)    you can redistribute it and/or modify it under the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)    the GNU General Public License as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)    Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)    This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)    but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)    GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)    You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)    along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)    MA  02111-1307, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)    *************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  Translation from C++ and adaptation for use in ALSA-Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  were made by Giuliano Pochini <pochini@shiny.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int write_control_reg(struct echoaudio *chip, u32 value, char force);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static int set_input_clock(struct echoaudio *chip, u16 clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static int set_professional_spdif(struct echoaudio *chip, char prof);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static int set_digital_mode(struct echoaudio *chip, u8 mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static int check_asic_status(struct echoaudio *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	if (snd_BUG_ON((subdevice_id & 0xfff0) != GINA24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	if ((err = init_dsp_comm_page(chip))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			"init_hw - could not initialize DSP comm page\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	chip->device_id = device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	chip->subdevice_id = subdevice_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	chip->bad_board = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	chip->input_clock_types =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		ECHO_CLOCK_BIT_ESYNC | ECHO_CLOCK_BIT_ESYNC96 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		ECHO_CLOCK_BIT_ADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/* Gina24 comes in both '301 and '361 flavors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (chip->device_id == DEVICE_ID_56361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		chip->dsp_code_to_load = FW_GINA24_361_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		chip->digital_modes =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			ECHOCAPS_HAS_DIGITAL_MODE_ADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		chip->dsp_code_to_load = FW_GINA24_301_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		chip->digital_modes =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			ECHOCAPS_HAS_DIGITAL_MODE_ADAT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_CDROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if ((err = load_firmware(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	chip->bad_board = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int set_mixer_defaults(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	chip->professional_spdif = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	chip->digital_in_automute = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return init_line_levels(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static u32 detect_input_clocks(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u32 clocks_from_dsp, clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* Map the DSP clock detect bits to the generic driver clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	   detect bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	clock_bits = ECHO_CLOCK_BIT_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		clock_bits |= ECHO_CLOCK_BIT_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		clock_bits |= ECHO_CLOCK_BIT_ADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ESYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		clock_bits |= ECHO_CLOCK_BIT_ESYNC | ECHO_CLOCK_BIT_ESYNC96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Gina24 has an ASIC on the PCI card which must be loaded for anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) interesting to happen. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int load_asic(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32 control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	short asic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (chip->asic_loaded)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/* Give the DSP a few milliseconds to settle down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* Pick the correct ASIC for '301 or '361 Gina24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (chip->device_id == DEVICE_ID_56361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		asic = FW_GINA24_361_ASIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		asic = FW_GINA24_301_ASIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	err = load_asic_generic(chip, DSP_FNC_LOAD_GINA24_ASIC, asic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	chip->asic_code = asic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	/* Now give the new ASIC a little time to set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	/* See if it worked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	err = check_asic_status(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* Set up the control register if the load succeeded -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	   48 kHz, internal clock, S/PDIF RCA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		err = write_control_reg(chip, control_reg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int set_sample_rate(struct echoaudio *chip, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u32 control_reg, clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (snd_BUG_ON(rate >= 50000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		       chip->digital_mode == DIGITAL_MODE_ADAT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* Only set the clock for internal mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		dev_warn(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		/* Save the rate anyhow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		chip->comm_page->sample_rate = cpu_to_le32(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		chip->sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	control_reg = le32_to_cpu(chip->comm_page->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		clock = GML_96KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		clock = GML_88KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		clock = GML_44KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		/* Professional mode ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		if (control_reg & GML_SPDIF_PRO_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			clock |= GML_SPDIF_SAMPLE_RATE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			GML_SPDIF_SAMPLE_RATE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		clock = GML_22KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		clock = GML_16KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	case 11025:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		clock = GML_11KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		clock = GML_8KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			"set_sample_rate: %d invalid!\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	control_reg |= clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	chip->comm_page->sample_rate = cpu_to_le32(rate);	/* ignored by the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	chip->sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	dev_dbg(chip->card->dev, "set_sample_rate: %d clock %d\n", rate, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return write_control_reg(chip, control_reg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int set_input_clock(struct echoaudio *chip, u16 clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	u32 control_reg, clocks_from_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* Mask off the clock select bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	control_reg = le32_to_cpu(chip->comm_page->control_register) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		GML_CLOCK_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	case ECHO_CLOCK_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		chip->input_clock = ECHO_CLOCK_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return set_sample_rate(chip, chip->sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	case ECHO_CLOCK_SPDIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		if (chip->digital_mode == DIGITAL_MODE_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		control_reg |= GML_SPDIF_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			control_reg |= GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			control_reg &= ~GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	case ECHO_CLOCK_ADAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		if (chip->digital_mode != DIGITAL_MODE_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		control_reg |= GML_ADAT_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		control_reg &= ~GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	case ECHO_CLOCK_ESYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		control_reg |= GML_ESYNC_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		control_reg &= ~GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	case ECHO_CLOCK_ESYNC96:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		control_reg |= GML_ESYNC_CLOCK | GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			"Input clock 0x%x not supported for Gina24\n", clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	chip->input_clock = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	return write_control_reg(chip, control_reg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	u32 control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	int err, incompatible_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/* Set clock to "internal" if it's not compatible with the new mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	incompatible_clock = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	case DIGITAL_MODE_SPDIF_OPTICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	case DIGITAL_MODE_SPDIF_CDROM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	case DIGITAL_MODE_SPDIF_RCA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		if (chip->input_clock == ECHO_CLOCK_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			incompatible_clock = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	case DIGITAL_MODE_ADAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		if (chip->input_clock == ECHO_CLOCK_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			incompatible_clock = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			"Digital mode not supported: %d\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (incompatible_clock) {	/* Switch to 48KHz, internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		chip->sample_rate = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		set_input_clock(chip, ECHO_CLOCK_INTERNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	/* Clear the current digital mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	control_reg = le32_to_cpu(chip->comm_page->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	/* Tweak the control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	case DIGITAL_MODE_SPDIF_OPTICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		control_reg |= GML_SPDIF_OPTICAL_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	case DIGITAL_MODE_SPDIF_CDROM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		/* '361 Gina24 cards do not have the S/PDIF CD-ROM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		if (chip->device_id == DEVICE_ID_56301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			control_reg |= GML_SPDIF_CDROM_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	case DIGITAL_MODE_SPDIF_RCA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		/* GML_SPDIF_OPTICAL_MODE bit cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	case DIGITAL_MODE_ADAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		control_reg |= GML_ADAT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		control_reg &= ~GML_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	err = write_control_reg(chip, control_reg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	chip->digital_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		"set_digital_mode to %d\n", chip->digital_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return incompatible_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }