^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Copyright Echo Digital Audio Corporation (c) 1998 - 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) www.echoaudio.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) This file is part of Echo Digital Audio's generic driver library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Echo Digital Audio's generic driver library is free software;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) you can redistribute it and/or modify it under the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) the GNU General Public License as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Foundation, Inc., 59 Temple Place - Suite 330, Boston,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MA 02111-1307, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Translation from C++ and adaptation for use in ALSA-Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) were made by Giuliano Pochini <pochini@shiny.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int set_professional_spdif(struct echoaudio *chip, char prof);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int update_flags(struct echoaudio *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (snd_BUG_ON((subdevice_id & 0xfff0) != GINA20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if ((err = init_dsp_comm_page(chip))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "init_hw - could not initialize DSP comm page\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) chip->device_id = device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) chip->subdevice_id = subdevice_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) chip->bad_board = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) chip->dsp_code_to_load = FW_GINA20_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) chip->spdif_status = GD_SPDIF_STATUS_UNDEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) chip->clock_state = GD_CLOCK_UNDEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Since this card has no ASIC, mark it as loaded so everything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) works OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) chip->asic_loaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) chip->input_clock_types = ECHO_CLOCK_BIT_INTERNAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ECHO_CLOCK_BIT_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if ((err = load_firmware(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) chip->bad_board = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int set_mixer_defaults(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) chip->professional_spdif = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return init_line_levels(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static u32 detect_input_clocks(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 clocks_from_dsp, clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Map the DSP clock detect bits to the generic driver clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) detect bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clock_bits = ECHO_CLOCK_BIT_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (clocks_from_dsp & GLDM_CLOCK_DETECT_BIT_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) clock_bits |= ECHO_CLOCK_BIT_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* The Gina20 has no ASIC. Just do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int load_asic(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int set_sample_rate(struct echoaudio *chip, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 clock_state, spdif_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clock_state = GD_CLOCK_44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) spdif_status = GD_SPDIF_STATUS_44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clock_state = GD_CLOCK_48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) spdif_status = GD_SPDIF_STATUS_48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clock_state = GD_CLOCK_NOCHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) spdif_status = GD_SPDIF_STATUS_NOCHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (chip->clock_state == clock_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clock_state = GD_CLOCK_NOCHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (spdif_status == chip->spdif_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) spdif_status = GD_SPDIF_STATUS_NOCHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) chip->comm_page->sample_rate = cpu_to_le32(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) chip->comm_page->gd_clock_state = clock_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) chip->comm_page->gd_spdif_status = spdif_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) chip->comm_page->gd_resampler_state = 3; /* magic number - should always be 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Save the new audio state if it changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (clock_state != GD_CLOCK_NOCHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) chip->clock_state = clock_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (spdif_status != GD_SPDIF_STATUS_NOCHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) chip->spdif_status = spdif_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) chip->sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return send_vector(chip, DSP_VC_SET_GD_AUDIO_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int set_input_clock(struct echoaudio *chip, u16 clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case ECHO_CLOCK_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Reset the audio state to unknown (just in case) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) chip->clock_state = GD_CLOCK_UNDEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) chip->spdif_status = GD_SPDIF_STATUS_UNDEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) set_sample_rate(chip, chip->sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) chip->input_clock = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case ECHO_CLOCK_SPDIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) chip->comm_page->gd_clock_state = GD_CLOCK_SPDIFIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) chip->comm_page->gd_spdif_status = GD_SPDIF_STATUS_NOCHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) send_vector(chip, DSP_VC_SET_GD_AUDIO_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) chip->clock_state = GD_CLOCK_SPDIFIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) chip->input_clock = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Set input bus gain (one unit is 0.5dB !) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int set_input_gain(struct echoaudio *chip, u16 input, int gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (snd_BUG_ON(input >= num_busses_in(chip)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) chip->input_gain[input] = gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) gain += GL20_INPUT_GAIN_MAGIC_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) chip->comm_page->line_in_level[input] = gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Tell the DSP to reread the flags from the comm page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int update_flags(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return send_vector(chip, DSP_VC_UPDATE_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int set_professional_spdif(struct echoaudio *chip, char prof)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (prof)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) chip->comm_page->flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) cpu_to_le32(DSP_FLAG_PROFESSIONAL_SPDIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) chip->comm_page->flags &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ~cpu_to_le32(DSP_FLAG_PROFESSIONAL_SPDIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) chip->professional_spdif = prof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return update_flags(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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