Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)    All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)    www.echoaudio.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)    This file is part of Echo Digital Audio's generic driver library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)    Echo Digital Audio's generic driver library is free software;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)    you can redistribute it and/or modify it under the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)    the GNU General Public License as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)    Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)    This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)    but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)    GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)    You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)    along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)    MA  02111-1307, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)    *************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  Translation from C++ and adaptation for use in ALSA-Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  were made by Giuliano Pochini <pochini@shiny.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* These functions are common for Gina24, Layla24 and Mona cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* ASIC status check - some cards have one or two ASICs that need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) loaded.  Once that load is complete, this function is called to see if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) the load was successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) If this load fails, it does not necessarily mean that the hardware is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) defective - the external box may be disconnected or turned off. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static int check_asic_status(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32 asic_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	send_vector(chip, DSP_VC_TEST_ASIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/* The DSP will return a value to indicate whether or not the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	   ASIC is currently loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (read_dsp(chip, &asic_status) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			"check_asic_status: failed on read_dsp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		chip->asic_loaded = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	chip->asic_loaded = (asic_status == ASIC_ALREADY_LOADED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return chip->asic_loaded ? 0 : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* Most configuration of Gina24, Layla24, or Mona is accomplished by writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) the control register.  write_control_reg sends the new control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) value to the DSP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static int write_control_reg(struct echoaudio *chip, u32 value, char force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	__le32 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* Handle the digital input auto-mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (chip->digital_in_automute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		value |= GML_DIGITAL_IN_AUTO_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		value &= ~GML_DIGITAL_IN_AUTO_MUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	dev_dbg(chip->card->dev, "write_control_reg: 0x%x\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/* Write the control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	reg_value = cpu_to_le32(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (reg_value != chip->comm_page->control_register || force) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		chip->comm_page->control_register = reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return send_vector(chip, DSP_VC_WRITE_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) /* Gina24, Layla24, and Mona support digital input auto-mute.  If the digital
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) input auto-mute is enabled, the DSP will only enable the digital inputs if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) the card is syncing to a valid clock on the ADAT or S/PDIF inputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) If the auto-mute is disabled, the digital inputs are enabled regardless of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) what the input clock is set or what is connected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static int set_input_auto_mute(struct echoaudio *chip, int automute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	dev_dbg(chip->card->dev, "set_input_auto_mute %d\n", automute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	chip->digital_in_automute = automute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/* Re-set the input clock to the current value - indirectly causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	the auto-mute flag to be sent to the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return set_input_clock(chip, chip->input_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* S/PDIF coax / S/PDIF optical / ADAT - switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int set_digital_mode(struct echoaudio *chip, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	u8 previous_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int err, i, o;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (chip->bad_board)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* All audio channels must be closed before changing the digital mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (snd_BUG_ON(chip->pipe_alloc_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (snd_BUG_ON(!(chip->digital_modes & (1 << mode))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	previous_mode = chip->digital_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	err = dsp_set_digital_mode(chip, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/* If we successfully changed the digital mode from or to ADAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	   then make sure all output, input and monitor levels are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	   updated by the DSP comm object. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (err >= 0 && previous_mode != mode &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	    (previous_mode == DIGITAL_MODE_ADAT || mode == DIGITAL_MODE_ADAT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		for (o = 0; o < num_busses_out(chip); o++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			for (i = 0; i < num_busses_in(chip); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 				set_monitor_gain(chip, o, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 						 chip->monitor_gain[o][i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #ifdef ECHOCARD_HAS_INPUT_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		for (i = 0; i < num_busses_in(chip); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			set_input_gain(chip, i, chip->input_gain[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		update_input_line_level(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		for (o = 0; o < num_busses_out(chip); o++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			set_output_gain(chip, o, chip->output_gain[o]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		update_output_line_level(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Set the S/PDIF output format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int set_professional_spdif(struct echoaudio *chip, char prof)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u32 control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* Clear the current S/PDIF flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	control_reg = le32_to_cpu(chip->comm_page->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	control_reg &= GML_SPDIF_FORMAT_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* Set the new S/PDIF flags depending on the mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	control_reg |= GML_SPDIF_TWO_CHANNEL | GML_SPDIF_24_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		GML_SPDIF_COPY_PERMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (prof) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		/* Professional mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		control_reg |= GML_SPDIF_PRO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		switch (chip->sample_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			control_reg |= GML_SPDIF_SAMPLE_RATE0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				GML_SPDIF_SAMPLE_RATE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			control_reg |= GML_SPDIF_SAMPLE_RATE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			control_reg |= GML_SPDIF_SAMPLE_RATE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		/* Consumer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		switch (chip->sample_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			control_reg |= GML_SPDIF_SAMPLE_RATE0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				GML_SPDIF_SAMPLE_RATE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			control_reg |= GML_SPDIF_SAMPLE_RATE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if ((err = write_control_reg(chip, control_reg, false)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	chip->professional_spdif = prof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	dev_dbg(chip->card->dev, "set_professional_spdif to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		prof ? "Professional" : "Consumer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }