^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Copyright Echo Digital Audio Corporation (c) 1998 - 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) www.echoaudio.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) This file is part of Echo Digital Audio's generic driver library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Echo Digital Audio's generic driver library is free software;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) you can redistribute it and/or modify it under the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) the GNU General Public License as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Foundation, Inc., 59 Temple Place - Suite 330, Boston,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MA 02111-1307, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Translation from C++ and adaptation for use in ALSA-Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) were made by Giuliano Pochini <pochini@shiny.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifndef _ECHO_DSP_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define _ECHO_DSP_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /**** Echogals: Darla20, Gina20, Layla20, and Darla24 ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #if defined(ECHOGALS_FAMILY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NUM_ASIC_TESTS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define READ_DSP_TIMEOUT 1000000L /* one second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /**** Echo24: Gina24, Layla24, Mona, Mia, Mia-midi ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #elif defined(ECHO24_FAMILY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DSP_56361 /* Some Echo24 cards use the 56361 DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define READ_DSP_TIMEOUT 100000L /* .1 second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /**** 3G: Gina3G, Layla3G ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #elif defined(ECHO3G_FAMILY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DSP_56361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define READ_DSP_TIMEOUT 100000L /* .1 second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MIN_MTC_1X_RATE 32000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /**** Indigo: Indigo, Indigo IO, Indigo DJ ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #elif defined(INDIGO_FAMILY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DSP_56361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define READ_DSP_TIMEOUT 100000L /* .1 second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #error No family is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Max inputs and outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DSP_MAXAUDIOINPUTS 16 /* Max audio input channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DSP_MAXAUDIOOUTPUTS 16 /* Max audio output channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DSP_MAXPIPES 32 /* Max total pipes (input + output) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * These are the offsets for the memory-mapped DSP registers; the DSP base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * address is treated as the start of a u32 array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CHI32_CONTROL_REG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CHI32_STATUS_REG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CHI32_VECTOR_REG 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CHI32_DATA_REG 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Interesting bits within the DSP registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CHI32_VECTOR_BUSY 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CHI32_STATUS_REG_HF3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CHI32_STATUS_REG_HF4 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CHI32_STATUS_REG_HF5 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CHI32_STATUS_HOST_READ_FULL 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CHI32_STATUS_HOST_WRITE_EMPTY 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CHI32_STATUS_IRQ 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * DSP commands sent via slave mode; these are sent to the DSP by write_dsp()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DSP_FNC_SET_COMMPAGE_ADDR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DSP_FNC_LOAD_LAYLA_ASIC 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DSP_FNC_LOAD_GINA24_ASIC 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DSP_FNC_LOAD_MONA_PCI_CARD_ASIC 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DSP_FNC_LOAD_LAYLA24_PCI_CARD_ASIC 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DSP_FNC_LOAD_MONA_EXTERNAL_ASIC 0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC 0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DSP_FNC_LOAD_3G_ASIC 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Defines to handle the MIDI input state engine; these are used to properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * extract MIDI time code bytes and their timestamps from the MIDI input stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MIDI_IN_STATE_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MIDI_IN_STATE_TS_HIGH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MIDI_IN_STATE_TS_LOW 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MIDI_IN_STATE_F1_DATA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MIDI_IN_SKIP_DATA (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) Setting the sample rates on Layla24 is somewhat schizophrenic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) For standard rates, it works exactly like Mona and Gina24. That is, for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 8, 11.025, 16, 22.05, 32, 44.1, 48, 88.2, and 96 kHz, you just set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) appropriate bits in the control register and write the control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) In order to support MIDI time code sync (and possibly SMPTE LTC sync in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) the future), Layla24 also has "continuous sample rate mode". In this mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) Layla24 can generate any sample rate between 25 and 50 kHz inclusive, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 50 to 100 kHz inclusive for double speed mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) To use continuous mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) -Set the clock select bits in the control register to 0xe (see the #define
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) -Set double-speed mode if you want to use sample rates above 50 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) -Write the control register as you would normally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) -Now, you need to set the frequency register. First, you need to determine the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) value for the frequency register. This is given by the following formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) frequency_reg = (LAYLA24_MAGIC_NUMBER / sample_rate) - 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) Note the #define below for the magic number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) -Wait for the DSP handshake
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) -Write the frequency_reg value to the .SampleRate field of the comm page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) -Send the vector command SET_LAYLA24_FREQUENCY_REG (see vmonkey.h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) Once you have set the control register up for continuous mode, you can just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) write the frequency register to change the sample rate. This could be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) used for MIDI time code sync. For MTC sync, the control register is set for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) continuous mode. The driver then just keeps writing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SET_LAYLA24_FREQUENCY_REG command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) -----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define LAYLA24_MAGIC_NUMBER 677376000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define LAYLA24_CONTINUOUS_CLOCK 0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * DSP vector commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DSP_VC_RESET 0x80ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #ifndef DSP_56361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DSP_VC_ACK_INT 0x8073
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DSP_VC_SET_VMIXER_GAIN 0x0000 /* Not used, only for compile */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DSP_VC_START_TRANSFER 0x0075 /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DSP_VC_METERS_ON 0x0079
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DSP_VC_METERS_OFF 0x007b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DSP_VC_UPDATE_OUTVOL 0x007d /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DSP_VC_UPDATE_INGAIN 0x007f /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DSP_VC_ADD_AUDIO_BUFFER 0x0081 /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DSP_VC_TEST_ASIC 0x00eb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DSP_VC_UPDATE_CLOCKS 0x00ef /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DSP_VC_SET_LAYLA_SAMPLE_RATE 0x00f1 /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DSP_VC_SET_GD_AUDIO_STATE 0x00f1 /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DSP_VC_WRITE_CONTROL_REG 0x00f1 /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define DSP_VC_MIDI_WRITE 0x00f5 /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DSP_VC_STOP_TRANSFER 0x00f7 /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DSP_VC_UPDATE_FLAGS 0x00fd /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DSP_VC_GO_COMATOSE 0x00f9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #else /* !DSP_56361 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Vector commands for families that use either the 56301 or 56361 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define DSP_VC_ACK_INT 0x80F5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define DSP_VC_SET_VMIXER_GAIN 0x00DB /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DSP_VC_START_TRANSFER 0x00DD /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DSP_VC_METERS_ON 0x00EF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define DSP_VC_METERS_OFF 0x00F1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DSP_VC_UPDATE_OUTVOL 0x00E3 /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DSP_VC_UPDATE_INGAIN 0x00E5 /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DSP_VC_ADD_AUDIO_BUFFER 0x00E1 /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DSP_VC_TEST_ASIC 0x00ED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DSP_VC_UPDATE_CLOCKS 0x00E9 /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DSP_VC_SET_LAYLA24_FREQUENCY_REG 0x00E9 /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DSP_VC_SET_LAYLA_SAMPLE_RATE 0x00EB /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DSP_VC_SET_GD_AUDIO_STATE 0x00EB /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DSP_VC_WRITE_CONTROL_REG 0x00EB /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DSP_VC_MIDI_WRITE 0x00E7 /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DSP_VC_STOP_TRANSFER 0x00DF /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DSP_VC_UPDATE_FLAGS 0x00FB /* Handshke rqd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define DSP_VC_GO_COMATOSE 0x00d9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #endif /* !DSP_56361 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * Timeouts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define HANDSHAKE_TIMEOUT 20000 /* send_vector command timeout (20ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define VECTOR_BUSY_TIMEOUT 100000 /* 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MIDI_OUT_DELAY_USEC 2000 /* How long to wait after MIDI fills up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * Flags for .Flags field in the comm page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DSP_FLAG_MIDI_INPUT 0x0001 /* Enable MIDI input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define DSP_FLAG_SPDIF_NONAUDIO 0x0002 /* Sets the "non-audio" bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * in the S/PDIF out status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * bits. Clear this flag for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * audio data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * set it for AC3 or WMA or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * some such */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DSP_FLAG_PROFESSIONAL_SPDIF 0x0008 /* 1 Professional, 0 Consumer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * Clock detect bits reported by the DSP for Gina20, Layla20, Darla24, and Mia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define GLDM_CLOCK_DETECT_BIT_WORD 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define GLDM_CLOCK_DETECT_BIT_SUPER 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define GLDM_CLOCK_DETECT_BIT_SPDIF 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define GLDM_CLOCK_DETECT_BIT_ESYNC 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Clock detect bits reported by the DSP for Gina24, Mona, and Layla24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define GML_CLOCK_DETECT_BIT_WORD96 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define GML_CLOCK_DETECT_BIT_WORD48 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define GML_CLOCK_DETECT_BIT_SPDIF48 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define GML_CLOCK_DETECT_BIT_SPDIF96 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define GML_CLOCK_DETECT_BIT_WORD (GML_CLOCK_DETECT_BIT_WORD96 | GML_CLOCK_DETECT_BIT_WORD48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define GML_CLOCK_DETECT_BIT_SPDIF (GML_CLOCK_DETECT_BIT_SPDIF48 | GML_CLOCK_DETECT_BIT_SPDIF96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define GML_CLOCK_DETECT_BIT_ESYNC 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define GML_CLOCK_DETECT_BIT_ADAT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * Layla clock numbers to send to DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define LAYLA20_CLOCK_INTERNAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define LAYLA20_CLOCK_SPDIF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define LAYLA20_CLOCK_WORD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define LAYLA20_CLOCK_SUPER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Gina/Darla clock states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define GD_CLOCK_NOCHANGE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define GD_CLOCK_44 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define GD_CLOCK_48 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define GD_CLOCK_SPDIFIN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define GD_CLOCK_UNDEF 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Gina/Darla S/PDIF status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define GD_SPDIF_STATUS_NOCHANGE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define GD_SPDIF_STATUS_44 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define GD_SPDIF_STATUS_48 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define GD_SPDIF_STATUS_UNDEF 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * Layla20 output clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define LAYLA20_OUTPUT_CLOCK_SUPER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define LAYLA20_OUTPUT_CLOCK_WORD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) Magic constants for the Darla24 hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define GD24_96000 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define GD24_48000 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define GD24_44100 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define GD24_32000 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define GD24_22050 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define GD24_16000 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define GD24_11025 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define GD24_8000 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define GD24_88200 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define GD24_EXT_SYNC 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * Return values from the DSP when ASIC is loaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define ASIC_ALREADY_LOADED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define ASIC_NOT_LOADED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * DSP Audio formats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * These are the audio formats that the DSP can transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * via input and output pipes. LE means little-endian,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * BE means big-endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * DSP_AUDIOFORM_MS_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * 8-bit mono unsigned samples. For playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * mono data is duplicated out the left and right channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * of the output bus. The "MS" part of the name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * means mono->stereo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * DSP_AUDIOFORM_MS_16LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * 16-bit signed little-endian mono samples. Playback works
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * like the previous code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * DSP_AUDIOFORM_MS_24LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * 24-bit signed little-endian mono samples. Data is packed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * three bytes per sample; if you had two samples 0x112233 and 0x445566
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * they would be stored in memory like this: 33 22 11 66 55 44.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * DSP_AUDIOFORM_MS_32LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * 24-bit signed little-endian mono samples in a 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * container. In other words, each sample is a 32-bit signed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * integer, where the actual audio data is left-justified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * in the 32 bits and only the 24 most significant bits are valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * DSP_AUDIOFORM_SS_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * DSP_AUDIOFORM_SS_16LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * DSP_AUDIOFORM_SS_24LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * DSP_AUDIOFORM_SS_32LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * Like the previous ones, except now with stereo interleaved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * data. "SS" means stereo->stereo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * DSP_AUDIOFORM_MM_32LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Similar to DSP_AUDIOFORM_MS_32LE, except that the mono
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * data is not duplicated out both the left and right outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * This mode is used by the ASIO driver. Here, "MM" means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * mono->mono.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * DSP_AUDIOFORM_MM_32BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Just like DSP_AUDIOFORM_MM_32LE, but now the data is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * in big-endian format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define DSP_AUDIOFORM_MS_8 0 /* 8 bit mono */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define DSP_AUDIOFORM_MS_16LE 1 /* 16 bit mono */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define DSP_AUDIOFORM_MS_24LE 2 /* 24 bit mono */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define DSP_AUDIOFORM_MS_32LE 3 /* 32 bit mono */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define DSP_AUDIOFORM_SS_8 4 /* 8 bit stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define DSP_AUDIOFORM_SS_16LE 5 /* 16 bit stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define DSP_AUDIOFORM_SS_24LE 6 /* 24 bit stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define DSP_AUDIOFORM_SS_32LE 7 /* 32 bit stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define DSP_AUDIOFORM_MM_32LE 8 /* 32 bit mono->mono little-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define DSP_AUDIOFORM_MM_32BE 9 /* 32 bit mono->mono big-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define DSP_AUDIOFORM_SS_32BE 10 /* 32 bit stereo big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define DSP_AUDIOFORM_INVALID 0xFF /* Invalid audio format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * Super-interleave is defined as interleaving by 4 or more. Darla20 and Gina20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * do not support super interleave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * 16 bit, 24 bit, and 32 bit little endian samples are supported for super
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * interleave. The interleave factor must be even. 16 - way interleave is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * current maximum, so you can interleave by 4, 6, 8, 10, 12, 14, and 16.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * The actual format code is derived by taking the define below and or-ing with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * the interleave factor. So, 32 bit interleave by 6 is 0x86 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * 16 bit interleave by 16 is (0x40 | 0x10) = 0x50.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define DSP_AUDIOFORM_SUPER_INTERLEAVE_16LE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define DSP_AUDIOFORM_SUPER_INTERLEAVE_24LE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define DSP_AUDIOFORM_SUPER_INTERLEAVE_32LE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * Gina24, Mona, and Layla24 control register defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define GML_CONVERTER_ENABLE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define GML_SPDIF_PRO_MODE 0x0020 /* Professional S/PDIF == 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) consumer == 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define GML_SPDIF_SAMPLE_RATE0 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define GML_SPDIF_SAMPLE_RATE1 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define GML_SPDIF_TWO_CHANNEL 0x0100 /* 1 == two channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 0 == one channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define GML_SPDIF_NOT_AUDIO 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define GML_SPDIF_COPY_PERMIT 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define GML_SPDIF_24_BIT 0x0800 /* 1 == 24 bit, 0 == 20 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define GML_ADAT_MODE 0x1000 /* 1 == ADAT mode, 0 == S/PDIF mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define GML_SPDIF_OPTICAL_MODE 0x2000 /* 1 == optical mode, 0 == RCA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define GML_SPDIF_CDROM_MODE 0x3000 /* 1 == CDROM mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * 0 == RCA or optical mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define GML_DOUBLE_SPEED_MODE 0x4000 /* 1 == double speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 0 == single speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define GML_DIGITAL_IN_AUTO_MUTE 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define GML_96KHZ (0x0 | GML_DOUBLE_SPEED_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define GML_88KHZ (0x1 | GML_DOUBLE_SPEED_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define GML_48KHZ 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define GML_44KHZ 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define GML_32KHZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define GML_22KHZ 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define GML_16KHZ 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define GML_11KHZ 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define GML_8KHZ 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define GML_SPDIF_CLOCK 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define GML_ADAT_CLOCK 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define GML_WORD_CLOCK 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define GML_ESYNC_CLOCK 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define GML_ESYNCx2_CLOCK 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define GML_CLOCK_CLEAR_MASK 0xffffbff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define GML_SPDIF_RATE_CLEAR_MASK (~(GML_SPDIF_SAMPLE_RATE0|GML_SPDIF_SAMPLE_RATE1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define GML_DIGITAL_MODE_CLEAR_MASK 0xffffcfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define GML_SPDIF_FORMAT_CLEAR_MASK 0xfffff01f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * Mia sample rate and clock setting constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define MIA_32000 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define MIA_44100 0x0042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define MIA_48000 0x0041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define MIA_88200 0x0142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define MIA_96000 0x0141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define MIA_SPDIF 0x00000044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define MIA_SPDIF96 0x00000144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define MIA_MIDI_REV 1 /* Must be Mia rev 1 for MIDI support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * 3G register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define E3G_CONVERTER_ENABLE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define E3G_SPDIF_PRO_MODE 0x0020 /* Professional S/PDIF == 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) consumer == 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define E3G_SPDIF_SAMPLE_RATE0 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define E3G_SPDIF_SAMPLE_RATE1 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define E3G_SPDIF_TWO_CHANNEL 0x0100 /* 1 == two channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 0 == one channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define E3G_SPDIF_NOT_AUDIO 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define E3G_SPDIF_COPY_PERMIT 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define E3G_SPDIF_24_BIT 0x0800 /* 1 == 24 bit, 0 == 20 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define E3G_DOUBLE_SPEED_MODE 0x4000 /* 1 == double speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 0 == single speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define E3G_PHANTOM_POWER 0x8000 /* 1 == phantom power on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 0 == phantom power off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define E3G_96KHZ (0x0 | E3G_DOUBLE_SPEED_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define E3G_88KHZ (0x1 | E3G_DOUBLE_SPEED_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define E3G_48KHZ 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define E3G_44KHZ 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define E3G_32KHZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define E3G_22KHZ 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define E3G_16KHZ 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define E3G_11KHZ 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define E3G_8KHZ 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define E3G_SPDIF_CLOCK 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define E3G_ADAT_CLOCK 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define E3G_WORD_CLOCK 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define E3G_CONTINUOUS_CLOCK 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define E3G_ADAT_MODE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define E3G_SPDIF_OPTICAL_MODE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define E3G_CLOCK_CLEAR_MASK 0xbfffbff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define E3G_DIGITAL_MODE_CLEAR_MASK 0xffffcfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define E3G_SPDIF_FORMAT_CLEAR_MASK 0xfffff01f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Clock detect bits reported by the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define E3G_CLOCK_DETECT_BIT_WORD96 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define E3G_CLOCK_DETECT_BIT_WORD48 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define E3G_CLOCK_DETECT_BIT_SPDIF48 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define E3G_CLOCK_DETECT_BIT_ADAT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define E3G_CLOCK_DETECT_BIT_SPDIF96 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define E3G_CLOCK_DETECT_BIT_WORD (E3G_CLOCK_DETECT_BIT_WORD96|E3G_CLOCK_DETECT_BIT_WORD48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define E3G_CLOCK_DETECT_BIT_SPDIF (E3G_CLOCK_DETECT_BIT_SPDIF48|E3G_CLOCK_DETECT_BIT_SPDIF96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Frequency control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define E3G_MAGIC_NUMBER 677376000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define E3G_FREQ_REG_DEFAULT (E3G_MAGIC_NUMBER / 48000 - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define E3G_FREQ_REG_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* 3G external box types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define E3G_GINA3G_BOX_TYPE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define E3G_LAYLA3G_BOX_TYPE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define E3G_ASIC_NOT_LOADED 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define E3G_BOX_TYPE_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Indigo express control register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define INDIGO_EXPRESS_32000 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define INDIGO_EXPRESS_44100 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define INDIGO_EXPRESS_48000 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define INDIGO_EXPRESS_DOUBLE_SPEED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define INDIGO_EXPRESS_QUAD_SPEED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define INDIGO_EXPRESS_CLOCK_MASK 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * Gina20 & Layla20 have input gain controls for the analog inputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * this is the magic number for the hardware that gives you 0 dB at -10.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define GL20_INPUT_GAIN_MAGIC_NUMBER 0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * Defines how much time must pass between DSP load attempts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define DSP_LOAD_ATTEMPT_PERIOD 1000000L /* One second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * Size of arrays for the comm page. MAX_PLAY_TAPS and MAX_REC_TAPS are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * no longer used, but the sizes must still be right for the DSP to see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * the comm page correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define MONITOR_ARRAY_SIZE 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define VMIXER_ARRAY_SIZE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define MIDI_OUT_BUFFER_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define MIDI_IN_BUFFER_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define MAX_PLAY_TAPS 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define MAX_REC_TAPS 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define DSP_MIDI_OUT_FIFO_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* sg_entry is a single entry for the scatter-gather list. The array of struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) sg_entry struct is read by the DSP, so all values must be little-endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define MAX_SGLIST_ENTRIES 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct sg_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) __le32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) The comm page. This structure is read and written by the DSP; the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) DSP code is a firm believer in the byte offsets written in the comments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) at the end of each line. This structure should not be changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) Any reads from or writes to this structure should be in little-endian format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct comm_page { /* Base Length*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) __le32 comm_size; /* size of this object 0x000 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) __le32 flags; /* See Appendix A below 0x004 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) __le32 unused; /* Unused entry 0x008 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) __le32 sample_rate; /* Card sample rate in Hz 0x00c 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) __le32 handshake; /* DSP command handshake 0x010 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) __le32 cmd_start; /* Chs. to start mask 0x014 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) __le32 cmd_stop; /* Chs. to stop mask 0x018 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) __le32 cmd_reset; /* Chs. to reset mask 0x01c 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) __le16 audio_format[DSP_MAXPIPES]; /* Chs. audio format 0x020 32*2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct sg_entry sglist_addr[DSP_MAXPIPES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Chs. Physical sglist addrs 0x060 32*8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) __le32 position[DSP_MAXPIPES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Positions for ea. ch. 0x160 32*4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) s8 vu_meter[DSP_MAXPIPES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* VU meters 0x1e0 32*1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) s8 peak_meter[DSP_MAXPIPES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* Peak meters 0x200 32*1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) s8 line_out_level[DSP_MAXAUDIOOUTPUTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Output gain 0x220 16*1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) s8 line_in_level[DSP_MAXAUDIOINPUTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Input gain 0x230 16*1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) s8 monitors[MONITOR_ARRAY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* Monitor map 0x240 0x180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) __le32 play_coeff[MAX_PLAY_TAPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* Gina/Darla play filters - obsolete 0x3c0 168*4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) __le32 rec_coeff[MAX_REC_TAPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Gina/Darla record filters - obsolete 0x660 192*4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) __le16 midi_input[MIDI_IN_BUFFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* MIDI input data transfer buffer 0x960 256*2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u8 gd_clock_state; /* Chg Gina/Darla clock state 0xb60 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u8 gd_spdif_status; /* Chg. Gina/Darla S/PDIF state 0xb61 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u8 gd_resampler_state; /* Should always be 3 0xb62 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u8 filler2; /* 0xb63 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) __le32 nominal_level_mask; /* -10 level enable mask 0xb64 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) __le16 input_clock; /* Chg. Input clock state 0xb68 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) __le16 output_clock; /* Chg. Output clock state 0xb6a 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) __le32 status_clocks; /* Current Input clock state 0xb6c 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) __le32 ext_box_status; /* External box status 0xb70 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) __le32 cmd_add_buffer; /* Pipes to add (obsolete) 0xb74 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) __le32 midi_out_free_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* # of bytes free in MIDI output FIFO 0xb78 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) __le32 unused2; /* Cyclic pipes 0xb7c 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) __le32 control_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Mona, Gina24, Layla24, 3G ctrl reg 0xb80 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) __le32 e3g_frq_register; /* 3G frequency register 0xb84 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u8 filler[24]; /* filler 0xb88 24*1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) s8 vmixer[VMIXER_ARRAY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Vmixer levels 0xba0 64*1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u8 midi_output[MIDI_OUT_BUFFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* MIDI output data 0xbe0 32*1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #endif /* _ECHO_DSP_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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