^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Copyright Echo Digital Audio Corporation (c) 1998 - 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) www.echoaudio.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) This file is part of Echo Digital Audio's generic driver library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Echo Digital Audio's generic driver library is free software;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) you can redistribute it and/or modify it under the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) the GNU General Public License as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Foundation, Inc., 59 Temple Place - Suite 330, Boston,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MA 02111-1307, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Translation from C++ and adaptation for use in ALSA-Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) were made by Giuliano Pochini <pochini@shiny.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #if PAGE_SIZE < 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #error PAGE_SIZE is < 4k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int restore_dsp_rettings(struct echoaudio *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Some vector commands involve the DSP reading or writing data to and from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) comm page; if you send one of these commands to the DSP, it will complete the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) command and then write a non-zero value to the Handshake field in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) comm page. This function waits for the handshake to show up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int wait_handshake(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Wait up to 20ms for the handshake from the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) for (i = 0; i < HANDSHAKE_TIMEOUT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Look for the handshake value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (chip->comm_page->handshake) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dev_err(chip->card->dev, "wait_handshake(): Timeout waiting for DSP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Much of the interaction between the DSP and the driver is done via vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) commands; send_vector writes a vector command to the DSP. Typically, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) causes the DSP to read or write fields in the comm page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PCI posting is not required thanks to the handshake logic. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int send_vector(struct echoaudio *chip, u32 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) wmb(); /* Flush all pending writes before sending the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Wait up to 100ms for the "vector busy" bit to be off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) for (i = 0; i < VECTOR_BUSY_TIMEOUT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (!(get_dsp_register(chip, CHI32_VECTOR_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) CHI32_VECTOR_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) set_dsp_register(chip, CHI32_VECTOR_REG, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*if (i) DE_ACT(("send_vector time: %d\n", i));*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev_err(chip->card->dev, "timeout on send_vector\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* write_dsp writes a 32-bit value to the DSP; this is used almost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) exclusively for loading the DSP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int write_dsp(struct echoaudio *chip, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 status, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) for (i = 0; i < 10000000; i++) { /* timeout = 10s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) status = get_dsp_register(chip, CHI32_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if ((status & CHI32_STATUS_HOST_WRITE_EMPTY) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) set_dsp_register(chip, CHI32_DATA_REG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) wmb(); /* write it immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) chip->bad_board = true; /* Set true until DSP re-loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dev_dbg(chip->card->dev, "write_dsp: Set bad_board to true\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* read_dsp reads a 32-bit value from the DSP; this is used almost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) exclusively for loading the DSP and checking the status of the ASIC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int read_dsp(struct echoaudio *chip, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 status, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) for (i = 0; i < READ_DSP_TIMEOUT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) status = get_dsp_register(chip, CHI32_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if ((status & CHI32_STATUS_HOST_READ_FULL) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *data = get_dsp_register(chip, CHI32_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) chip->bad_board = true; /* Set true until DSP re-loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev_err(chip->card->dev, "read_dsp: Set bad_board to true\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) Firmware loading functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* This function is used to read back the serial number from the DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) this is triggered by the SET_COMMPAGE_ADDR command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) Only some early Echogals products have serial numbers in the ROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) the serial number is not used, but you still need to do this as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) part of the DSP load process. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int read_sn(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 sn[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (read_dsp(chip, &sn[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "Failed to read serial number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "Read serial number %08x %08x %08x %08x %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) sn[0], sn[1], sn[2], sn[3], sn[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifndef ECHOCARD_HAS_ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* This card has no ASIC, just return ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline int check_asic_status(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) chip->asic_loaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #endif /* !ECHOCARD_HAS_ASIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #ifdef ECHOCARD_HAS_ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Load ASIC code - done after the DSP is loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 i, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 *code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) err = get_firmware(&fw, chip, asic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_warn(chip->card->dev, "Firmware not found !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) code = (u8 *)fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) size = fw->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Send the "Here comes the ASIC" command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (write_dsp(chip, cmd) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) goto la_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Write length of ASIC file in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (write_dsp(chip, size) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) goto la_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (write_dsp(chip, code[i]) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) goto la_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) free_firmware(fw, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) la_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_err(chip->card->dev, "failed on write_dsp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) free_firmware(fw, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #endif /* ECHOCARD_HAS_ASIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #ifdef DSP_56361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Install the resident loader for 56361 DSPs; The resident loader is on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) the EPROM on the board for 56301 DSP. The resident loader is a tiny little
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) program that is used to load the real DSP code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int install_resident_loader(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int index, words, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u16 *code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* 56361 cards only! This check is required by the old 56301-based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) Mona and Gina24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (chip->device_id != DEVICE_ID_56361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Look to see if the resident loader is present. If the resident
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) loader is already installed, host flag 5 will be on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) status = get_dsp_register(chip, CHI32_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (status & CHI32_STATUS_REG_HF5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "Resident loader already installed; status is 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) i = get_firmware(&fw, chip, FW_361_LOADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (i < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_warn(chip->card->dev, "Firmware not found !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* The DSP code is an array of 16 bit words. The array is divided up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) into sections. The first word of each section is the size in words,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) followed by the section type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) Since DSP addresses and data are 24 bits wide, they each take up two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 16 bit words in the array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) This is a lot like the other loader loop, but it's not a loop, you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) don't write the memory type, and you don't write a zero at the end. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Set DSP format bits for 24 bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) set_dsp_register(chip, CHI32_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) get_dsp_register(chip, CHI32_CONTROL_REG) | 0x900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) code = (u16 *)fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Skip the header section; the first word in the array is the size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) of the first section, so the first real section of code is pointed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) to by Code[0]. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) index = code[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Skip the section size, LRS block type, and DSP memory type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) index += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Get the number of DSP words to write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) words = code[index++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Get the DSP address for this block; 24 bits, so build from two words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) address = ((u32)code[index] << 16) + code[index + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) index += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Write the count to the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (write_dsp(chip, words)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "install_resident_loader: Failed to write word count!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) goto irl_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Write the DSP address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (write_dsp(chip, address)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "install_resident_loader: Failed to write DSP address!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) goto irl_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Write out this block of code to the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) for (i = 0; i < words; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) data = ((u32)code[index] << 16) + code[index + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (write_dsp(chip, data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "install_resident_loader: Failed to write DSP code\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) goto irl_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) index += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Wait for flag 5 to come up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) for (i = 0; i < 200; i++) { /* Timeout is 50us * 200 = 10ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) status = get_dsp_register(chip, CHI32_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (status & CHI32_STATUS_REG_HF5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (i == 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_err(chip->card->dev, "Resident loader failed to set HF5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) goto irl_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_dbg(chip->card->dev, "Resident loader successfully installed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) free_firmware(fw, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) irl_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) free_firmware(fw, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #endif /* DSP_56361 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int load_dsp(struct echoaudio *chip, u16 *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 address, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int index, words, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (chip->dsp_code == code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_warn(chip->card->dev, "DSP is already loaded!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) chip->bad_board = true; /* Set true until DSP loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) chip->dsp_code = NULL; /* Current DSP code not loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) chip->asic_loaded = false; /* Loading the DSP code will reset the ASIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_dbg(chip->card->dev, "load_dsp: Set bad_board to true\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* If this board requires a resident loader, install it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #ifdef DSP_56361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if ((i = install_resident_loader(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Send software reset command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (send_vector(chip, DSP_VC_RESET) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "LoadDsp: send_vector DSP_VC_RESET failed, Critical Failure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Delay 10us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Wait 10ms for HF3 to indicate that software reset is complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) for (i = 0; i < 1000; i++) { /* Timeout is 10us * 1000 = 10ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (get_dsp_register(chip, CHI32_STATUS_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) CHI32_STATUS_REG_HF3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (i == 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "load_dsp: Timeout waiting for CHI32_STATUS_REG_HF3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Set DSP format bits for 24 bit mode now that soft reset is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) set_dsp_register(chip, CHI32_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) get_dsp_register(chip, CHI32_CONTROL_REG) | 0x900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Main loader loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) index = code[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int block_type, mem_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Total Block Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Block Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) block_type = code[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (block_type == 4) /* We're finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Memory Type P=0,X=1,Y=2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) mem_type = code[index++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Block Code Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) words = code[index++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (words == 0) /* We're finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Start Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) address = ((u32)code[index] << 16) + code[index + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) index += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (write_dsp(chip, words) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) "load_dsp: failed to write number of DSP words\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (write_dsp(chip, address) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) "load_dsp: failed to write DSP address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (write_dsp(chip, mem_type) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) "load_dsp: failed to write DSP memory type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) for (i = 0; i < words; i++, index+=2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) data = ((u32)code[index] << 16) + code[index + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (write_dsp(chip, data) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "load_dsp: failed to write DSP data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (write_dsp(chip, 0) < 0) { /* We're done!!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "load_dsp: Failed to write final zero\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) for (i = 0; i < 5000; i++) { /* Timeout is 100us * 5000 = 500ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Wait for flag 4 - indicates that the DSP loaded OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (get_dsp_register(chip, CHI32_STATUS_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) CHI32_STATUS_REG_HF4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) set_dsp_register(chip, CHI32_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) get_dsp_register(chip, CHI32_CONTROL_REG) & ~0x1b00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (write_dsp(chip, DSP_FNC_SET_COMMPAGE_ADDR) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "load_dsp: Failed to write DSP_FNC_SET_COMMPAGE_ADDR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (write_dsp(chip, chip->comm_page_phys) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "load_dsp: Failed to write comm page address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Get the serial number via slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) This is triggered by the SET_COMMPAGE_ADDR command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) We don't actually use the serial number but we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) get it as part of the DSP init voodoo. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (read_sn(chip) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "load_dsp: Failed to read serial number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) chip->dsp_code = code; /* Show which DSP code loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) chip->bad_board = false; /* DSP OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "load_dsp: DSP load timed out waiting for HF4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* load_firmware takes care of loading the DSP and any ASIC code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int load_firmware(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int box_type, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (snd_BUG_ON(!chip->comm_page))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* See if the ASIC is present and working - only if the DSP is already loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (chip->dsp_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if ((box_type = check_asic_status(chip)) >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return box_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* ASIC check failed; force the DSP to reload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) chip->dsp_code = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) err = get_firmware(&fw, chip, chip->dsp_code_to_load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) err = load_dsp(chip, (u16 *)fw->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) free_firmware(fw, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if ((box_type = load_asic(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return box_type; /* error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return box_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) Mixer functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #if defined(ECHOCARD_HAS_INPUT_NOMINAL_LEVEL) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) defined(ECHOCARD_HAS_OUTPUT_NOMINAL_LEVEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Set the nominal level for an input or output bus (true = -10dBV, false = +4dBu) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int set_nominal_level(struct echoaudio *chip, u16 index, char consumer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (snd_BUG_ON(index >= num_busses_out(chip) + num_busses_in(chip)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Wait for the handshake (OK even if ASIC is not loaded) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) chip->nominal_level[index] = consumer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (consumer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) chip->comm_page->nominal_level_mask |= cpu_to_le32(1 << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) chip->comm_page->nominal_level_mask &= ~cpu_to_le32(1 << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #endif /* ECHOCARD_HAS_*_NOMINAL_LEVEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* Set the gain for a single physical output channel (dB). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int set_output_gain(struct echoaudio *chip, u16 channel, s8 gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (snd_BUG_ON(channel >= num_busses_out(chip)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Save the new value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) chip->output_gain[channel] = gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) chip->comm_page->line_out_level[channel] = gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #ifdef ECHOCARD_HAS_MONITOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Set the monitor level from an input bus to an output bus. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int set_monitor_gain(struct echoaudio *chip, u16 output, u16 input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) s8 gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (snd_BUG_ON(output >= num_busses_out(chip) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) input >= num_busses_in(chip)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) chip->monitor_gain[output][input] = gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) chip->comm_page->monitors[monitor_index(chip, output, input)] = gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #endif /* ECHOCARD_HAS_MONITOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Tell the DSP to read and update output, nominal & monitor levels in comm page. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int update_output_line_level(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return send_vector(chip, DSP_VC_UPDATE_OUTVOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Tell the DSP to read and update input levels in comm page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int update_input_line_level(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return send_vector(chip, DSP_VC_UPDATE_INGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* set_meters_on turns the meters on or off. If meters are turned on, the DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) will write the meter and clock detect values to the comm page at about 30Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static void set_meters_on(struct echoaudio *chip, char on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (on && !chip->meters_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) send_vector(chip, DSP_VC_METERS_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) chip->meters_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) } else if (!on && chip->meters_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) send_vector(chip, DSP_VC_METERS_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) chip->meters_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) memset((s8 *)chip->comm_page->vu_meter, ECHOGAIN_MUTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) DSP_MAXPIPES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) memset((s8 *)chip->comm_page->peak_meter, ECHOGAIN_MUTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) DSP_MAXPIPES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Fill out an the given array using the current values in the comm page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) Meters are written in the comm page by the DSP in this order:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) Output busses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) Input busses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) Output pipes (vmixer cards only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) This function assumes there are no more than 16 in/out busses or pipes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) Meters is an array [3][16][2] of long. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static void get_audio_meters(struct echoaudio *chip, long *meters)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) unsigned int i, m, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) for (i = 0 ; i < 96; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) meters[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) for (m = 0, n = 0, i = 0; i < num_busses_out(chip); i++, m++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) meters[n++] = chip->comm_page->vu_meter[m];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) meters[n++] = chip->comm_page->peak_meter[m];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #ifdef ECHOCARD_ECHO3G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) m = E3G_MAX_OUTPUTS; /* Skip unused meters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) for (n = 32, i = 0; i < num_busses_in(chip); i++, m++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) meters[n++] = chip->comm_page->vu_meter[m];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) meters[n++] = chip->comm_page->peak_meter[m];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #ifdef ECHOCARD_HAS_VMIXER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) for (n = 64, i = 0; i < num_pipes_out(chip); i++, m++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) meters[n++] = chip->comm_page->vu_meter[m];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) meters[n++] = chip->comm_page->peak_meter[m];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static int restore_dsp_rettings(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int i, o, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if ((err = check_asic_status(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Gina20/Darla20 only. Should be harmless for other cards. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) chip->comm_page->gd_clock_state = GD_CLOCK_UNDEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) chip->comm_page->gd_spdif_status = GD_SPDIF_STATUS_UNDEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) chip->comm_page->handshake = cpu_to_le32(0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Restore output busses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) for (i = 0; i < num_busses_out(chip); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) err = set_output_gain(chip, i, chip->output_gain[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #ifdef ECHOCARD_HAS_VMIXER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) for (i = 0; i < num_pipes_out(chip); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) for (o = 0; o < num_busses_out(chip); o++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) err = set_vmixer_gain(chip, o, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) chip->vmixer_gain[o][i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (update_vmixer_level(chip) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #endif /* ECHOCARD_HAS_VMIXER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #ifdef ECHOCARD_HAS_MONITOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) for (o = 0; o < num_busses_out(chip); o++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) for (i = 0; i < num_busses_in(chip); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) err = set_monitor_gain(chip, o, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) chip->monitor_gain[o][i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #endif /* ECHOCARD_HAS_MONITOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #ifdef ECHOCARD_HAS_INPUT_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) for (i = 0; i < num_busses_in(chip); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) err = set_input_gain(chip, i, chip->input_gain[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #endif /* ECHOCARD_HAS_INPUT_GAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) err = update_output_line_level(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) err = update_input_line_level(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) err = set_sample_rate(chip, chip->sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (chip->meters_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) err = send_vector(chip, DSP_VC_METERS_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #ifdef ECHOCARD_HAS_DIGITAL_MODE_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (set_digital_mode(chip, chip->digital_mode) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #ifdef ECHOCARD_HAS_DIGITAL_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (set_professional_spdif(chip, chip->professional_spdif) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #ifdef ECHOCARD_HAS_PHANTOM_POWER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (set_phantom_power(chip, chip->phantom_power) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #ifdef ECHOCARD_HAS_EXTERNAL_CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* set_input_clock() also restores automute setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (set_input_clock(chip, chip->input_clock) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #ifdef ECHOCARD_HAS_OUTPUT_CLOCK_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (set_output_clock(chip, chip->output_clock) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (wait_handshake(chip) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (send_vector(chip, DSP_VC_UPDATE_FLAGS) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) Transport functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* set_audio_format() sets the format of the audio data in host memory for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) this pipe. Note that _MS_ (mono-to-stereo) playback modes are not used by ALSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) but they are here because they are just mono while capturing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static void set_audio_format(struct echoaudio *chip, u16 pipe_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) const struct audioformat *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u16 dsp_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dsp_format = DSP_AUDIOFORM_SS_16LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Look for super-interleave (no big-endian and 8 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (format->interleave > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) switch (format->bits_per_sample) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dsp_format = DSP_AUDIOFORM_SUPER_INTERLEAVE_16LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dsp_format = DSP_AUDIOFORM_SUPER_INTERLEAVE_24LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dsp_format = DSP_AUDIOFORM_SUPER_INTERLEAVE_32LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dsp_format |= format->interleave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) } else if (format->data_are_bigendian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* For big-endian data, only 32 bit samples are supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) switch (format->interleave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dsp_format = DSP_AUDIOFORM_MM_32BE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #ifdef ECHOCARD_HAS_STEREO_BIG_ENDIAN32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dsp_format = DSP_AUDIOFORM_SS_32BE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) } else if (format->interleave == 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) format->bits_per_sample == 32 && !format->mono_to_stereo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* 32 bit little-endian mono->mono case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dsp_format = DSP_AUDIOFORM_MM_32LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* Handle the other little-endian formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) switch (format->bits_per_sample) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (format->interleave == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dsp_format = DSP_AUDIOFORM_SS_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dsp_format = DSP_AUDIOFORM_MS_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (format->interleave == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dsp_format = DSP_AUDIOFORM_SS_16LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dsp_format = DSP_AUDIOFORM_MS_16LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (format->interleave == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dsp_format = DSP_AUDIOFORM_SS_24LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dsp_format = DSP_AUDIOFORM_MS_24LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (format->interleave == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dsp_format = DSP_AUDIOFORM_SS_32LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dsp_format = DSP_AUDIOFORM_MS_32LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) "set_audio_format[%d] = %x\n", pipe_index, dsp_format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) chip->comm_page->audio_format[pipe_index] = cpu_to_le16(dsp_format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* start_transport starts transport for a set of pipes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) The bits 1 in channel_mask specify what pipes to start. Only the bit of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) first channel must be set, regardless its interleave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) Same thing for pause_ and stop_ -trasport below. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int start_transport(struct echoaudio *chip, u32 channel_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u32 cyclic_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) chip->comm_page->cmd_start |= cpu_to_le32(channel_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (chip->comm_page->cmd_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) send_vector(chip, DSP_VC_START_TRANSFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* Keep track of which pipes are transporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) chip->active_mask |= channel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) chip->comm_page->cmd_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_err(chip->card->dev, "start_transport: No pipes to start!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int pause_transport(struct echoaudio *chip, u32 channel_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) chip->comm_page->cmd_stop |= cpu_to_le32(channel_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) chip->comm_page->cmd_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (chip->comm_page->cmd_stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) send_vector(chip, DSP_VC_STOP_TRANSFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* Keep track of which pipes are transporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) chip->active_mask &= ~channel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) chip->comm_page->cmd_stop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) chip->comm_page->cmd_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dev_dbg(chip->card->dev, "pause_transport: No pipes to stop!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static int stop_transport(struct echoaudio *chip, u32 channel_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) chip->comm_page->cmd_stop |= cpu_to_le32(channel_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) chip->comm_page->cmd_reset |= cpu_to_le32(channel_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (chip->comm_page->cmd_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) send_vector(chip, DSP_VC_STOP_TRANSFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* Keep track of which pipes are transporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) chip->active_mask &= ~channel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) chip->comm_page->cmd_stop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) chip->comm_page->cmd_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dev_dbg(chip->card->dev, "stop_transport: No pipes to stop!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static inline int is_pipe_allocated(struct echoaudio *chip, u16 pipe_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return (chip->pipe_alloc_mask & (1 << pipe_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* Stops everything and turns off the DSP. All pipes should be already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) stopped and unallocated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static int rest_in_peace(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* Stops all active pipes (just to be sure) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) stop_transport(chip, chip->active_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) set_meters_on(chip, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #ifdef ECHOCARD_HAS_MIDI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) enable_midi_input(chip, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* Go to sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (chip->dsp_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* Make load_firmware do a complete reload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) chip->dsp_code = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* Put the DSP to sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return send_vector(chip, DSP_VC_GO_COMATOSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* Fills the comm page with default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static int init_dsp_comm_page(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* Check if the compiler added extra padding inside the structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (offsetof(struct comm_page, midi_output) != 0xbe0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) "init_dsp_comm_page() - Invalid struct comm_page structure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* Init all the basic stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) chip->card_name = ECHOCARD_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) chip->bad_board = true; /* Set true until DSP loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) chip->dsp_code = NULL; /* Current DSP code not loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) chip->asic_loaded = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) memset(chip->comm_page, 0, sizeof(struct comm_page));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* Init the comm page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) chip->comm_page->comm_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) cpu_to_le32(sizeof(struct comm_page));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) chip->comm_page->handshake = cpu_to_le32(0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) chip->comm_page->midi_out_free_count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) cpu_to_le32(DSP_MIDI_OUT_FIFO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) chip->comm_page->sample_rate = cpu_to_le32(44100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* Set line levels so we don't blast any inputs on startup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) memset(chip->comm_page->monitors, ECHOGAIN_MUTED, MONITOR_ARRAY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) memset(chip->comm_page->vmixer, ECHOGAIN_MUTED, VMIXER_ARRAY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* This function initializes the chip structure with default values, ie. all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * muted and internal clock source. Then it copies the settings to the DSP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * This MUST be called after the DSP is up and running !
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static int init_line_levels(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) memset(chip->output_gain, ECHOGAIN_MUTED, sizeof(chip->output_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) memset(chip->input_gain, ECHOGAIN_MUTED, sizeof(chip->input_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) memset(chip->monitor_gain, ECHOGAIN_MUTED, sizeof(chip->monitor_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) memset(chip->vmixer_gain, ECHOGAIN_MUTED, sizeof(chip->vmixer_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) chip->input_clock = ECHO_CLOCK_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) chip->output_clock = ECHO_CLOCK_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) chip->sample_rate = 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return restore_dsp_rettings(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* This is low level part of the interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) It returns -1 if the IRQ is not ours, or N>=0 if it is, where N is the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) of midi data in the input queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static int service_irq(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) int st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* Read the DSP status register and see if this DSP generated this interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (get_dsp_register(chip, CHI32_STATUS_REG) & CHI32_STATUS_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) st = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #ifdef ECHOCARD_HAS_MIDI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* Get and parse midi data if present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (chip->comm_page->midi_input[0]) /* The count is at index 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) st = midi_service_irq(chip); /* Returns how many midi bytes we received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* Clear the hardware interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) chip->comm_page->midi_input[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) send_vector(chip, DSP_VC_ACK_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) Functions for opening and closing pipes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* allocate_pipes is used to reserve audio pipes for your exclusive use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) The call will fail if some pipes are already allocated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static int allocate_pipes(struct echoaudio *chip, struct audiopipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) int pipe_index, int interleave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) u32 channel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) "allocate_pipes: ch=%d int=%d\n", pipe_index, interleave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (chip->bad_board)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) for (channel_mask = i = 0; i < interleave; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) channel_mask |= 1 << (pipe_index + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (chip->pipe_alloc_mask & channel_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) "allocate_pipes: channel already open\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) chip->comm_page->position[pipe_index] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) chip->pipe_alloc_mask |= channel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* This driver uses cyclic buffers only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) chip->pipe_cyclic_mask |= channel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) pipe->index = pipe_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) pipe->interleave = interleave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) pipe->state = PIPE_STATE_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* The counter register is where the DSP writes the 32 bit DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) position for a pipe. The DSP is constantly updating this value as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) it moves data. The DMA counter is in units of bytes, not samples. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) pipe->dma_counter = (__le32 *)&chip->comm_page->position[pipe_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) *pipe->dma_counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return pipe_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static int free_pipes(struct echoaudio *chip, struct audiopipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) u32 channel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (snd_BUG_ON(!is_pipe_allocated(chip, pipe->index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (snd_BUG_ON(pipe->state != PIPE_STATE_STOPPED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) for (channel_mask = i = 0; i < pipe->interleave; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) channel_mask |= 1 << (pipe->index + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) chip->pipe_alloc_mask &= ~channel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) chip->pipe_cyclic_mask &= ~channel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) Functions for managing the scatter-gather list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static int sglist_init(struct echoaudio *chip, struct audiopipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) pipe->sglist_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) memset(pipe->sgpage.area, 0, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) chip->comm_page->sglist_addr[pipe->index].addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) cpu_to_le32(pipe->sgpage.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static int sglist_add_mapping(struct echoaudio *chip, struct audiopipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) dma_addr_t address, size_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int head = pipe->sglist_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct sg_entry *list = (struct sg_entry *)pipe->sgpage.area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (head < MAX_SGLIST_ENTRIES - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) list[head].addr = cpu_to_le32(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) list[head].size = cpu_to_le32(length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) pipe->sglist_head++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) dev_err(chip->card->dev, "SGlist: too many fragments\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static inline int sglist_add_irq(struct echoaudio *chip, struct audiopipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return sglist_add_mapping(chip, pipe, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static inline int sglist_wrap(struct echoaudio *chip, struct audiopipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return sglist_add_mapping(chip, pipe, pipe->sgpage.addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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