Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)    All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)    www.echoaudio.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)    This file is part of Echo Digital Audio's generic driver library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)    Echo Digital Audio's generic driver library is free software;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)    you can redistribute it and/or modify it under the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)    the GNU General Public License as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)    Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)    This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)    but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)    GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)    You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)    along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)    MA  02111-1307, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)    *************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  Translation from C++ and adaptation for use in ALSA-Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  were made by Giuliano Pochini <pochini@shiny.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* These functions are common for all "3G" cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static int check_asic_status(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u32 box_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	chip->comm_page->ext_box_status = cpu_to_le32(E3G_ASIC_NOT_LOADED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	chip->asic_loaded = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	send_vector(chip, DSP_VC_TEST_ASIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (wait_handshake(chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		chip->dsp_code = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	box_status = le32_to_cpu(chip->comm_page->ext_box_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	dev_dbg(chip->card->dev, "box_status=%x\n", box_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	if (box_status == E3G_ASIC_NOT_LOADED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	chip->asic_loaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	return box_status & E3G_BOX_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static inline u32 get_frq_reg(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	return le32_to_cpu(chip->comm_page->e3g_frq_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /* Most configuration of 3G cards is accomplished by writing the control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) register. write_control_reg sends the new control register value to the DSP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static int write_control_reg(struct echoaudio *chip, u32 ctl, u32 frq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			     char force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	__le32 ctl_reg, frq_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		"WriteControlReg: Setting 0x%x, 0x%x\n", ctl, frq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ctl_reg = cpu_to_le32(ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	frq_reg = cpu_to_le32(frq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (ctl_reg != chip->comm_page->control_register ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	    frq_reg != chip->comm_page->e3g_frq_register || force) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		chip->comm_page->e3g_frq_register = frq_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		chip->comm_page->control_register = ctl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		return send_vector(chip, DSP_VC_WRITE_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	dev_dbg(chip->card->dev, "WriteControlReg: not written, no change\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Set the digital mode - currently for Gina24, Layla24, Mona, 3G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int set_digital_mode(struct echoaudio *chip, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u8 previous_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	int err, i, o;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* All audio channels must be closed before changing the digital mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (snd_BUG_ON(chip->pipe_alloc_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (snd_BUG_ON(!(chip->digital_modes & (1 << mode))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	previous_mode = chip->digital_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	err = dsp_set_digital_mode(chip, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* If we successfully changed the digital mode from or to ADAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 * then make sure all output, input and monitor levels are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 * updated by the DSP comm object. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (err >= 0 && previous_mode != mode &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	    (previous_mode == DIGITAL_MODE_ADAT || mode == DIGITAL_MODE_ADAT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		for (o = 0; o < num_busses_out(chip); o++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			for (i = 0; i < num_busses_in(chip); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 				set_monitor_gain(chip, o, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 						 chip->monitor_gain[o][i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #ifdef ECHOCARD_HAS_INPUT_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		for (i = 0; i < num_busses_in(chip); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			set_input_gain(chip, i, chip->input_gain[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		update_input_line_level(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		for (o = 0; o < num_busses_out(chip); o++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			set_output_gain(chip, o, chip->output_gain[o]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		update_output_line_level(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	case 32000 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	case 44100 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		if (chip->professional_spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			control_reg |= E3G_SPDIF_SAMPLE_RATE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	case 48000 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		control_reg |= E3G_SPDIF_SAMPLE_RATE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (chip->professional_spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		control_reg |= E3G_SPDIF_PRO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (chip->non_audio_spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		control_reg |= E3G_SPDIF_NOT_AUDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		E3G_SPDIF_COPY_PERMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	return control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Set the S/PDIF output format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int set_professional_spdif(struct echoaudio *chip, char prof)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u32 control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	control_reg = le32_to_cpu(chip->comm_page->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	chip->professional_spdif = prof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	return write_control_reg(chip, control_reg, get_frq_reg(chip), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* detect_input_clocks() returns a bitmask consisting of all the input clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) currently connected to the hardware; this changes as the user connects and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) disconnects clock inputs. You should use this information to determine which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) clocks the user is allowed to select. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static u32 detect_input_clocks(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	u32 clocks_from_dsp, clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* Map the DSP clock detect bits to the generic driver clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 * detect bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	clock_bits = ECHO_CLOCK_BIT_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		clock_bits |= ECHO_CLOCK_BIT_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	switch(chip->digital_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	case DIGITAL_MODE_SPDIF_RCA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	case DIGITAL_MODE_SPDIF_OPTICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			clock_bits |= ECHO_CLOCK_BIT_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	case DIGITAL_MODE_ADAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			clock_bits |= ECHO_CLOCK_BIT_ADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int load_asic(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	int box_type, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (chip->asic_loaded)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* Give the DSP a few milliseconds to settle down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	err = load_asic_generic(chip, DSP_FNC_LOAD_3G_ASIC, FW_3G_ASIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	chip->asic_code = FW_3G_ASIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* Now give the new ASIC some time to set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	/* See if it worked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	box_type = check_asic_status(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* Set up the control register if the load succeeded -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * 48 kHz, internal clock, S/PDIF RCA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (box_type >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		err = write_control_reg(chip, E3G_48KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 					E3G_FREQ_REG_DEFAULT, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return box_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int set_sample_rate(struct echoaudio *chip, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	u32 control_reg, clock, base_rate, frq_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* Only set the clock for internal mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		dev_warn(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		/* Save the rate anyhow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		chip->comm_page->sample_rate = cpu_to_le32(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		chip->sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		set_input_clock(chip, chip->input_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (snd_BUG_ON(rate >= 50000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		       chip->digital_mode == DIGITAL_MODE_ADAT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	control_reg = le32_to_cpu(chip->comm_page->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	control_reg &= E3G_CLOCK_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		clock = E3G_96KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		clock = E3G_88KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		clock = E3G_48KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		clock = E3G_44KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		clock = E3G_32KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		clock = E3G_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		if (rate > 50000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			clock |= E3G_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	control_reg |= clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	control_reg = set_spdif_bits(chip, control_reg, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	base_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (base_rate > 50000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		base_rate /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (base_rate < 32000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		base_rate = 32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	frq_reg = E3G_MAGIC_NUMBER / base_rate - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	if (frq_reg > E3G_FREQ_REG_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		frq_reg = E3G_FREQ_REG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	chip->comm_page->sample_rate = cpu_to_le32(rate);	/* ignored by the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	chip->sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		"SetSampleRate: %d clock %x\n", rate, control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	/* Tell the DSP about it - DSP reads both control reg & freq reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	return write_control_reg(chip, control_reg, frq_reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Set the sample clock source to internal, S/PDIF, ADAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int set_input_clock(struct echoaudio *chip, u16 clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	u32 control_reg, clocks_from_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	/* Mask off the clock select bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	control_reg = le32_to_cpu(chip->comm_page->control_register) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		E3G_CLOCK_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	case ECHO_CLOCK_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		chip->input_clock = ECHO_CLOCK_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		return set_sample_rate(chip, chip->sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	case ECHO_CLOCK_SPDIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		if (chip->digital_mode == DIGITAL_MODE_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		control_reg |= E3G_SPDIF_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			control_reg |= E3G_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 			control_reg &= ~E3G_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	case ECHO_CLOCK_ADAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		if (chip->digital_mode != DIGITAL_MODE_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		control_reg |= E3G_ADAT_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		control_reg &= ~E3G_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	case ECHO_CLOCK_WORD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		control_reg |= E3G_WORD_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			control_reg |= E3G_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			control_reg &= ~E3G_DOUBLE_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			"Input clock 0x%x not supported for Echo3G\n", clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	chip->input_clock = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	return write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	u32 control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	int err, incompatible_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	/* Set clock to "internal" if it's not compatible with the new mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	incompatible_clock = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	case DIGITAL_MODE_SPDIF_OPTICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	case DIGITAL_MODE_SPDIF_RCA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		if (chip->input_clock == ECHO_CLOCK_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			incompatible_clock = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	case DIGITAL_MODE_ADAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		if (chip->input_clock == ECHO_CLOCK_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 			incompatible_clock = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 			"Digital mode not supported: %d\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	if (incompatible_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		chip->sample_rate = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		set_input_clock(chip, ECHO_CLOCK_INTERNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	/* Clear the current digital mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	control_reg = le32_to_cpu(chip->comm_page->control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	/* Tweak the control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	case DIGITAL_MODE_SPDIF_OPTICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		control_reg |= E3G_SPDIF_OPTICAL_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	case DIGITAL_MODE_SPDIF_RCA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		/* E3G_SPDIF_OPTICAL_MODE bit cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	case DIGITAL_MODE_ADAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		control_reg |= E3G_ADAT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		control_reg &= ~E3G_DOUBLE_SPEED_MODE;	/* @@ useless */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	chip->digital_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	dev_dbg(chip->card->dev, "set_digital_mode(%d)\n", chip->digital_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	return incompatible_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }