Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)    All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)    www.echoaudio.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)    This file is part of Echo Digital Audio's generic driver library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)    Echo Digital Audio's generic driver library is free software;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)    you can redistribute it and/or modify it under the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)    the GNU General Public License as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)    Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)    This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)    but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)    GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)    You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)    along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)    MA  02111-1307, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  ****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  Translation from C++ and adaptation for use in ALSA-Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  were made by Giuliano Pochini <pochini@shiny.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  ****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)    Here's a block diagram of how most of the cards work:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)                   +-----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)            record |           |<-------------------- Inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)           <-------|           |        |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)      PCI          | Transport |        |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)      bus          |  engine   |       \|/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)           ------->|           |    +-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)             play  |           |--->|monitor|-------> Outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)                   +-----------+    | mixer |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)                                    +-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)    The lines going to and from the PCI bus represent "pipes".  A pipe performs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)    audio transport - moving audio data to and from buffers on the host via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)    bus mastering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)    The inputs and outputs on the right represent input and output "busses."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)    A bus is a physical, real connection to the outside world.  An example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)    of a bus would be the 1/4" analog connectors on the back of Layla or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)    an RCA S/PDIF connector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)    For most cards, there is a one-to-one correspondence between outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)    and busses; that is, each individual pipe is hard-wired to a single bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)    Cards that work this way are Darla20, Gina20, Layla20, Darla24, Gina24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)    Layla24, Mona, and Indigo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)    Mia has a feature called "virtual outputs."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)                   +-----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)            record |           |<----------------------------- Inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)           <-------|           |                  |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)      PCI          | Transport |                  |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)      bus          |  engine   |                 \|/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)           ------->|           |   +------+   +-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)             play  |           |-->|vmixer|-->|monitor|-------> Outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)                   +-----------+   +------+   | mixer |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)                                              +-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)    Obviously, the difference here is the box labeled "vmixer."  Vmixer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)    short for "virtual output mixer."  For Mia, pipes are *not* hard-wired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)    to a single bus; the vmixer lets you mix any pipe to any bus in any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)    combination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)    Note, however, that the left-hand side of the diagram is unchanged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)    Transport works exactly the same way - the difference is in the mixer stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)    Pipes and busses are numbered starting at zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)    Pipe index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)    ==========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)    A number of calls in CEchoGals refer to a "pipe index".  A pipe index is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)    a unique number for a pipe that unambiguously refers to a playback or record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)    pipe.  Pipe indices are numbered starting with analog outputs, followed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)    digital outputs, then analog inputs, then digital inputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)    Take Gina24 as an example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)    Pipe index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)    0-7            Analog outputs (0 .. FirstDigitalBusOut-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)    8-15           Digital outputs (FirstDigitalBusOut .. NumBussesOut-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)    16-17          Analog inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)    18-25          Digital inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)    You get the pipe index by calling CEchoGals::OpenAudio; the other transport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)    functions take the pipe index as a parameter.  If you need a pipe index for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)    some other reason, use the handy Makepipe_index method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)    Some calls take a CChannelMask parameter; CChannelMask is a handy way to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)    group pipe indices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)    Digital mode switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)    ===================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)    Some cards (right now, Gina24, Layla24, and Mona) have a Digital Mode Switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)    or DMS.  Cards with a DMS can be set to one of three mutually exclusive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)    digital modes: S/PDIF RCA, S/PDIF optical, or ADAT optical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)    This may create some confusion since ADAT optical is 8 channels wide and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)    S/PDIF is only two channels wide.  Gina24, Layla24, and Mona handle this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)    by acting as if they always have 8 digital outs and ins.  If you are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)    either S/PDIF mode, the last 6 channels don't do anything - data sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)    out these channels is thrown away and you will always record zeros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)    Note that with Gina24, Layla24, and Mona, sample rates above 50 kHz are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)    only available if you have the card configured for S/PDIF optical or S/PDIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)    RCA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)    Double speed mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)    =================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)    Some of the cards support 88.2 kHz and 96 kHz sampling (Darla24, Gina24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)    Layla24, Mona, Mia, and Indigo).  For these cards, the driver sometimes has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)    to worry about "double speed mode"; double speed mode applies whenever the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)    sampling rate is above 50 kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)    For instance, Mona and Layla24 support word clock sync.  However, they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)    actually support two different word clock modes - single speed (below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)    50 kHz) and double speed (above 50 kHz).  The hardware detects if a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)    or double speed word clock signal is present; the generic code uses that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)    information to determine which mode to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)    The generic code takes care of all this for you.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #ifndef _ECHOAUDIO_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define _ECHOAUDIO_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #include "echoaudio_dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	PCI configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * PCI vendor ID and device IDs for the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define VENDOR_ID		0x1057
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DEVICE_ID_56301		0x1801
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DEVICE_ID_56361		0x3410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SUBVENDOR_ID		0xECC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  * Valid Echo PCI subsystem card IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DARLA20			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GINA20			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define LAYLA20			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DARLA24			0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GINA24			0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define LAYLA24			0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MONA			0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MIA			0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define INDIGO			0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define INDIGO_IO		0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define INDIGO_DJ		0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DC8			0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define INDIGO_IOX		0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define INDIGO_DJX		0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ECHO3G			0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	Array sizes and so forth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * Sizes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ECHO_MAXAUDIOINPUTS	32	/* Max audio input channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ECHO_MAXAUDIOOUTPUTS	32	/* Max audio output channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ECHO_MAXAUDIOPIPES	32	/* Max number of input and output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 					 * pipes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define E3G_MAX_OUTPUTS		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ECHO_MAXMIDIJACKS	1	/* Max MIDI ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ECHO_MIDI_QUEUE_SZ 	512	/* Max MIDI input queue entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ECHO_MTC_QUEUE_SZ	32	/* Max MIDI time code input queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 					 * entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  * MIDI activity indicator timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MIDI_ACTIVITY_TIMEOUT_USEC	200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)    Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  * Clock numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define ECHO_CLOCK_INTERNAL		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ECHO_CLOCK_WORD			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ECHO_CLOCK_SUPER		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ECHO_CLOCK_SPDIF		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ECHO_CLOCK_ADAT			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ECHO_CLOCK_ESYNC		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ECHO_CLOCK_ESYNC96		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ECHO_CLOCK_MTC			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ECHO_CLOCK_NUMBER		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ECHO_CLOCKS			0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * Clock bit numbers - used to report capabilities and whatever clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * are being detected dynamically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ECHO_CLOCK_BIT_INTERNAL		(1 << ECHO_CLOCK_INTERNAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ECHO_CLOCK_BIT_WORD		(1 << ECHO_CLOCK_WORD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ECHO_CLOCK_BIT_SUPER		(1 << ECHO_CLOCK_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ECHO_CLOCK_BIT_SPDIF		(1 << ECHO_CLOCK_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ECHO_CLOCK_BIT_ADAT		(1 << ECHO_CLOCK_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ECHO_CLOCK_BIT_ESYNC		(1 << ECHO_CLOCK_ESYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ECHO_CLOCK_BIT_ESYNC96		(1 << ECHO_CLOCK_ESYNC96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ECHO_CLOCK_BIT_MTC		(1<<ECHO_CLOCK_MTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)    Digital modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  * Digital modes for Mona, Layla24, and Gina24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DIGITAL_MODE_NONE			0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DIGITAL_MODE_SPDIF_RCA			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DIGITAL_MODE_SPDIF_OPTICAL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define DIGITAL_MODE_ADAT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DIGITAL_MODE_SPDIF_CDROM		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DIGITAL_MODES				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * Digital mode capability masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA	(1 << DIGITAL_MODE_SPDIF_RCA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL	(1 << DIGITAL_MODE_SPDIF_OPTICAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define ECHOCAPS_HAS_DIGITAL_MODE_ADAT		(1 << DIGITAL_MODE_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_CDROM	(1 << DIGITAL_MODE_SPDIF_CDROM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define EXT_3GBOX_NC			0x01	/* 3G box not connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define EXT_3GBOX_NOT_SET		0x02	/* 3G box not detected yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ECHOGAIN_MUTED		(-128)	/* Minimum possible gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define ECHOGAIN_MINOUT		(-128)	/* Min output gain (dB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ECHOGAIN_MAXOUT		(6)	/* Max output gain (dB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ECHOGAIN_MININP		(-50)	/* Min input gain (0.5 dB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ECHOGAIN_MAXINP		(50)	/* Max input gain (0.5 dB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define PIPE_STATE_STOPPED	0	/* Pipe has been reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define PIPE_STATE_PAUSED	1	/* Pipe has been stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define PIPE_STATE_STARTED	2	/* Pipe has been started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define PIPE_STATE_PENDING	3	/* Pipe has pending start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct audiopipe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	volatile __le32 *dma_counter;	/* Commpage register that contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 					 * the current dma position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 					 * (lower 32 bits only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	u32 last_period;                /* Counter position last time a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 					 * period elapsed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	u32 last_counter;		/* Used exclusively by pcm_pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 					 * under PCM core locks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 					 * The last position, which is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 					 * to compute...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	u32 position;			/* ...the number of bytes tranferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 					 * by the DMA engine, modulo the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 					 * buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	short index;			/* Index of the first channel or <0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 					 * if hw is not configured yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	short interleave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	struct snd_dma_buffer sgpage;	/* Room for the scatter-gather list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	struct snd_pcm_hardware hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	struct snd_pcm_hw_constraint_list constr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	short sglist_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	char state;			/* pipe state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct audioformat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	u8 interleave;			/* How the data is arranged in memory:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 					 * mono = 1, stereo = 2, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	u8 bits_per_sample;		/* 8, 16, 24, 32 (24 bits left aligned) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	char mono_to_stereo;		/* Only used if interleave is 1 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 					 * if this is an output pipe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	char data_are_bigendian;	/* 1 = big endian, 0 = little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct echoaudio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	struct snd_pcm_substream *substream[DSP_MAXPIPES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	struct mutex mode_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	u16 num_digital_modes, digital_mode_list[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	u16 num_clock_sources, clock_source_list[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	unsigned int opencount;  /* protected by mode_mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	struct snd_kcontrol *clock_src_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	struct snd_pcm *analog_pcm, *digital_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	const char *card_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	unsigned long dsp_registers_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	struct resource *iores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	struct snd_dma_buffer commpage_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #ifdef ECHOCARD_HAS_MIDI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	struct snd_rawmidi_substream *midi_in, *midi_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	char tinuse;				/* Timer in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	char midi_full;				/* MIDI output buffer is full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	char can_set_rate;                      /* protected by mode_mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	char rate_set;                          /* protected by mode_mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	/* This stuff is used mainly by the lowlevel code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	struct comm_page *comm_page;	/* Virtual address of the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 					 * seen by DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	u32 pipe_alloc_mask;		/* Bitmask of allocated pipes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	u32 pipe_cyclic_mask;		/* Bitmask of pipes with cyclic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 					 * buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	u32 sample_rate;		/* Card sample rate in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	u8 digital_mode;		/* Current digital mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 					 * (see DIGITAL_MODE_*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	u8 spdif_status;		/* Gina20, Darla20, Darla24 - only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	u8 clock_state;			/* Gina20, Darla20, Darla24 - only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	u8 input_clock;			/* Currently selected sample clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 					 * source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	u8 output_clock;		/* Layla20 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	char meters_enabled;		/* VU-meters status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	char asic_loaded;		/* Set true when ASIC loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	char bad_board;			/* Set true if DSP won't load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	char professional_spdif;	/* 0 = consumer; 1 = professional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	char non_audio_spdif;		/* 3G - only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	char digital_in_automute;	/* Gina24, Layla24, Mona - only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	char has_phantom_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	char hasnt_input_nominal_level;	/* Gina3G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	char phantom_power;		/* Gina3G - only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	char has_midi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	char midi_input_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #ifdef ECHOCARD_ECHO3G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	/* External module -dependent pipe and bus indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	char px_digital_out, px_analog_in, px_digital_in, px_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	char bx_digital_out, bx_analog_in, bx_digital_in, bx_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	char nominal_level[ECHO_MAXAUDIOPIPES];	/* True == -10dBV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 						 * False == +4dBu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	s8 input_gain[ECHO_MAXAUDIOINPUTS];	/* Input level -50..+50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 						 * unit is 0.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	s8 output_gain[ECHO_MAXAUDIOOUTPUTS];	/* Output level -128..+6 dB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 						 * (-128=muted) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	s8 monitor_gain[ECHO_MAXAUDIOOUTPUTS][ECHO_MAXAUDIOINPUTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		/* -128..+6 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	s8 vmixer_gain[ECHO_MAXAUDIOOUTPUTS][ECHO_MAXAUDIOOUTPUTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		/* -128..+6 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	u16 digital_modes;		/* Bitmask of supported modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 					 * (see ECHOCAPS_HAS_DIGITAL_MODE_*) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	u16 input_clock_types;		/* Suppoted input clock types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	u16 output_clock_types;		/* Suppoted output clock types -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 					 * Layla20 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	u16 device_id, subdevice_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	u16 *dsp_code;			/* Current DSP code loaded,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 					 * NULL if nothing loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	short dsp_code_to_load;		/* DSP code to load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	short asic_code;		/* Current ASIC code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	u32 comm_page_phys;			/* Physical address of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 						 * memory seen by DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	u32 __iomem *dsp_registers;		/* DSP's register base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	u32 active_mask;			/* Chs. active mask or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 						 * punks out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	const struct firmware *fw_cache[8];	/* Cached firmwares */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #ifdef ECHOCARD_HAS_MIDI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	u16 mtc_state;				/* State for MIDI input parsing state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	u8 midi_buffer[MIDI_IN_BUFFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int init_dsp_comm_page(struct echoaudio *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int init_line_levels(struct echoaudio *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int free_pipes(struct echoaudio *chip, struct audiopipe *pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int load_firmware(struct echoaudio *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int wait_handshake(struct echoaudio *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int send_vector(struct echoaudio *chip, u32 command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int get_firmware(const struct firmware **fw_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 			struct echoaudio *chip, const short fw_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static void free_firmware(const struct firmware *fw_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 			  struct echoaudio *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #ifdef ECHOCARD_HAS_MIDI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int enable_midi_input(struct echoaudio *chip, char enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static void snd_echo_midi_output_trigger(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 			struct snd_rawmidi_substream *substream, int up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int midi_service_irq(struct echoaudio *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int snd_echo_midi_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 				struct echoaudio *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static inline void clear_handshake(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	chip->comm_page->handshake = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static inline u32 get_dsp_register(struct echoaudio *chip, u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	return readl(&chip->dsp_registers[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static inline void set_dsp_register(struct echoaudio *chip, u32 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 				    u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	writel(value, &chip->dsp_registers[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Pipe and bus indexes. PX_* and BX_* are defined as chip->px_* and chip->bx_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) for 3G cards because they depend on the external box. They are integer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) constants for all other cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) Never use those defines directly, use the following functions instead. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static inline int px_digital_out(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	return PX_DIGITAL_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static inline int px_analog_in(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	return PX_ANALOG_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static inline int px_digital_in(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	return PX_DIGITAL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static inline int px_num(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	return PX_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static inline int bx_digital_out(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	return BX_DIGITAL_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static inline int bx_analog_in(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	return BX_ANALOG_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static inline int bx_digital_in(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	return BX_DIGITAL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static inline int bx_num(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	return BX_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static inline int num_pipes_out(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	return px_analog_in(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static inline int num_pipes_in(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	return px_num(chip) - px_analog_in(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static inline int num_busses_out(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	return bx_analog_in(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static inline int num_busses_in(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	return bx_num(chip) - bx_analog_in(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static inline int num_analog_busses_out(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	return bx_digital_out(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static inline int num_analog_busses_in(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	return bx_digital_in(chip) - bx_analog_in(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static inline int num_digital_busses_out(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	return num_busses_out(chip) - num_analog_busses_out(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static inline int num_digital_busses_in(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	return num_busses_in(chip) - num_analog_busses_in(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* The monitor array is a one-dimensional array; compute the offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)  * into the array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static inline int monitor_index(const struct echoaudio *chip, int out, int in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	return out * num_busses_in(chip) + in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #endif /* _ECHOAUDIO_H_ */