^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA driver for Echoaudio soundcards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2003-2004 Giuliano Pochini <pochini@shiny.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define ECHO3G_FAMILY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define ECHOCARD_ECHO3G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define ECHOCARD_NAME "Echo3G"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ECHOCARD_HAS_MONITOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ECHOCARD_HAS_ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ECHOCARD_HAS_INPUT_NOMINAL_LEVEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ECHOCARD_HAS_OUTPUT_NOMINAL_LEVEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ECHOCARD_HAS_SUPER_INTERLEAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ECHOCARD_HAS_DIGITAL_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ECHOCARD_HAS_DIGITAL_MODE_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ECHOCARD_HAS_ADAT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ECHOCARD_HAS_EXTERNAL_CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ECHOCARD_HAS_STEREO_BIG_ENDIAN32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ECHOCARD_HAS_MIDI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ECHOCARD_HAS_PHANTOM_POWER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Pipe indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PX_ANALOG_OUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PX_DIGITAL_OUT chip->px_digital_out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PX_ANALOG_IN chip->px_analog_in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PX_DIGITAL_IN chip->px_digital_in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PX_NUM chip->px_num
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Bus indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BX_ANALOG_OUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BX_DIGITAL_OUT chip->bx_digital_out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BX_ANALOG_IN chip->bx_analog_in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BX_DIGITAL_IN chip->bx_digital_in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BX_NUM chip->bx_num
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <sound/rawmidi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include "echoaudio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_FIRMWARE("ea/loader_dsp.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_FIRMWARE("ea/echo3g_dsp.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MODULE_FIRMWARE("ea/3g_asic.fw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FW_361_LOADER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FW_ECHO3G_DSP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FW_3G_ASIC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct firmware card_fw[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {0, "loader_dsp.fw"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {0, "echo3g_dsp.fw"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {0, "3g_asic.fw"}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct pci_device_id snd_echo_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {0x1057, 0x3410, 0xECC0, 0x0100, 0, 0, 0}, /* Echo 3G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct snd_pcm_hardware pcm_hardware_skel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SNDRV_PCM_INFO_SYNC_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .formats = SNDRV_PCM_FMTBIT_U8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SNDRV_PCM_FMTBIT_S24_3LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SNDRV_PCM_FMTBIT_S32_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SNDRV_PCM_FMTBIT_S32_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .rates = SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SNDRV_PCM_RATE_96000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) SNDRV_PCM_RATE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .rate_min = 32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .rate_max = 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .buffer_bytes_max = 262144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .period_bytes_min = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .period_bytes_max = 131072,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .periods_max = 220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #include "echo3g_dsp.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #include "echoaudio_dsp.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #include "echoaudio_3g.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #include "echoaudio.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #include "midi.c"
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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