^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Copyright Echo Digital Audio Corporation (c) 1998 - 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) www.echoaudio.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) This file is part of Echo Digital Audio's generic driver library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Echo Digital Audio's generic driver library is free software;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) you can redistribute it and/or modify it under the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) the GNU General Public License as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Foundation, Inc., 59 Temple Place - Suite 330, Boston,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MA 02111-1307, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Translation from C++ and adaptation for use in ALSA-Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) were made by Giuliano Pochini <pochini@shiny.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (snd_BUG_ON((subdevice_id & 0xfff0) != DARLA24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if ((err = init_dsp_comm_page(chip))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "init_hw: could not initialize DSP comm page\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) chip->device_id = device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) chip->subdevice_id = subdevice_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) chip->bad_board = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) chip->dsp_code_to_load = FW_DARLA24_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Since this card has no ASIC, mark it as loaded so everything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) works OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) chip->asic_loaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) chip->input_clock_types = ECHO_CLOCK_BIT_INTERNAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ECHO_CLOCK_BIT_ESYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if ((err = load_firmware(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) chip->bad_board = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int set_mixer_defaults(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return init_line_levels(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static u32 detect_input_clocks(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 clocks_from_dsp, clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Map the DSP clock detect bits to the generic driver clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) detect bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) clock_bits = ECHO_CLOCK_BIT_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (clocks_from_dsp & GLDM_CLOCK_DETECT_BIT_ESYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) clock_bits |= ECHO_CLOCK_BIT_ESYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* The Darla24 has no ASIC. Just do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int load_asic(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int set_sample_rate(struct echoaudio *chip, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clock = GD24_96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clock = GD24_88200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clock = GD24_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clock = GD24_44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clock = GD24_32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clock = GD24_22050;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clock = GD24_16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case 11025:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) clock = GD24_11025;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clock = GD24_8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "set_sample_rate: Error, invalid sample rate %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "set_sample_rate: %d clock %d\n", rate, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) chip->sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Override the sample rate if this card is set to Echo sync. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (chip->input_clock == ECHO_CLOCK_ESYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) clock = GD24_EXT_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) chip->comm_page->gd_clock_state = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return send_vector(chip, DSP_VC_SET_GD_AUDIO_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int set_input_clock(struct echoaudio *chip, u16 clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (snd_BUG_ON(clock != ECHO_CLOCK_INTERNAL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) clock != ECHO_CLOCK_ESYNC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) chip->input_clock = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return set_sample_rate(chip, chip->sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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