^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Copyright Echo Digital Audio Corporation (c) 1998 - 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) www.echoaudio.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) This file is part of Echo Digital Audio's generic driver library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Echo Digital Audio's generic driver library is free software;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) you can redistribute it and/or modify it under the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) the GNU General Public License as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Foundation, Inc., 59 Temple Place - Suite 330, Boston,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MA 02111-1307, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Translation from C++ and adaptation for use in ALSA-Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) were made by Giuliano Pochini <pochini@shiny.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (snd_BUG_ON((subdevice_id & 0xfff0) != DARLA20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if ((err = init_dsp_comm_page(chip))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "init_hw: could not initialize DSP comm page\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) chip->device_id = device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) chip->subdevice_id = subdevice_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) chip->bad_board = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) chip->dsp_code_to_load = FW_DARLA20_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) chip->spdif_status = GD_SPDIF_STATUS_UNDEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) chip->clock_state = GD_CLOCK_UNDEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Since this card has no ASIC, mark it as loaded so everything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) works OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) chip->asic_loaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) chip->input_clock_types = ECHO_CLOCK_BIT_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if ((err = load_firmware(chip)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) chip->bad_board = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int set_mixer_defaults(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return init_line_levels(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* The Darla20 has no external clock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static u32 detect_input_clocks(const struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return ECHO_CLOCK_BIT_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* The Darla20 has no ASIC. Just do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int load_asic(struct echoaudio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int set_sample_rate(struct echoaudio *chip, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 clock_state, spdif_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (wait_handshake(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) clock_state = GD_CLOCK_44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) spdif_status = GD_SPDIF_STATUS_44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clock_state = GD_CLOCK_48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) spdif_status = GD_SPDIF_STATUS_48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clock_state = GD_CLOCK_NOCHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) spdif_status = GD_SPDIF_STATUS_NOCHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (chip->clock_state == clock_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clock_state = GD_CLOCK_NOCHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (spdif_status == chip->spdif_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) spdif_status = GD_SPDIF_STATUS_NOCHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) chip->comm_page->sample_rate = cpu_to_le32(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) chip->comm_page->gd_clock_state = clock_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) chip->comm_page->gd_spdif_status = spdif_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) chip->comm_page->gd_resampler_state = 3; /* magic number - should always be 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Save the new audio state if it changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (clock_state != GD_CLOCK_NOCHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) chip->clock_state = clock_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (spdif_status != GD_SPDIF_STATUS_NOCHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) chip->spdif_status = spdif_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) chip->sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clear_handshake(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return send_vector(chip, DSP_VC_SET_GD_AUDIO_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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